DESIGN OF LPDDR3 MEMORY CONTROLLER WITH AXI

COMPLIANT
1
POOJASHREE, 2SANJAY ELIGAR, 3YOGESH SONI

Abstract- The paper presents the implementation of compliant LPDDR3 memory controller. It discusses the overall
architecture of the LPDDR3 controller. As system bandwidths continue to increase, memory technologies have been
optimized for higher speeds and performance. The next generation family of Low Power Double Data Rate (LPDDR)
RAMs is LPDDR3 RAM. LPDDR3 RAMs offer numerous advantages compared to LPDDR2. Low Power Double Data
Rate 3 (LPDDR3) SDRAM Controller is designed for use in applications requiring high memory throughput, high clock
rates and full programmability. LPDDR3 was designed specifically for mobile devices like smart phones, tablets and ultra-
books. These memory devices are rapidly developing, with high density, high memory bandwidth and low device cost.
However, because of the high-speed interface technology and complex instruction-based memory access control, a specific
purpose memory controller is necessary for optimizing the memory access trade off.

Index Terms- LPDDR3 memories, LPDDR3 Controller, AXI interface.

I. INTRODUCTION II. BLOCK DIAGRAM OF LPDDR3 MEMORY

CONTROLLER
This LPDDR3 controller is the AXI compliant which
permits access of LPDDR3 memory content through
AXI Bus interface. The handshaking mechanism is
mainly used to meet the requirement of AXI bus
protocol LPDDR3 RAM is a modern kind of dynamic
random access memory (DRAM) with a high
bandwidth interface. The LPDDR3 controller works
as an important bridge between the AXI host and
DDR3 memory. It takes care of the LPDDR3
initialization and various timing requirements of the
LPDDR3 memory. It is the 3rd generation of LPDDR
memories, featuring higher performance and lower Fig .1: Block diagram of low power DDR3 controller.
power consumption with earlier generations.
LPDDR3 Memory Controller has following features:
LPDDR3 offers a higher data rate, improved 1. Compliant to JESD209-3 LPDDR3 Spec.
bandwidth and power efficiency, and higher memory 2. Should support LPDDR3 addressing up to16Gb.
densities over LPDDR2. LPDDR3 achieves a data 3. Supports AXI Slave I/F.
rate of 1600Mbps (LPDDR2 achieves 1066Mbps) 4. Supports AXI Address width as 32 bits.
through write-leveling and CA training, on-die 5. Supports AXI Data width as 32 bits.
termination (ODT), and low-I/O capacitance. 6. Supports Direct Signal I/F for the Configuration &
Status Reporting.
LPDDR3 will preserve the power-efficient features 7. Supports all applicable transfer types, bus types,
and signaling interface of LPDDR2, allowing for fast response types etc. on AXI Slave I/F.
clock stop/start, low-power self-refresh, and smart 8. Supports out of ordering depth of 1.
array management. As with LPDDR2, LPDDR3 9. Doesn’t support multiple outstanding transactions.
supports both package-on-package (Pop) and discrete 10. Doesn’t support Exclusive access type of
packaging types to meet form factor requirements of transactions.
various mobile devices. 11. Doesn’t support Locked Transfers.
12. Fully Parameterized
Write-leveling and CA training allow the memory 13. Developed to strict RTL coding & IP Reuse
controller to compensate for signal skew, ensuring guidelines
that data input setup and hold timing as well as 14. One step automated IP test is provided to check
command and address input timing requirements are that IP has been unpacked correctly & contains
met while operating at the fastest input bus speeds. complete package.
ODT enables a light termination to LPDDR3 data 15. Fully Synthesizable.
lanes to improve high-speed signaling with minimal
impact on power consumption system operation and The Low power DDR3 memory controller has
pin count. following blocks. - AXI Interface.

Proceedings of 07th IRF International Conference, 22nd June-2014, Bengaluru, India, ISBN: 978-93-84209-29-2
33
 Design of LPDDR3 Memory Controller With AXI Compliant

- Initialization sequence state machine. C. User Interface:

- User Interface. It includes timing registers for initialization block and
- LPDDR3 Memory Controller state machine. memory controller each of 32 bits.

A. AXI Interface: It has five different channels 1. D. LPDDR3 Memory Controller state machine:
Write address 2. Write data 3. Write response 4. Read
address 5.
Read data.
Output of the write data channel and read data
channel are connected to write and read FIFO
respectively.
The AMBA AXI protocol is targeted at high-
performance, high-frequency system design and
includes a number of features that make it suitable for
a high-speed submicron interconnects. The key
features of the AXI protocol are:
Separate address/control and data phase.
Support for unaligned data transfers using byte Fig .3: Controller state machine
strobes.
Burst-based transactions with only start address Controller can go from IDLE to many different states.
issue.
ACTIVE: The ACTIVATE command must be
B. - Initialization sequence state machine: applied before any READ or WRITE operation can
In order to successfully read from a DDR memory a be executed. The device can accept a READ or
lengthy initialization sequence involving the WRITE command after the ACTIVATE command is
programming of the device’s mode registers must be issued. After a bank has been activated it must be
done, data can then be written to the device and only precharged before another ACTIVATE command can
then can a read instruction be executed which is the be applied to the same bank. Row addresses are used
first time in the test sequence that the test engineer to determine which row to activate in the selected
will be able to validate that the preceding bank.
initialization sequence and write commands have in
fact executed successfully. After the initialization READ and WRITE: After a bank has been
sequence is complete, the device is ready for any activated, a read or write cycle can be executed. The
valid command. LPDDR3 SDRAM provides a fast column access
operation. A single Read or Write Command will
initiate a burst read or write operation on successive
clock cycles. Burst interrupts are not allowed.

PRECHARGE: The PRECHARGE command is

used to precharge or close a bank that has been
activated. The PRECHARGE command can be used
to precharge each bank independently or all banks
simultaneously.

REFRESH: A bank must be idle before it can be

refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
SELF REFRESH: Once the SDRAM has entered
Self Refresh mode, all of the external signals except
CKE, are “don’t care”. The clock is internally
disabled during Self Refresh Operation to save
power.

IDLE POWER DOWN: If power-down occurs

when all banks are idle, this mode is referred to as
idle power-down.

ACTIVE POWER DOWN: if power-down occurs

when there is a row active in any bank, this mode is
Fig 2: Initialization state machine referred toas active power-down.

Proceedings of 07th IRF International Conference, 22nd June-2014, Bengaluru, India, ISBN: 978-93-84209-29-2
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 Design of LPDDR3 Memory Controller With AXI Compliant

E. Functional Description
LPDDR3-SDRAM is a high-speed synchronous
DRAM
device internally configured as an 8-bank memory.
These devices contain the following number of bits:
4 GB has 4,294,967,296 bits
8 GB has 8,589,934,592 bits
16 GB has 17,179,869,184 bits
32 GB has 34,359,738,368 bits

LPDDR3 devices use double data rate architecture on

the Command/Address (CA) bus to reduce the
number of input pins in the system. The 10-bit CA
bus contains command, address, and bank
information. Each command uses one clock cycle,
during which command information is transferred on
both the positive and negative edge of the clock.
These devices also use double data rate architecture
on the DQ pins to achieve high speed operation. The
double data rate architecture is essentially an 8n
prefetch architecture with an interface designed to
transfer two data bits per DQ every clock cycle at the
I/O pins. A single read or write access for the
LPDDR3 SDRAM effectively consists of a single 8n- IV.RESULTS
bit wide, one clock cycle data transfer at the internal
DRAM core and eight corresponding n-bit wide, one The below figures are showing snapshot of the
half- clock-cycle data transfers at the I/O pins. LPDDR3 Controller operation in various modes. The
design has been coded in “Verilog HDL” language
Read and write accesses to the LPDDR3 SDRAMs simulation is done using Modelsim by Mentor
are burst oriented; accesses start at a selected location graphics tool and Active-HDL 9.1.
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the A. Initialization
registration of an Activate command, which is then
followed by a Read or Write command. The address
and BA bits registered coincident with the Activate
command are used to select the row and the bank to
be accessed. The address bits registered coincident
with the Read or Write command are used to select
the bank and the starting column location for the
burst access.

F. Address Mapping
The input address comes along with the AXI
command. 32 bit AXI address is divided into row,
column and bank address as follows Fig.4: Simulation waveform of initialization sequence.

Column address= AXI address [11:0] B.Write Address

Row address= AXI address [26:12]
Bank address=AXI address [29:27]
III IMPLIMENTATION
The synthesized details of the design are as shown in
table 1 and 2. Table1: Target device
Table2: Device Utilization summary
The Table 2 shows the Module name and target
device used.
It also shows the place and route status and number of
errors & warnings.
Table 3 shows the device utilization i.e. number of
registers,
number of PIO registers and number of slices used.
Fig.5: Simulation waveform of write address.
th nd
Proceedings of 07 IRF International Conference, 22 June-2014, Bengaluru, India, ISBN: 978-93-84209-29-2
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 Design of LPDDR3 Memory Controller With AXI Compliant

C.Write Data E.Read Address

Fig.8: Simulation waveform of read address.

CONCLUSION
Fig.6: Simulation waveform of write data
In this paper the DDR3 controller is designed using
D.Write Response Verilog HDL. This design is simulated in Modelsim
by Mentor graphics tool and successfully synthesized
in gVim, also in RTL compiler by Cadence EDA
tool.

REFERENCES

[1] www.altera.com/literature/ug/ug_altmemphy.p df, External

DDR Memory PHY Interface Mega Function User Guide
(ALTMEMPHY), accessed on 23 Feb. 2009

[2] LPDDR3 SDRAM Specification (JESD209-3), JEDEC

Standard, JEDEC Solid State TechnologyAssociation, May.
2012.

[3] ARM, AMBA Specifications (Rev2.0). [Online]. Available

at <http://www.arm.com>, 1999.

[4] http://en.wikipedia.org/wiki/Advanced_Microc ntroller_

Fig.7: Simulation waveform of write response. Bus_ Architecture

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Proceedings of 07th IRF International Conference, 22nd June-2014, Bengaluru, India, ISBN: 978-93-84209-29-2
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