17.

4 TIMER IC UNIT OPERATION

Another popular analog–digital integrated circuit is the versatile 555 timer. The IC is
made of a combination of linear comparators and digital flip-flops as described in
Fig. 17.16. The entire circuit is usually housed in an 8-pin package as specified in
Fig. 17.16. A series connection of three resistors sets the reference voltage levels to
the two comparators at 2VCC/3 and VCC/3, the output of these comparators setting or
resetting the flip-flop unit. The output of the flip-flop circuit is then brought out
through an output amplifier stage. The flip-flop circuit also operates a transistor in-
side the IC, the transistor collector usually being driven low to discharge a timing ca-
pacitor.

VCC Threshold
8 6

R +
Control 5 ( 23 VCC) 1
voltage –
3
Output Output
R F/F
stage
( 13 VCC)
+ 7
2 Discharge

R –
1 2
Trigger
input 4
Figure 17.16 Details of 555
timer IC. Reset Vref

Astable Operation
One popular application of the 555 timer IC is as an astable multivibrator or clock
circuit. The following analysis of the operation of the 555 as an astable circuit in-
cludes details of the different parts of the unit and how the various inputs and out-
puts are utilized. Figure 17.17 shows an astable circuit built using an external resis-
tor and capacitor to set the timing interval of the output signal.

Figure 17.17 Astable

multivibrator using 555 IC.

732
 Capacitor C charges toward VCC through external resistors RA and RB. Referring
to Fig. 17.17, the capacitor voltage rises until it goes above 2VCC/3. This voltage is
the threshold voltage at pin 6, which drives comparator 1 to trigger the flip-flop so
that the output at pin 3 goes low. In addition, the discharge transistor is driven on,
causing the output at pin 7 to discharge the capacitor through resistor RB. The ca-
pacitor voltage then decreases until it drops below the trigger level (VCC/3). The flip-
flop is triggered so that the output goes back high and the discharge transistor is turned
off, so that the capacitor can again charge through resistors RA and RB toward VCC.
Figure 17.18a shows the capacitor and output waveforms resulting from the astable
circuit. Calculation of the time intervals during which the output is high and low can
be made using the relations

Thigh  0.7(RA  RB)C (17.3)

Tlow  0.7RBC (17.4)

The total period is
T  period  Thigh  Tlow (17.5)
The frequency of the astable circuit is then calculated using*

1 1.44
f     (17.6)
T (RA  2RB)C

Figure 17.18 Astable multivibrator for Example 17.1: (a) circuit; (b) waveforms.

*The period can be directly calculated from

T  0.693(RA  2RB)C  0.7(RA  2RB)C
and the frequency from
1.44
f  
(RA  2RB)C

17.4 Timer IC Unit Operation 733

 EXAMPLE 17.1 Determine the frequency and draw the output waveform for the circuit of Fig. 17.18a.

Solution
Using Eqs. (17.3) through (17.6) yields
Thigh  0.7(RA  RB)C  0.7(7.5  103  7.5  103)(0.1  106)

 1.05 ms

Tlow  0.7RBC  0.7(7.5  103)(0.1  106)  0.525 ms

T  Thigh  Tlow  1.05 ms  0.525 ms  1.575 ms

1 1
f      635 Hz
T 1.575  103
The waveforms are drawn in Fig. 17.18b.

Monostable Operation
The 555 timer can also be used as a one-shot or monostable multivibrator circuit, as
shown in Fig. 17.19. When the trigger input signal goes negative, it triggers the one-
shot, with output at pin 3 then going high for a time period
Thigh  1.1RAC (17.7)
Referring back to Fig. 17.16, the negative edge of the trigger input causes compara-
tor 2 to trigger the flip-flop, with the output at pin 3 going high. Capacitor C charges
toward VCC through resistor RA. During the charge interval, the output remains high.
When the voltage across the capacitor reaches the threshold level of 2VCC/3, com-
parator 1 triggers the flip-flop, with output going low. The discharge transistor also
goes low, causing the capacitor to remain at near 0 V until triggered again.
Figure 17.19b shows the input trigger signal and the resulting output waveform
for the 555 timer operated as a one-shot. Time periods for this circuit can range from
microseconds to many seconds, making this IC useful for a range of applications.

Figure 17.19 Operation of 555 timer as one-shot: (a) circuit; (b) waveforms.

734 Chapter 17 Linear-Digital ICs

Determine the period of the output waveform for the circuit of Fig. 17.20 when trig- EXAMPLE 17.2
gered by a negative pulse.

Figure 17.20 Monostable cir-

cuit for Example 17.2.

Solution
Using Eq. (17.7), we obtain
Thigh  1.1RAC  1.1(7.5  103)(0.1  106)  0.825 ms

17.5 VOLTAGE-CONTROLLED
OSCILLATOR
A voltage-controlled oscillator (VCO) is a circuit that provides a varying output sig-
nal (typically of square-wave or triangular-wave form) whose frequency can be ad-
justed over a range controlled by a dc voltage. An example of a VCO is the 566 IC
unit, which contains circuitry to generate both square-wave and triangular-wave sig-
nals whose frequency is set by an external resistor and capacitor and then varied by
an applied dc voltage. Figure 17.21a shows that the 566 contains current sources to
charge and discharge an external capacitor C1 at a rate set by external resistor R1 and
the modulating dc input voltage. A Schmitt trigger circuit is used to switch the cur-
rent sources between charging and discharging the capacitor, and the triangular volt-
age developed across the capacitor and square wave from the Schmitt trigger are pro-
vided as outputs through buffer amplifiers.
Figure 17.21b shows the pin connection of the 566 unit and a summary of for-
mula and value limitations. The oscillator can be programmed over a 10-to-1 fre-
quency range by proper selection of an external resistor and capacitor, and then mod-
ulated over a 10-to-1 frequency range by a control voltage, VC.
A free-running or center-operating frequency, fo, can be calculated from

V  VC
 
2
fo     (17.8)
R1C1 V
with the following practical circuit value restrictions:

1. R1 should be within the range 2 k

R1
20 k.
2. VC should be within range 34V
VC
V.

17.5 Voltage-Controlled Oscillator 735

Figure 17.21 A 566 function
generator: (a) block diagram;
(b) pin configuration and summary
of operating data.

3. fo should be below 1 MHz.

4. V should range between 10 V and 24 V.

Figure 17.22 shows an example in which the 566 function generator is used to
provide both square-wave and triangular-wave signals at a fixed frequency set by R1,
C1, and VC. A resistor divider R2 and R3 sets the dc modulating voltage at a fixed
value

Figure 17.22 Connection of

566 VCO unit.

736 Chapter 17 Linear-Digital ICs

 R3 10 k
VC   V  (12 V)  10.4 V
R2  R3 1.5 k  10 k
(which falls properly in the voltage range 0.75V  9 V and V  12 V). Using Eq.
(17.8) yields
12  10.4
 
2
fo     32.5 kHz
(10  103)(820  1012) 12
The circuit of Fig. 17.23 shows how the output square-wave frequency can be ad-
justed using the input voltage, VC, to vary the signal frequency. Potentiometer R3 al-
lows varying VC from about 9 V to near 12 V, over the full 10-to-1 frequency range.
With the potentiometer wiper set at the top, the control voltage is
R3  R4 5 k  18 k
VC   (V)  (12 V)  11.74 V
R2  R3  R4 510   5 k  18 k
resulting in a lower output frequency of
12  11.74
 
2
fo     19.7 kHz
(10  103)(220  1012) 12

Figure 17.23 Connection of

566 as a VCO unit.

With the wiper arm of R3 set at the bottom, the control voltage is
R4  18 k
VC  (V )  (12 V)  9.19 V
R2  R3  R4 510   5 k  18 k
resulting in an upper frequency of
12  9.19
 
2
fo     212.9 kHz
(10  103)(220  1012) 12
The frequency of the output square wave can then be varied using potentiometer R3
over a frequency range of at least 10 to 1.
Rather than varying a potentiometer setting to change the value of VC, an input
modulating voltage, Vin, can be applied as shown in Fig. 17.24. The voltage divider
sets VC at about 10.4 V. An input ac voltage of about 1.4 V peak can drive VC around
the bias point between voltages of 9 and 11.8 V, causing the output frequency to vary
over about a 10-to-1 range. The input signal Vin thus frequency-modulates the output
voltage around the center frequency set by the bias value of VC  10.4 V ( fo 
121.2 kHz).

17.5 Voltage-Controlled Oscillator 737

 Figure 17.24 Operation of
VCO with frequency-modulating
input.

17.6 PHASE-LOCKED LOOP

A phase-locked loop (PLL) is an electronic circuit that consists of a phase detector,
a low-pass filter, and a voltage-controlled oscillator connected as shown in Fig. 17.25.
Common applications of a PLL include: (1) frequency synthesizers that provide mul-
tiples of a reference signal frequency [e.g., the carrier frequency for the multiple chan-
nels of a citizens’ band (CB) unit or marine-radio-band unit can be generated using
a single-crystal-controlled frequency and its multiples generated using a PLL]; (2)
FM demodulation networks for FM operation with excellent linearity between the in-
put signal frequency and the PLL output voltage; (3) demodulation of the two data
transmission or carrier frequencies in digital-data transmission used in frequency-shift
keying (FSK) operation; and (4) a wide variety of areas including modems, teleme-
try receivers and transmitters, tone decoders, AM detectors, and tracking filters.
An input signal, Vi, and that from a VCO, Vo, are compared by a phase comparator
(refer to Fig. 17.25) providing an output voltage, Ve, that represents the phase differ-
ence between the two signals. This voltage is then fed to a low-pass filter that pro-

Figure 17.25 Block diagram of basic phase-locked loop (PLL).

738 Chapter 17 Linear-Digital ICs

vides an output voltage (amplified if necessary) that can be taken as the output volt-
age from the PLL and is used internally as the voltage to modulate the VCO’s fre-
quency. The closed-loop operation of the circuit is to maintain the VCO frequency
locked to that of the input signal frequency.

Basic PLL Operation

The basic operation of a PLL circuit can be explained using the circuit of Fig. 17.25
as reference. We will first consider the operation of the various circuits in the phase-
locked loop when the loop is operating in lock (the input signal frequency and the
VCO frequency are the same). When the input signal frequency is the same as that
from the VCO to the comparator, the voltage, Vd, taken as output is the value needed
to hold the VCO in lock with the input signal. The VCO then provides output of a
fixed-amplitude square-wave signal at the frequency of the input. Best operation is
obtained if the VCO center frequency, fo, is set with the dc bias voltage midway in
its linear operating range. The amplifier allows this adjustment in dc voltage from that
obtained as output of the filter circuit. When the loop is in lock, the two signals to
the comparator are of the same frequency, although not necessarily in phase. A fixed
phase difference between the two signals to the comparator results in a fixed dc volt-
age to the VCO. Changes in the input signal frequency then result in change in the
dc voltage to the VCO. Within a capture-and-lock frequency range, the dc voltage
will drive the VCO frequency to match that of the input.
While the loop is trying to achieve lock, the output of the phase comparator con-
tains frequency components at the sum and difference of the signals compared. A low-
pass filter passes only the lower-frequency component of the signal so that the loop
can obtain lock between input and VCO signals.
Owing to the limited operating range of the VCO and the feedback connection of
the PLL circuit, there are two important frequency bands specified for a PLL. The
capture range of a PLL is the frequency range centered about the VCO free-running
frequency, fo, over which the loop can acquire lock with the input signal. Once the
PLL has achieved capture, it can maintain lock with the input signal over a somewhat
wider frequency range called the lock range.

Applications
The PLL can be used in a wide variety of applications, including (1) frequency de-
modulation, (2) frequency synthesis, and (3) FSK decoders. Examples of each of these
follow.

FREQUENCY DEMODULATION
FM demodulation or detection can be directly achieved using the PLL circuit. If
the PLL center frequency is selected or designed at the FM carrier frequency, the fil-
tered or output voltage of the circuit of Fig. 17.25 is the desired demodulated volt-
age, varying in value proportional to the variation of the signal frequency. The PLL
circuit thus operates as a complete intermediate-frequency (IF) strip, limiter, and de-
modulator as used in FM receivers.
One popular PLL unit is the 565, shown in Fig. 17.26a. The 565 contains a phase
detector, amplifier, and voltage-controlled oscillator, which are only partially con-
nected internally. An external resistor and capacitor, R1 and C1, are used to set the
free-running or center frequency of the VCO. Another external capacitor, C2, is used
to set the low-pass filter passband, and the VCO output must be connected back as
input to the phase detector to close the PLL loop. The 565 typically uses two power
supplies, V and V.

17.6 Phase-Locked Loop 739