BCA-305 Computer Architecture

Unit 1- Introduction
Dr. Santosh Kumar
Lucknow Public College of
Professional Studies
 General Register Organisation
• General Purpose Register(GPR) can be in
generally 8 to 16 bits.
• Registers are temporary storage units made up
of Integrated Circuits (IC’s) of a computer that
keep data as well as instructions in binary 0 and
1 form.
• ALU performs operation on data stored in
these GPRs and also stores results in these
registers only.
 General Register Organisation
• There are few special purpose address registers.
• Mainly are Program Counter (PC) and Stack Pointer
(SP).
• A special simple ALU can be attached as an address
generation logic performing the simple fixed-point
computations.
• The inputs to the CU are from the IR(Instruction
Register) that contains the operation code of the
instruction to be executed from status register
which help in generating proper control signals on
branch operation.
 General Register Organisation
• The system bus plays the role of communication media.
• There are several intermediate buffer registers also
which help in intermediate storage of information.
• In this organisation of CPU, parallelism can be
implemented within the ALU operation or through the
overlapped operations of data processing and program
CU.
• One of the key differences among various computers is
the difference in their register sets.
• Some computers have very large while some has
smaller sets.
Implementation of Common Bus using MUX
• Common bus organisation is a very efficient method of
interconnecting all the units of Computer System.
• If a large no. of registers are included in processor unit,
common bus system is needed.
• In this organisation, the registers communicate with
each other not only for direct data transfers but also
while performing various micro-operations.
• Acc. To the diag. , 7 registers are used for GPR.
• Output of each register is connected to 2 MUXs inputs.
• 3 select lines are used to select any one of the 7
registers and contents of selected registers are supplied
to the inputs of ALU.
 Implementation of Common Bus using MUX
• The buses A and B are used to form the inputs to
the common ALU.
• The operation to be performed is selected in the
ALU and is used to determine the arithmetic or logic
micro-operation by using function select lines.
• The result of the micro-operation is available as
output data and also goes into the Inputs of all the
registers.
• Any one of the destination register receives the
information from the output bus which is selected
by a decoder.
 Implementation of Common Bus using MUX
• Selector Inputs for CU
• MUX A Selector (SEL A): To place the contents of R1
into bus A
• MUX B Selector (SEL B): To place the contents of R2
into bus B
• ALU operation Selector (OPR): To provide the
arithmetic addition A + B
• Decoder Destinatin Selector ( Sel D): To transfer the
contents of the output bus into R3.
• Control Word: It is a group of binary bits which are
assigned and formatted to perform the specified
operation.
 Stack Organisations
• A stack is an ordered set of elements only one of
which can be accessed at a time.
• Last In First Out (LIFO)
• 2 Operations performed
PUSH and POP
Stack Implementation in 2 ways:
1. Register Stack
2. Memory Stack
 Stack Organisations
1. Register Stack:
1) Implementation of Push operation
Step1: SP SP + 1; Increment Stack Pointer
Step2: M[SP] DR; Write item on top of the stack
Step3: If (SP==0) then (FULL  1); Check if stack is full
Step4: Empty  0; Mark Stack not empty
2). Implementation of POP operation
Step1: DR  M[SP]; Read item from top of the stack
Step2: SP SP - 1; Decrement stack Pointer
Step3: If (SP==0) then (Empty  1); Check if stack is empty
Step4: FULL  0; Mark Stack not full
 Stack Organisations
2. Memory Stack:
• A stack can be implemented by a RAM attached to a
CPU.
• A contiguous block of locations is reserved in RAM
for the stack.
Addresses are needed for Proper Operation
• Stack Pointer: It contains the address of the TOS.
• Stack Base: It contains the address of the bottom
location in the reserved block.
• Stack Limit: It contains the address of the other end
of the reserved block. (refer diag.)
 Addressing Modes
• It specifies how to calculate the effective memory
address of an operand by using information held in
registers and/or constants contained within a
machine instruction or elsewhere.
• In simple words, It can be defined as Addessing
modes tells the computer where to get/place a
number.
• It can also be defined as, “The techniques for
specifying the address of the operands.
• Effective Address:
 Addressing Modes
Effective Address: (EA) of an operand is the address of
(or the pointer to) the Main Memory or RF location in
which the operand is contained.
Operand = [EA]
Types of Addressing Modes
1. Immediate
2. Direct
3. Indirect
4. Register
5. Register Indirect
6. Displacement
 Addressing Modes
1. Immediate Addressing: An immediate mode
instruction has an operand field rather than
address field.
D=A
This is used to initialize the value of a variable the
advantage of this mode is that no additional memory
access is required for executing the instruction.
IR OP Operand

For ex- MVI A 05  Move 05 in Register A

 Addressing Modes
2. Direct Addressing: In this the instruction contains the address
of the data (operand) in the memory.
The operand will be present at some location in the memory
and its address in memory is provided in the instruction in the
instruction itself.
The operand is in either a RF register or a RAM loction, whose
address is explicitly given in the instruction ie. the address field
of the instruction contains the effective address.
EA = A
And D = (EA)
For ex- STA 2400H
STA means store content of accumulator in the memory location
2400H
 Addressing Modes
3. InDirect Addressing: In this the problem with direct
addressing is that the length of the address field is usually
less than the word length, thus limiting the address range.
One solution is to have the address field refer to the
address of a word in memory, which in turn contains a
full-length address of the operand.
EA = (A) and
D = (EA)
It requires atleast 2 memory references.
For ex-
LXI H, 2500H, Load H-L pair with 2500H
 Addressing Modes
4. Register Addressing: It is similar to direct addressing.
The only difference is that the address field refers to a register
rather than a main memory address.
EA = R
D = (EA)
For ex-
MOV A,B; contents of Register B are moved to Reg. A
5. Register Indirect Addressing: It is analogous to Indirect
addressing.
Only difference is whether the address field refers to a memory
location or a register.
For ex-
EA = (R)
 Addressing Modes
6. Displacement Addressing: A very powerful mode
of addressing combines the capabilities of direct
addressing and registers indirect addressing.
It is known by a variety of names depending upon the
context of its use, but the basic mechanism is the
same. This is referred to as Displacement Addressing.
EA = A + (R)
It requires that the instruction have 2 address fields,
atleast one of which is explicit.
 Instruction Formats
• It defines the layout of bits of an instruction in terms of its
constituent parts that the bits of an instruction can be
grouped into parts called fields.
• A computer can contain multiple Instruction Formats.
• It is the duty of the CU to determine the Instruction
Format and send appropriate signals to various parts of
the CPU.
• Elements of an Instruction Format
1. Operation Code
2. Reference to Opcode
3. Reference to Operands which may store results of data
4. Reference for Next Instruction
 Instruction Formats
1. Operation Code: An operation code also termed as
opcode which specifies the operation to be
performed.
2. Reference to Opcode: A reference to the operands
on which data processing is to be performed.
3. Reference to Operands which may store results of
data: A reference to the operands which may store
the results of data processing operation performed
by the instruction.
4. Reference for Next Instruction: A reference for the
next instruction, to be fetched and executed.
 Instruction Formats
Length of Instruction Format: Instructions of 8086
vary from 1 to 6 bytes instructions. (see diag.)
Types of Instructions
It is of 4 types as follows on the no. of operands they
contain or require to operate on:
1. Three-Address Instructions
2. Two-Address Instructions
3. One-Address Instructions
4. Zero-Address Instructions
 Instruction Formats
1. Three-Address Instructions: Computers with 3-
address IF can use each address field to specify
either a processor register or a memory operand.
For ex-
X=(A + B) * (C + D)
ADD R1, A, B R1 M[A]+ M[B]
ADD R2, C, D R2  M[C] + M[D]
MUL X,R1,R2 M[X]  R1, R2
 Instruction Formats
2. Two-Address Instructions: There are most common
in commercial computers. For ex-
X=(A + B) * (C + D)
MOV R1, A R1 M[A]
ADD R1, B R1  R1 + M[B]
MOV R2,C R2 M[C]
ADD R2, D R2 R2 + M[D]
MUL R1, R2 R1  R1 * R2
MOV X, R1 M[X]  R1
 Instruction Formats
3. One-Address Instructions: This is used as an implie
accumulator(AC) register for all data manipulation.
For multiplication and division there is a need for a 2nd
Register.
For ex- X=(A + B) * (C + D)
LOAD A AC  M[A]
ADD B AC  AC + M[B]
STORE T M[T]  AC
LOAD C AC  M[C]
ADD D AC  AC + M[D]
MUL T AC  AC * M[T]
STORE X M[X]  AC
 Instruction Formats
3. Zero-Address Instructions: A stack organised
computer does not use an address field for the
instructions ADD and MUL. The PUSH and POP
instructions need an address field to specify the
operand that communicates with the stack.
For ex- X=(A + B) * (C + D)
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  (A+B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C + D)
MUL TOS  (C + D) * (A + B)
 Contd.. Instruction Formats
3. Zero-Address Instructions:
PUSH A TOS  A

PUSH B TOS  B

ADD TOS  (A+B)

PUSH C TOS  C

PUSH D TOS  D

ADD TOS  (C + D)

MUL TOS  (C + D) * (A + B)
 Data Transfer & Manipulation
Computers provide an extensive set of instructions to
give the user the flexibility to carryout various
computational tasks.
The instruction set of different computers differs from
each other mostly in the way the operands are
determined from the address and mode fields.
Most Computer Instructions are of 3 types:
1. Data Transfer
2. Data Manipulation
3. Program Control
 Data Transfer & Manipulation
Data transfer instructions move data from one place
in the computer to another without changing the data
content. Some are as follows: Name Mnemonic Code
Load LD
For ex- Store ST

MOV BX, 592FH; Move MOV

Exchange XCH
Loads the immediate Input IN

No. 592FH in BX Output OUT

Push PUSH
Pop POP
 Data Manipulation Instructions(DMI)
2. Data Manipulation:
Instructions are those that performs arithmetic, logic
and shift operations.
DMI perform operations on data and provide the
computational capabilities for the computer.
It is of 3 types:
1. Arithmetic
2. Logical and Bit Manipulation
3. Shift and Rotate
 Data Manipulation Instructions(DMI)
1. Arithmetic Instructions:
4 basic operations are add, sub, mul and div.
Name Mnemonic Code
Addition ADD
Subtraction SUB
Multiplication MUL
Division DIV
Increment INC
Decrement DEC
Add with carry ADDC
Subtract with borrow SUBB
Negate( 2’s Complement) NEG
 Data Manipulation Instructions(DMI)
1. Arithmetic Instructions:
Ex- Multiplication Instructions
MOV BL, 5 Load data
MOV CL, 10
MOV AL, CL Position data
MUL BL Multiply
MOV DX, AX Position Product
 Data Manipulation Instructions(DMI)
2. Logical and Bit Manipulation Instructions:
• Logical instructions perform binary operations on
string of bits stored in registers.
• The logical instructions consider each bit of the
operand separately and treat it as a Boolean
Variable.
 Data Manipulation Instructions(DMI)
2. Logical and Bit Manipulation Instructions:
Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive OR XOR
Clear Carry CLRC
Set Carry SETC
Complement Carry COMC
Enable Interrupt EI
Disable Interrupt DI
 Data Manipulation Instructions(DMI)
3. Shift and Rotate Instructions:
• Shifts are operations in which the bits of a word are
moved to the left or right.
• The bit shifted in at the end of the word determines
the type of shift used.
• Shift instructions may specify logical shifts,
arithmetic shifts or rotate-type operations.
• In either case the shift may be to the right or to the
left.
 Data Manipulation Instructions(DMI)
3. Shift and Rotate Instructions:
Name Mnemonics
Logical Shift Right SHR
Logical Shift Left SHL
Arithmetic Shift Right SHRA
Arithmetic Shift Left SHLA
Rotate Right ROR
Rotate Left ROL
Rotate right through carry RORC
Rotate left through carry ROLC