8Gb: x16 TwinDie DDR3L SDRAM

Description

TwinDie™ 1.35V DDR3L SDRAM

MT41K512M16 – 32 Meg x 16 x 8 Banks x 2 Ranks

Description Options Marking

• Configuration
The 8Gb (TwinDie™) 1.35V DDR3L SDRAM is a low- – 32 Meg x 16 x 8 banks x 2 ranks 512M16
voltage version of the 1.5V DDR3 SDRAM device. It • FBGA package (Pb-free)
uses two Micron 4Gb DDR3L SDRAM x16 die for es- – 96-ball FBGA TNA
sentially two ranks of 4Gb DDR3L SDRAM. Unless sta- (10mm x 14mm x 1.2mm)
ted otherwise, the DDR3L meets the functional and • Timing – cycle time1
timing specifications listed in the equivalent-density – 1.071ns @ CL = 13 (DDR3L-1866) -107
DDR3 SDRAM data sheets. Refer to Micron’s 4Gb – 1.25ns @ CL = 11 (DDR3L-1600) -125
DDR3 SDRAM data sheet for the specifications not in- – 1.5ns @ CL = 9 (DDR3L-1333) -15E
cluded in this document. Specifications for base part – 1.87ns @ CL = 7 (DDR3L-1066) -187E
number MT41K256M16 (monolithic) correlate to • Operating temperature
manufacturing part number MT41K512M16. – Commercial (0°C ≤ T C ≤ 95°C) None
Features – Industrial (-40°C ≤ T C ≤ 95°C) IT
• Uses two 4Gb x16 Micron die in one package • Revision :E
• Two ranks (includes dual CS#, ODT, CKE, and ZQ Note: 1. CL = CAS (READ) latency.
balls)
• VDD = V DDQ = 1.35V (1.283–1.425V); backward com-
patible to 1.5V operation
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ballout
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-1071, 2,3 1866 13-13-13 13.91 13.91 13.91
-1251, 2 1600 11-11-11 13.75 13.75 13.75
-15E1 1333 9-9-9 13.5 13.5 13.5
-187E 1066 7-7-7 13.1 13.1 13.1

Notes: 1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).

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 8Gb: x16 TwinDie DDR3L SDRAM
Description

Table 2: Addressing

Parameter 512 Meg x 16

Configuration 32 Meg x 16 x 8 banks x 2 ranks
Refresh count 8K
Row address 32K A[14:0]
Bank address 8 BA[2:0]
Column address 1K A[9:0]
Page size 2KB

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.

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 8Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions

Ball Assignments and Descriptions

Figure 1: 96-Ball FBGA – x16 (Top View)

Note: 1. Dark balls (with rings) designate balls that differ from the monolithic versions.

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 8Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions

Table 3: 96-Ball FBGA – x16 Ball Descriptions

Symbol Type Description

A[14:13], A12/BC#, Input Address inputs: Provide the row address for ACTIVATE commands, and the column
A11, A10/AP, A[9:0] address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table – Command in
the DDR3 SDRAM data sheet.
BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE[1:0] Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for power-
down entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#[1:0] Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# pro-
vides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT[0:1] Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.

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 8Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions

Table 3: 96-Ball FBGA – x16 Ball Descriptions (Continued)

Symbol Type Description

RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-
ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.
UDM Input Input data mask: UDM is an upper-byte input mask signal for write data. Upper-
byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD Supply Power supply: 1.35V, 1.283–1.45V.
VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V.
VREFCA Supply Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS Supply Ground.
VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ[1:0] Reference External reference ball for output drive calibration: This lower byte ball is tied
to an external 240Ω resistor (RZQ), which is tied to VSSQ.
NC – No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).

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 8Gb: x16 TwinDie DDR3L SDRAM
Functional Description

Functional Description
The TwinDie DDR3L SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 8-bank DDR3L SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like die tested within a monolithic die package.
The DDR3L SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3L SDRAM input receiver. DQS is center-aligned with da-
ta for WRITEs. The read data is transmitted by the DDR3L SDRAM and edge-aligned to
the data strobes.
Read and write accesses to the DDR3L SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a program-
med sequence. Accesses begin with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR3L data sheet for complete information re-
garding individual die initialization, register definition, command descriptions, and die
operation.

Industrial Temperature
The industrial temperature (IT) option, if offered, requires that the case temperature
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when
TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Addi-
tionally, ODT resistance, IDD values, some IDD specifications and the input/output im-
pedance must be derated when T C is < 0°C or > 95°C. See the DDR3 monolithic data
sheet for details.

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 8Gb: x16 TwinDie DDR3L SDRAM
Functional Block Diagram

Functional Block Diagram

Figure 2: Functional Block Diagram (32 Meg x 16 x 8 Banks x 2 Ranks)

Rank 1
(32 Meg x 16 x 8 banks)

Rank 0
(32 Meg x 16 x 8 banks)

CS0#
CS1# RAS# CK
CKE0
CKE1 CAS# CK# A[14:0],
BA[2:0] ODT0
ODT1 WE#
ZQ0
ZQ1 DQS, DQS#
DQ[15:0]
DM/TDQS
TDQS#

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 8Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications

Electrical Specifications
Absolute Rating
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the device data sheet is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may adversely affect reliability.

Table 4: Absolute Maximum DC Ratings

Parameter Symbol Min Max Units Notes

VDD supply voltage relative to VSS VDD –0.4 1.975 V 1
VDD supply voltage relative to VSSQ VDDQ –0.4 1.975 V
Voltage on any ball relative to VSS VIN, VOUT –0.4 1.975 V
Input leakage current II –4 4 µA
Any input 0V ≤ VIN ≤ VDD,
VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current IVREF –2 2 µA 2
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Operating case temperature TC 0 95 °C 3, 4
Storage temperature TSTG –55 150 °C

Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤ 300mV.
2. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
3. MAX operating case temperature. TC is measured in the center of the package (see the
Temperature Test Point Location figure).
4. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC dur-
ing operation.

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 8Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications

Input/Output Capacitance
The lump capacitance values are not listed. Simulations should use actual models and
not lumped capacitance.

Temperature and Thermal Impedance

It is imperative that the DDR3L SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in main-
taining the proper junction temperature is using the device’s thermal impedances cor-
rectly. Thermal impedances listed in the Thermal Characteristics table apply to the cur-
rent die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the
thermal impedance table. For designs that are expected to last several years and require
the flexibility to use several DRAM die shrinks, consider using final target theta values
(rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR3 SDRAM device’s safe junction temperature range can be maintained when
the T C specification is not exceeded. In applications where the device’s ambient tem-
perature is too high, use of forced air and/or heat sinks may be required to satisfy the
case temperature specifications.

Table 5: Thermal Characteristics

Notes 1–3 apply to entire table
Parameter Symbol Value Units Notes
Operating temperature TC 0 to 85 °C
0 to 95 °C 4

Notes: 1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR), if available, must be enabled.

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 8Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications

Figure 3: Temperature Test Point Location

Test point

Length (L)

0.5 (L)

0.5 (W)
Width (W)

Table 6: Thermal Impedance

ΘJA (°C/W) ΘJA (°C/W) ΘJA (°C/W)

Airflow = Airflow = Airflow =
Die Rev Package Substrate 0m/s 1m/s 2m/s ΘJB (°C/W) ΘJC (°C/W) Notes
E 96-ball Low con- 48.0 36.4 31.9 n/a 1.8 1
ductivity
High con- 28.6 23.4 21.6 16.5 n/a
ductivity

Note: 1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.

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 8Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications – ICDD Parameters

Electrical Specifications – ICDD Parameters

Table 7: DDR3L ICDD Specifications and Conditions (Die Revision E)

Combined Individual Bus

Symbol Die Status Width -187E -15E -125 -107 Units
ICDD0 ICDD0 = x16 78 81 89 96 mA
IDD0 + IDD2P0 + 5
ICDD1 ICDD1 = x16 103 107 110 114 mA
IDD1 + IDD2P0 + 5
ICDD2P0 (slow exit) ICDD2P0 = x16 36 36 36 36 mA
IDD2P0 + IDD2P0
ICDD2P1 (fast exit) ICDD2P1 = x16 44 46 50 55 mA
IDD2P1 + IDD2P0
ICDD2Q ICDD2Q = x16 45 46 50 53 mA
IDD2Q + IDD2P0
ICDD2N ICDD2N = x16 46 47 50 53 mA
IDD2N + IDD2P0
ICDD2N T ICDD2NT = x16 53 57 60 63 mA
IDD2NT + IDD2P0
ICDD3P ICDD3P = IDD3P + IDD2P0 x16 50 53 56 59 mA
ICDD3N ICDD3N = x16 59 63 65 67 mA
IDD3N + IDD2P0
ICDD4R ICDD4R = x16 208 225 258 275 mA
IDD4R + IDD2P0 + 5
ICDD4W ICDD4W = x16 160 175 194 213 mA
IDD4W + IDD2P0 + 5
ICDD5B ICDD5B = x16 242 246 253 257 mA
IDD5B + IDD2P0
ICDD6 ICDD6 = x16 40 40 40 40 mA
(room temperature) IDD6 + IDD6
ICDD6ET ICDD6ET = x16 50 50 50 50 mA
(extended tempera- IDD6ET + IDD6ET
ture)
ICDD7 ICDD7 = x16 221 240 266 297 mA
IDD7 + IDD2P0 + 5
ICDD8 ICDD8 = 2 × IDD2P0 + 4 x16 40 40 40 40 mA

Note: 1. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.

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 8Gb: x16 TwinDie DDR3L SDRAM
Package Dimensions

Package Dimensions

Figure 4: 96-Ball FBGA – Die Revision E (Package Code TNA)

Seating plane

A 0.12 A

96X Ø0.45
Dimensions
apply to solder
balls post- reflow Ball A1 ID Ball A1 ID
on Ø0.33 NSMD (covered by SR)
ball pads. 9 8 7 3 2 1

A
B
C
D
E
F
14 ±0.1 G
H
12 CTR
J
K
L
M
N
P
R
0.8 TYP
T

0.8 TYP 1.1 ±0.1

6.4 CTR 0.25 MIN

10 ±0.1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

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 8Gb: x16 TwinDie DDR3L SDRAM
Package Dimensions

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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