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 Table of Contents
Before you Begin .......................................................................................................................... 2

Lab 3: Datapath Planning .............................................................................................................. 3

Objectives .................................................................................................................................. 3
Introduction ................................................................................................................................ 3
Exercise 1: Translating Datapath Diagram to DftSpecification: pad_io Block.................................. 4
Exercise 2: Translating Datapath Diagram to DftSpecification: blk_a ............................................12
Exercise 3: Translating Datapath Diagram to DftSpecification: blk_b ............................................22
Exercise 4: Translating Datapath Diagram to DftSpecification: blk_c ............................................25
Exercise 5: Translating Datapath Diagram to DftSpecification: blk_d (Optional) ............................28

Lab Answers ................................................................................................................................30

Lab 3.........................................................................................................................................30

NOTES:.........................................................................................................................................32

Lab: Datapath Planning 1

 Before you Begin

You will need to:

1. Obtain lab data if you have not already done so.

2. Set environment variables.

Obtaining Lab Data

If the ssn_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the ssn_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_ssn_data_v2021.2_20210907.tar.gz.

3. In the resultant window, select the Download button, enable the Save File button, then, select the OK
button to download the file.

4. Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_ssn_data_v2021.2_20210907.tar.gz .

5. In a terminal window, extract the files from the compressed tar file using the command:

tar xzvf ./tessent_ssn_data_v2021.2_20210907.tar.gz

You should now have a directory named ssn_data in your Home directory. That directory contains all the
files you need to perform the exercises, in this learning path.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables already
setup.

$SSN_LABS is an environment variable set up under the home directory that points to the training data
directory. If it is not already set up, you can execute SETENV SSN_LABS $HOME/ssn_data at your Linux
prompt to create it.

You are now ready to proceed with lab exercises.

Lab: Datapath Planning 2

 Lab 3: Datapath Planning

Objectives
Upon completing this lab, you should be able to:

• Plan a datapath through physical regions from ssn_bus_in to ssn_bus_out

• Translate an SSN datapath picture to a DftSpecification

• Add an extra output path leading to the adjacent block

• Add multiplexers and pipelines

• Use the Configuration Data Visualizer to set the DftSpecification

Introduction
In this lab, you will use a floorplan of a chip that has five different blocks as demonstrated in the following
diagram. You will plan the datapath through each one of those blocks from the ssn_bus_in to the
ssn_bus_out as located on the floorplan. Then you will add multiplexers to create debug return paths and
to modify the datapath to exclude some physical blocks.

Figure 3.1 Floorplan of Chip

Lab: Datapath Planning 3

Exercise 1: Translating Datapath Diagram to
DftSpecification: pad_io Block
In this exercise, you will translate the pad_io block datapath as shown in the following figure into a
DftSpecification.
bus_to_blk_a

DQ
Receiver1xPipeline

bus_frm_blk_d
Figure 3.2 Floorplan of Chip with pad_io modifications

Also, you are to add a Receiver1xPipeline between the ssn_bus_in and the bus_to_blk_a; which is a node
used at the start of the Datapath, or when crossing SSN clock CTS (clock tree synthesis) regions and
FIFOs or time-multiplexing are not used.

Change to the $SSN_LABS/Lab3/Exercise1 directory.

$ cd $SSN_LABS/Lab3/Exercise1

Examine the run_pad_io file, which loads the design and executes the required steps to give you the
ability to edit the wrappers directly. Close the file when you are done without making any changes.

Run the dofile.

$ ./run_pad_io

Set the DftSpecification and include the SSN wrapper.

ANALYSIS> set spec [create_dft_specification \

-sri_sib_list {ssn} -replace]
ANALYSIS> report_config_data

Open the Configuration Data Visualizer.

ANALYSIS> display_specification

Lab: Datapath Planning 4

You can see the DftSpecification wrapper of the pad_io block as shown in the following figure.

Right-click on the DftSpecifcation entry and choose Add > SSN as shown in the following.

Now you can see that the SSN wrapper has been added.

Select the SSN wrapper, verify the value of the ijtag_host_interface is Sib(ssn). If not, set it as
shown below, and click Apply.

Lab: Datapath Planning 5

 Define the bus clock period, bus width, and bus port names of the bus in/out, and clock, as follows:

a. Right-click on the SSN wrapper and choose Add > Datapath. Click on the inserted Datapath(1)
to edit the wrapper configuration. Set the SSN bus clock period to 5ns, which is equivalent to a
bus clock frequency of 200MHz, and the output bus width to be a 10 bits wide SSN bus.

Expand the Connections options, then set the bus clock input and the bus data input and output as
follows:

bus_clock_in ssn_clock_in
bus_data_in ssn_bus_in[%d]
bus_data_out ssn_bus_out[%d]

Click Apply to save your progress.

Question 1: In which order should we define the datapath nodes?

________________________________________________________

Referring to Figure 3.2, you can see that in the path back from the ssn_bus_out to the first node,
there is a multiplexer that we need to add to this datapath. The multiplexer has two paths, the first
path is from blk_d.

a. Right-click on the Datapath(1) then choose Add > Multiplexer.

Select the Multiplexer(1) and set the id to returnPath, as shown in the figure below.

Now to define the other driver of the mux, which is the bus_frm_blk_d signal, we need to add this
connection as a secondary bus. Expand the Connections options, then set the secondary_bus_data_in
to bus_frm_blk_d[%d], then click Apply.

Lab: Datapath Planning 6

 Refer back to Figure 3.2, where you can see that for the other side of the mux, there is a
Receiver1xPipeline node connected to the signal bus_to_blk_a. To add this node:

Right-click on the Datapath(1) then choose Add > Receiver1xPipeline.

Change its id to pad_io, then click Apply.

The output of the pipeline is the first leg of the mux, this path also connects to blk_a by bus_to_blk_a,
so you need to add this path.

Add a sub wrapper to the Receiver1xPipeline. You will need to define this net as an ExtraOutputPath.

Select Receiver1xPipeline, right click and choose Add > ExtraOutputPath.

Select the ExtraOutputPath wrapper added and expand the Connections options, set bus_data_out to
bus_to_blk_a[%d], then click Apply.

Lab: Datapath Planning 7

 Report the DFT Configuration to view afterward.

ANALYSIS> report_config_data $spec

The result of this command will be the same structure created by the DFT Configuration Visualizer.

To process the DftSpecification, select the DFTSpecification wrapper and click the Execute button as
shown below.

This button does the same process as the process_dft_specification command.

Extract the ICL.

INSERTION> extract_icl

Now let’s take a look at the Hierarchical schematic in Tessent Visualizer.

SETUP> open_visualizer

Open the Instance Browser, select the Module name = pad_io, right-click and choose Show on
Hierarchical Schematic.

Select the pad_io instance, then from the bottom pane of the window, choose the Nets option, then
we will select the nets we want to see.

Scroll down until you find the ssn_clock_in signal and select it, then right-click on it and choose
Show on Hierarchical Schematic.

Lab: Datapath Planning 8

Now repeat the same steps for the other nets, select the following nets: all ssn_bus_out, all ssn_bus_in, all
bus_to_blk_a, all bus_frm_blk_d, and all bus_data_out then right-click and choose Show on Hierarchical
Schematic.

Lab: Datapath Planning 9

Now if you compare this schematic with Figure 3.2 which we followed earlier to populate the
DftSpecification, you can see that all needed nodes have been inserted and connected correctly.

Create a patterns specification.

SETUP> create_patterns_specification

Process the patterns specification.

SETUP> process_patterns_specification

Lab: Datapath Planning 10

 Set the simulation library and run the testbench simulations.

SETUP> set_simulation_library_sources \
-v ../../libs/library/standard_cells/verilog/adk.v
SETUP> run_testbench_simulations

There should not be any simulation failures. Notice that the status of the simulations is reported as
they run. If you would like to check the pass/fail of simulations that had been run previously, use:

SETUP> check_testbench_simulations -report_status

Exit the session.

SETUP> exit

Notice that a complete script of all the previous steps has already been added to the
solutions directory.
Note

Lab: Datapath Planning 11

Exercise 2: Translating Datapath Diagram to
DftSpecification: blk_a
In this exercise, you will translate the blk_a block datapath into a DftSpecification as shown in the following
figure.

Figure 3.3 Floorplan of Chip with blk_a modifications

As you can see, we will also add a pipeline stage to the output side of the block. The connection from the
SSH to blk_d should be unchanged.

Change to the $SSN_LABS/Lab3/Exercise2 directory.

$ cd $SSN_LABS/Lab3/Exercise2

Examine the run_blk_a dofile, this file loads the design and makes all the required steps to give you
the ability to edit the wrappers directly; close the file when you are done without editing anything.

Run the dofile.

$ ./run_blk_a

Set the DftSpecification and include the SSN, EDT, and OCC pieces.

ANALYSIS> set spec [create_dft_specification \

-sri_sib_list {occ edt ssn} -replace]
ANALYSIS> report_config_data

Open the Configuration Data Visualizer.

ANALYSIS> display_specification

Lab: Datapath Planning 12

You can see the DftSpecification wrapper of the blk_a block as shown in the following figure:

Right-click on the DftSpecifcation line and choose Add > SSN as shown in the following figure:

Now you can see that the SSN wrapper has been added.

Lab: Datapath Planning 13

 Select the added SSN wrapper, verify the value of the ijtag_host_interface is Sib(ssn). If not, set it
as shown below and click Apply.

Define the bus clock period, bus width, and bus port names of the bus in/out, and clock, as follows:

Right-click on the SSN wrapper and choose Add > Datapath wrapper. Click on the inserted
Datapath(1) and edit the wrapper configuration by setting the SSN bus clock period to 5ns,
which is equivalent to a bus clock frequency of 200MHz. Set the output_bus_width to 10 bits
wide for SSN.

In the Connections area set the bus clock input and the bus data input and output to the following:

bus_clock_in ssn_clock_in

bus_data_in bus_frm_pad_io[%d]
bus_data_out bus_to_blk_b[%d]

Click Apply to save your progress.

Referring back to Figure 3.3, you can see that in the path from output port bus_to_blk_b to the first
node that comes after it, the pipeline is highlighted in orange, so we need to add this pipeline stage:

Right-click on the Datapath(1) then Add > Pipeline. For this inserted pipeline, set the id to blk_a_out,
then click Apply.

Lab: Datapath Planning 14

 After you have added the pipeline block, you need to add the SSH node:

Right-click on Datapath(1) then choose Add > ScanHost. Set its id to blk_a, then click Apply.

The bus leaving from the SSH also exits to blk_d from port bus_to_blk_d, so define this net as an
ExtraOutputPath:

Right-click on the ScanHost(blk_a) wrapper and choose Add > ExtraOutputPath, as a sub
wrapper to the ScanHost wrapper.

Select the new ExtraOutputPath and in the Connections area in the right panel set bus_data_out =
bus_to_blk_d[%d], and click Apply.

Lab: Datapath Planning 15

 Refer back to Figure 3.3, where you can see that the input of the SSH is connected to a pipeline
which has an input connected to the bus_frm_pad_io signal, so we need to add this pipeline:

Right-click on the Datapath(1) then choose Add > Pipeline, change its id to blk_a_in, and
click Apply.

Now you are done with the SSN wrapper.

Add the OCC wrapper, which defines the configuration of the OCC to be generated and inserted into
the design.

Right-click on DftSpecification(blk_a,rtl1), then choose Add > OCC. In the configuration

panel set ijtag_host_interface = Sib(occ) and click Apply.

Select the OCC wrapper, right-click then choose Add > Controller, add the following configuration
settings, and click Apply.

id clka
clock_intercept_node clka

Lab: Datapath Planning 16

Now you are done with the OCC wrapper.

We need to define the EDT wrapper. This wrapper specifies the port names for the interface of the
EDT controller and also defines the configurations for internal and external EDT modes.

Right click on DftSpecification(blk_a,rtl1), then choose Add > EDT, and in the configuration
panel set the following:

ijtag_host_interface = Sib(edt)

Remember to click Apply for this edit and the following ones.

Select the EDT wrapper, right-click then choose Add > Controller to add the internal controller, then add
the following configuration settings:

id c1_int
longest_chain_range 250, 300
scan_chain_count 500
input_channel_count 7
output_channel_count 7
leaf_instance_name internal_edt

Click Apply when you are done.

Lab: Datapath Planning 17

Expand the controller, and in the Connections wrapper, add the following in the right panel:

mode_enables = DftSignal(int_edt_mode)

Now, add the external controller by selecting the EDT wrapper, right-click then choose Add >
Controller, then add the following configuration settings:

id
c1_ext
longest_chain_range
250, 300
scan_chain_count
60
input_channel_count
1
output_channel_count
1
leaf_instance_name
external_edt

Expand the controller, and in the Connections panel, add the following:

mode_enables = DftSignal(ext_edt_mode)

Lab: Datapath Planning 18

 Now you have completed all the necessary step to define the wrapper contents.

Report the DFT Configuration to view the results.

ANALYSIS> report_config_data $spec

Process the DftSpecification by clicking the Execute button as shown below.

This button does the same process as the process_dft_specification command.

Extract the ICL.

INSERTION> extract_icl

Now let’s take a look at the Hierarchical schematic in Tessent Visualizer.

SETUP> open_visualizer

Open the Instance Browser, select the Module name = blk_a, right-click and choose Show on
Hierarchical Schematic.

As we did in Exercise1, we will only select the nets we want to show, select the blk_a instance, then
from the bottom pane of the window choose the Nets option and select the following nets: all
bus_to_blk_b, all bus_frm_pad_io, all bus_to_blk_d, all bus_data_out_tsl, and all bus_data_out.

Lab: Datapath Planning 19

 Right-click and choose Show on Hierarchical Schematic.

Now if you compare this schematic with Figure 3.3 which we followed earlier to set the wrappers
information, you can see that all needed blocks have been inserted and connected correctly.

Create a patterns specification.

SETUP> create_patterns_specification

Process the patterns specification.

SETUP> process_patterns_specification

Set the simulation library location and run the testbench simulations.

SETUP> set_simulation_library_sources \
-v ../../libs/library/standard_cells/verilog/adk.v
SETUP> run_testbench_simulations

Lab: Datapath Planning 20

 There should not be any simulation failures. Notice that the status of the simulations is reported as
they run. If you would like to check the pass/fail of simulations that had been run previously, use:

SETUP> check_testbench_simulations -report_status

Exit the session.

SETUP> exit

Notice that a complete script of all the previous steps has already been added
to the solutions directory.
Note

Lab: Datapath Planning 21

Exercise 3: Translating Datapath Diagram to
DftSpecification: blk_b
In this exercise, you will translate the blk_b block datapath into a DftSpecification as shown in the following
figure.

bus_frm_blk_a

Lab3_bus_to_blk_c
Figure 3.4 Floorplan of Chip with blk_b modifications

You are required to add an extra path after the pipeline, name this path Lab3_bus_to_blk_c.

Change to the $SSN_LABS/Lab3/Exercise3 directory.

$ cd $SSN_LABS/Lab3/Exercise3

Examine the file run_blk_b. This file loads the design and the wrappers of the initial design without
the new path Lab3_bus_to_blk_c, so you are required to add this path to the wrapper. Close the file
without editing anything and run it.

$ ./run_blk_b

Question 1: Based on what you have done in the previous exercises, refer to Figure 3.4, what is
the node that should be added first in the Datapath(1) wrapper?

_______________________________________________________

As you notice the path backward from the output of the block, which is the bus_to_blk_c signal to the
first node, there is an SSH node that you need to add.

Question 2: What do you think you should add after the SSH node you just added?

_______________________________________________________

Add the Pipeline node to be able to locate the Lab3_bus_to_blk_c signal as an ExtraOutputPath.

Lab: Datapath Planning 22

 The signal Lab3_bus_to_blk_c is connected to the output of the pipeline and the input of the SSH
node; this signal should be defined as an ExtraOutputPath. The ExtraOutputPath should be
located in the Pipeline wrapper.

Follow the instructions you did in the previous exercises, and place the wrapper in the correct place
and order. Your wrapper should look like this:

Report the DFT Configuration.

ANALYSIS> report_config_data $spec

Process the DftSpecification by clicking the Execute button.

Extract the ICL.

INSERTION> extract_icl

Now let’s take a look at the Hierarchical schematic in Tessent Visualizer

SETUP> open_visualizer

Select the blk_b instance and add it to the Hierarchical Schematic, select the block and then from the
bottom of the window choose the Nets option. Select all the nets needed to be shown on the
hierarchical schematic. Select the following nets: all bus_to_blk_c, all bus_frm_blk_a, all
Lab3_bus_to_blk_c, and all bus_data_out, then right-click and choose Show on Hierarchical
Schematic.

Lab: Datapath Planning 23

Now if you compare this schematic with Figure 3.4 which we followed earlier to set the wrapper contents,
you can see that all needed blocks have been inserted and connected correctly.

Create patterns specification.

____________________________________________

Process the patterns specification.

____________________________________________

Set the simulation library and run the testbench simulations.

______________________________________________

______________________________________________

Exit the session.

____________________________________________

Notice that a complete script of all the previous steps has already been added
to the solutions directory.
Note

Lab: Datapath Planning 24

Exercise 4: Translating Datapath Diagram to
DftSpecification: blk_c
In this exercise, you will translate the blk_c block datapath into a DftSpecification as shown in the following
figure.

Lab3_bus_frm_blk_b

Figure 3.5 Floorplan of Chip with blk_c modifications

You are required to add an extra multiplexer after the SSH node, which has a second leg connected to
blk_b by the bus connection Lab3_bus_frm_blk_b.

Change to the $SSN_LABS/Lab3/Exercise4 directory.

$ cd $SSN_LABS/Lab3/Exercise4

Examine the file run_blk_c. This file loads the design and the wrappers of the initial design without
the new path Lab3_bus_frm_blk_b, so you need to add this path to the wrapper. Close the file without
editing anything and run it.

$ ./run_blk_c

Refer back to Figure 3.5, you can see that you need to add the multiplexer node to the output of the
SSH which is also the output of this block blk_c.

The primary input of the multiplexer should be driven by the SSH node, so you need to add an SSH
node.

The secondary input of the multiplexer is connected to the signal Lab3_bus_frm_blk_b.

Follow the instructions you did in the previous exercises and place the components in the correct
places. Your specification should look like this when finished:

Lab: Datapath Planning 25

 Report the DFT Configuration.

__________________________________________________

Process the DftSpecification by clicking the Execute button.

Extract the ICL.

__________________________________________________

Now let’s take a look at the Hierarchical schematic in Tessent Visualizer.

__________________________________________________

Select the blk_c instance, then from the bottom pane of the window choose the Nets option. Select
the following nets: all bus_to_blk_d, all bus_frm_blk_b, all Lab3_bus_frm_blk_b, and all
bus_data_out, then right-click and choose Show on Hierarchical Schematic.

Lab: Datapath Planning 26

Now if you compare this schematic with Figure 3.5 which we followed earlier to set the wrapper contents,
you can see that all needed blocks have been inserted and connected correctly.

Create a patterns specification.

SETUP> create_patterns_specification

Process the patterns specification.

SETUP> process_patterns_specification

Set the simulation library and run the testbench simulations.

SETUP> set_simulation_library_sources \
-v ../../libs/library/standard_cells/verilog/adk.v
SETUP> run_testbench_simulations

Exit the session.

SETUP> exit

Notice that a complete script of all the previous steps has already been added
to the solutions directory.
Note

Lab: Datapath Planning 27

Exercise 5: Translating Datapath Diagram to
DftSpecification: blk_d (Optional)
In this exercise, you will translate the blk_d block datapath into a DftSpecification as shown in the following
figure.

Figure 3.6 Floorplan of Chip with blk_d modifications

Change to the $SSN_LABS/Lab3/Exercise5 directory.

$ cd $SSN_LABS/Lab3/Exercise5

Examine the run_blk_d file, which loads the design and the wrapper contents. Close the file without
editing anything and run it.

$ ./run_blk_d

In the Tessent Visualizer, open the Instance Browser, select the Module name = blk_d, right-click
and choose Show on Hierarchical Schematic.

Now let’s select all the needed nets, select all the following nets: all bus_to_pad_io, all
bus_from_blk_a, all bus_frm_blk_c, and all bus_data_out; then right-click and select Show on
Hierarchical Schematic.

Lab: Datapath Planning 28

Now if you compare this schematic with Figure 3.6 which we followed earlier to set the wrapper contents,
you can see that all needed items have been inserted and connected correctly.

When you are done, you can exit the session.

SETUP> exit

Notice that a complete script of all the previous steps has already been added
to the solutions directory.
Note

Lab: Datapath Planning 29

 Lab Answers

Lab 3
Exercise 1
In which order should we define the datapath nodes?

You should define the datapath nodes from the output node to the input node.

Exercise 3
Based on what you have done in the previous exercises, refer back to Figure 3.4, what is
the node that should be added first in the Datapath(1) wrapper?

The SSH node.

Q.2. Now, what do you think you should add after the SSH node you just added?
The Pipeline node and its ExtraOutputPath wrapper.

12. Create patterns specification.

SETUP> create_patterns_specification

13. Process the patterns specification.

SETUP> process_patterns_specification

14. Set the simulation library and run the testbench simulations.

SETUP> set_simulation_library_sources \
-v ../../libs/library/standard_cells/verilog/adk.v
SETUP> run_testbench_simulations

15. Exit the session.

SETUP> exit
Exercise 4
7. Report the DFT Configuration.

ANALYSIS> report_config_data $spec

9. Extract the ICL.

INSERTION> extract_icl

Lab: Datapath Planning 30

 10. Now let’s take a look at the Hierarchical schematic in Tessent Visualizer.

SETUP> open_visualizer

Lab: Datapath Planning 31

 NOTES:

Lab: Datapath Planning 32