HI-3717

Single-Rail ARINC 717 Protocol IC

July 2020 with SPI Interface

GENERAL DESCRIPTION APPLICATIONS

The HI-3717 from Holt Integrated Circuits is a CMOS device
designed for interfacing an ARINC 717 compatible bus to a · Digital Flight Data Acquisition Units (DFDAU)
Serial Peripheral Interface (SPI) enabled micro-controller. · Digital Flight Data Recorders (DFDR)
The part includes a selectable Harvard Bi-Phase (HBP) or
Bi-Polar Return-to-Zero (BPRZ) receive channel and · Quick Access Recorders (cassette type)
transmit channels with HBP and BPRZ encoders and line · Expandable Flight Data Acquisition and Recording
drivers. The receive channel has integrated analog line
Systems
receivers and the transmit channels have integrated line
drivers for the corresponding encoding method (HBP and
BPRZ). The part operates from a single +3.3V supply using PIN CONFIGURATIONS (Top View)
only four external capacitors. Each transmit and receive
channel has a 32-word by 12-bit FIFO for data buffering.

TXHA
GND
VDD

C1+

C2+
C1-

C2-
The HI-3717 is available in very small 44-pin 7mm x 7mm

V+

V-
-
-
-
-
-
-
-
-
-
-
-
Chip-scale (QFN) and 44-pin Quad Flat Pack (PQFP) plastic

44
43
42
41
40
39
38
37
36
35
34
packages.
NOCONV - 1 33 - OUTHA
RINB-40 - 2 32 - TXOUTHA
RINB - 3 31 - TXOUTHB
RINA - 4 30 - OUTHB
RINA-40 - 5 HI-3717PCI
FEATURES GND
TFIFO
- 6
- 7
HI-3717PCT
29
28
27
-
-
-
TXHB
TXBA
OUTBA
TEMPTY - 8 HI-3717PCM 26 - TXOUTBA
INSYNC - 9 25 - TXOUTBB
· Compliant with ARINC 717-14 (May 29, 2009) SYNC0 - 10 24 - OUTBB
SYNC1 - 11 23 - TXBB
· Operates from a single +3.3V supply with on-chip
converters to provide proper voltages for both Harvard
12
13
14
15
16
17
18
19
20
21
22
Bi-Phase (HPB) and Bi-Polar Return-to-Zero (BPRZ) -
-
-
-
-
-
-
-
-
-
-
MATCH
RFIFO
ROVF
MR
RSEL
GND
SI
SCK
SO
CS
ACLK
outputs
· One selectable receive channel as HBP or BPRZ with
integrated analog line receiver 44 - Pin Plastic 7mm x 7mm
· Both HBP and BPRZ transmitters have integrated line Chip-Scale Package (QFN)
drivers as well as digital outputs
· 32-word by 12-bit FIFOs for both the receive and the TXHA
GND
VDD

C1+

C2+
C1-

C2-

transmit channel
V+

V-
-
-
-
-
-
-
-
-
-
-
-
44
43
42
41
40
39
38
37
36
35
34

· Programmable slew rates on transmit channels: 1.5μs,

7.5μs or 10μs
· Digital transmitter outputs available for use with
external line drivers NOCONV - 1 33 - OUTHA
RINB-40 - 2 32 - TXOUTHA
· Programmable bit rates: 384, 768, 1536, 3072, 6144, RINB - 3 31 - TXOUTHB
30 - OUTHB
12288, 24576, 49152 and 98304 bits/sec (32, 64, 128, RINA - 4
HI-3717PQI 29 - TXHB
RINA-40 - 5
256, 512, 1024, 2048, 4096 and 8192 words/sec) GND - 6 HI-3717PQT 28 - TXBA
· Enhanced Sync detection allows multiple false sync TFIFO - 7 27 - OUTBA
TEMPTY - 8
HI-3717PQM 26 - TXOUTBA
marks in user data while still synchronizing within 8 INSYNC - 9 25 - TXOUTBB
seconds SYNC0 - 10 24 - OUTBB
SYNC1 - 11 23 - TXBB
· Fast SPI transmitter write and receiver read modes
· Match pin flags when preprogrammed word count /
subframe is received
12
13
14
15
16
17
18
19
20
21
22
-
-
-
-
-
-
-
-
-
-
-

· Frame / subframe word count indicator

MATCH
RFIFO
ROVF
MR
RSEL
GND
SI
SCK
SO
CS
ACLK

· Industrial and Extended temperature ranges

· Burn-in available
44 - Pin Plastic Quad Flat Pack (PQFP)

HOLT INTEGRATED CIRCUITS

(DS3717 Rev. J) www.holtic.com 07/20
 HI-3717

BLOCK DIAGRAM
VDD (3.3V)

10uF 0.1uF
CSUPPLY

TXHA

5Ω OUTHA
Transmit Transmit HBP Line 37.5Ω TXOUTHA
32 x 12-BIT Rate Encoder Driver
FIFO Selection 37.5Ω TXOUTHB

Slew 5Ω OUTHB
Rate
& TXHB
Loopback
Test TXBA
Control
5Ω OUTBA

BPRZ Line 37.5Ω TXOUTBA

Encoder Driver
37.5Ω TXOUTBB

5Ω OUTBB

TXBB
NOCONV +3.3V

V+
Transmit FIFO V+
MR Status Register
TXFSTAT V-
COUT
V-
SCK COUT
CS SPI DC / DC
C1+
SI Interface Converter
C1- CFLY+
SO
C2+
Control Control
ARINC 717
Register 0 Register 1 C2- CFLY-
ACLK Clock
Divider CTRL0 CTRL1

RSEL

Receive FIFO FIFO Status Pin Word Count

Status Register Assignment Utility Register
RXFSTAT Register WRDCNT
FSPIN

MATCH
RFIFO
TFIFO
HBP Line TEMPTY
Receiver

RINA 40 KΩ
RINB 40 KΩ
HBP / BPRZ
RINA-40 HBP / BPRZ Clock RECEIVE
SYNC
RINB-40 Data Recovery 32 x 12-BIT ROVF
Detect
Sampler & FIFO
Decoder
INSYNC
SYNC1
SYNC0
BPRZ Line
Receiver

GND

FIGURE 1.

HOLT INTEGRATED CIRCUITS

2
 HI-3717

PIN DESCRIPTIONS
Internal
SIGNAL FUNCTION DESCRIPTION Pull-up / Down
NOCONV INPUT Disables on-chip DC-DC voltage converter 50KΩ pull-down
RINB-40 INPUT Alternate receiver negative input. Requires external 40K ohm resistor
RINB INPUT Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP)
RINA INPUT Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP)
RINA-40 INPUT Alternate receiver positive input. Requires external 40K ohm resistor
GND POWER Chip 0V Supply (All GND pins on package must be connected)
Output is user programmable to indicate the Transmit FIFO Full or Half-full state.
TFIFO OUTPUT
See FSPIN<5>, in Table 7, FIFO Status Pin Assignment Register.
TEMPTY OUTPUT Output goes high when the transmit FIFO is empty
Output goes high when the receiver is synchronized to the incoming data. Synchroni-
INSYNC OUTPUT zation occurs at the next valid sync mark following the detection of the proper
number and order of consecutively spaced sync marks. See Table 5.
Output in conjunction with SYNC1 output indicates when each of the four ARINC 717
SYNC0 OUTPUT subframe sync words are received. Only valid in 4 Sync-Word mode when the
INSYNC pin is high.
Output in conjunction with SYNC0 output indicates when each of the four ARINC 717
SYNC1 OUTPUT subframe sync words are received. Only valid in 4 Sync-Word mode when the
INSYNC pin is high.
Output goes high when the value of the Frame Word Count Register matches the
MATCH OUTPUT
value in the Frame Count Utility Register, WRDCNT.
Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty
RFIFO OUTPUT
state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register.
Receive FIFO Overflow. Output goes high when an attempt is made to load a full
ROVF OUTPUT
Receive FIFO
MR INPUT Master Reset, active low 50KΩ pull-up
RSEL INPUT Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0 50KΩ pull-down
SI INPUT SPI interface serial data input 50KΩ pull-down
SCK INPUT SPI Clock. Data is shifted into SI and out of SO when CS is low. 50KΩ pull-down
SO OUTPUT SPI Interface seral data output
CS INPUT Chip Select. Data is shifted into SI and out of SO using SCK when CS is low 50KΩ pull-up
ACLK INPUT Master timing source for receiver and transmitters. 24 MHZ ±0.1% 50KΩ pull-down

TA B L E 1 .

HOLT INTEGRATED CIRCUITS

3
 HI-3717

PIN DESCRIPTIONS (cont.)

Internal
SIGNAL FUNCTION DESCRIPTION Pull-up / Down

TXBB OUTPUT Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required)
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external
OUTBB OUTPUT
32.5 ohm resistor
Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717
TXOUTBB OUTPUT
bus
Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC
TXOUTBA OUTPUT
717 bus
Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external
OUTBA OUTPUT
32.5 ohm resistor
TXBA OUTPUT Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required)
TXHB OUTPUT Harvard Bi-Phase (HBP) digital low output (external line driver required)
Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5
OUTHB OUTPUT
ohm resistor
TXOUTHB OUTPUT Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus
TXOUTHA OUTPUT Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus
Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5
OUTHA OUTPUT
ohm resistor
TXHA OUTPUT Harvard Bi-Phase (HBP) digital high output (external line driver required)
V- CONVERTER DC/DC converter negative voltage
C2- CONVERTER DC/DC converter fly capacitor for V-
C2+ CONVERTER DC/DC converter fly capacitor for V-
V+ CONVERTER DC/DC converter positive voltage
C1+ CONVERTER DC/DC converter fly capacitor for V+
C1- CONVERTER DC/DC converter fly capacitor for V+
VDD POWER Chip +3.3V Supply

TA B L E 1 ( c o n t . ) .

TA B L E 1 .

HOLT INTEGRATED CIRCUITS

4
 HI-3717

SERIAL PERIPHERAL
INTERFACE (SPI)
SPI BASICS HI-3717 SPI INSTRUCTIONS
The HI-3717 uses an SPI (Serial Peripheral Interface) for host Instruction op codes are used to read, write and configure the
access to internal registers and data FIFOs. Host serial HI-3717. Each SPI read or write operation begins with an 8-bit
communication is enabled through the Chip Select (CS) pin, instruction. When CS goes low, the next 8 clocks at the SCK
and is accessed via a four-wire interface consisting of Serial pin shift an instruction op code into the decoder, starting with
Data Input (SI) from the host, Serial Data Output (SO) to the the first rising edge. The op code is shifted into the SI pin, most
host and Serial Clock (SCK). All read / write cycles are significant bit (MSB) first. The SPI can be clocked up to10 MHz.
completely self-timed.
The SPI instructions are of a common format. The most
The SPI protocol specifies master and slave operation; the significant bit (MSB) specifies whether the instruction is a write
HI-3717 operates as an SPI slave. “0” or read “1” transfer.

The SPI protocol defines two parameters, CPOL (clock

polarity) and CPHA (clock phase). The possible CPOL-CPHA

/W
R
combinations define four possible “SPI Modes”. Without
describing details of the SPI modes, the HI-3717 operates in X X X X X X X
Mode 0 where input data for each device (master and slave) is MSB 7 6 5 4 3 2 1 0 LSB
clocked on the rising edge of SCK, and output data for each SPI INSTRUCTION FORMAT
device changes on the falling edge (CPHA = 0, CPOL = 0). The
host SPI logic must be set for Mode 0 for proper
communications with the HI-3717 . For write instructions, the most significant bit of the data word
must immediately follow the instruction op code and is clocked
As seen in Figure 2, SPI Mode 0 holds SCK in the low state into its register on the next rising SCK edge. Data word length
when idle. The SPI protocol transfers serial data as 8-bit bytes. varies depending on word type written: 8-bit Control & Status
Once CS is asserted, the next 8 rising edges on SCK latch input Register writes, 16-bit Word Count Utility Register writes and
data into the master and slave devices, starting with each byte's 16-bit Transmit FIFO writes.
most-significant bit. A rising edge on CS terminates the serial
transfer and re-initializes the HI-3717 SPI for the next transfer. For read instructions, the most significant bit of the requested
If CS goes high before a full byte is clocked by SCK, the data word appears at the SO pin at the next falling SCK edge
incomplete byte clocked into the device SI pin is discarded. after the last op code bit is clocked into the decoder. As in write
instructions, the data field bit-length varies with read instruction
In the general case, both master and slave simultaneously type.
send and receive serial data (full duplex), per Figure 2 below.
However the HI-3717 operates half duplex, maintaining high Since HI-3717 operates in half-duplex mode, the host discards
impedance on the SO output, except when actually transmitting the dummy byte it receives while serially transmitting the
serial data. When the HI-3717 is sending data on SO during instruction op code to the HI-3717.
read operations, activity on its SI input is ignored. Figure 3 and
Figure 4 show actual behavior for the HI-3717 SO output.

SCK (SPI Mode 0)

SI MSB LSB

High Z High Z
SO MSB LSB

CS

FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0

HOLT INTEGRATED CIRCUITS

5
 HI-3717

Figure 3 and Figure 4 show read and write timing as it appears Note: SPI Instruction op-codes not shown in Table 2 are
for a single-byte and dual-byte register operation. The “reserved” and must not be used. Further, these op-codes will
instruction op code is immediately followed by a data byte not provide meaningful data in response to a read instruction.
comprising the 8-bit data word read or written. For a register
Two instruction bytes cannot be “chained”; CS must be negated
read or write, CS is negated after the data byte is transferred.
after each instruction, and then reasserted for the following
Table 2 summarizes the HI-3717 SPI instruction set. Read or Write instruction.

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK

MSB LSB

SI

Op-Code Byte MSB LSB MSB

High Z High Z
SO

Data Byte

CS

Note: Two instruction bytes cannot be “chained”;

CS must be negated after each instruction, and then
reasserted for the following Read or Write instruction.

FIGURE 3. Single-Byte Read From a Register

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
SCK
SPI Mode 0
MSB LSB MSB LSB MSB LSB

SI

Op-Code Byte Data Byte 0 Data Byte 1

High Z
SO

CS

Note: Two instruction bytes cannot be “chained”;

CS must be negated after each instruction, and then
reasserted for the following Read or Write instruction.

FIGURE 4. 2-Byte SPI Write Example

HOLT INTEGRATED CIRCUITS

6
 HI-3717

SPI INSTRUCTION SET

# Data
OP Code R/W DESCRIPTION
bytes

0x64 W 1 Write Control Register 0

0x62 W 1 Write Control Register 1
0x6A W 1 Write Receiver FIFO Status Pin Assignment Register
0x72 W 2 Write Word Count Utility Register
0x74 W 2 Write Transmit FIFO word
0x2* W 1 Fast Write Transmit FIFO Word

0xE4 R 1 Read Control Register 0

0xE2 R 1 Read Control Register 1
0xE6 R 1 Read Receive FIFO Status Register
0xE8 R 1 Read Transmit FIFO Status Register
0xEA R 1 Read Receive FIFO Status Pin Assignment Register
0xF2 R 2 Read Word Count Utility Register
0xF6 R 2 Read Receive FIFO Word
0xFE R 4 Read Receive FIFO Word and Word Count
0xC* R 1 Fast Read Receive FIFO

* In the case of FAST instructions, the last four bits of the instruction byte are data
TABLE 2. SPI Instruction Set

HOLT INTEGRATED CIRCUITS

7
 HI-3717

REGISTER DESCRIPTIONS
CONTROL REGISTER 0: CTRL0

SL PS
S L W1

EL
R 0
EW
XS
W
2

0
1

E
BR

BR
BR

32
Read: SPI Op-code 0xE4 X
Write: SPI Op-code 0x64 7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 - R/W 0 Not Used. Always reads a “0”
6-4 BR2:0 R/W 0 Setting these bits sets the ARINC 717 data rate for both the receive and transmit data.
000 768 Bits/sec. ( 64 words/sec.)
001 1536 Bits/sec. (128 words/sec.)
010 3072 Bits/sec. (256 words/sec.)
011 6144 Bits/sec. (512 words /sec.)
100 12288 Bits/sec. (1024 words/sec.)
101 24576 Bits/sec. (2048 words/sec.)
110 49152 Bits/sec. (4096 words/sec.)
111 98304 Bits/sec. (8192 words/sec.)
3 32WPS R/W 0 Setting this bit overrides the state of BR2:0 and sets the data rate at 384 Bits/sec. (32 words/sec.)
2-1 SLEW1:0 R/W 0 Setting these bits controls the nominal slew rate on both the HBP & BPRZ transmit channel outputs.
00 7.5 µs
01 10.0 µs ( Same as ARINC 429 Low Speed)
10 10.0 µs ( Same as ARINC 429 Low Speed)
11 1.5 µs ( Same as ARINC 429 High Speed)
0 RXSEL R/W 0 Selects either the HBP (”0”) or BPRZ (”1”) Receiver. This bit is logically OR’d with the RSEL input
pin.

TABLE 3.

C C
CONTROL REGISTER 1: CTRL1 YN YN T
T S
S T OS S
SR SF N TE
Read: SPI Op-code 0xE2 X X X X
Write: SPI Op-code 0x62 7 6 5 4 3 2 1 0
MSB LSB
Bit Name R/W Default Description
7-4 - R/W 0 Not Used, Always reads a “0”
3 SRST R/W 0 Software Reset - Setting this bit to “1” empties all the FIFO’s, clears the Sync detection logic and
sets the analog line drivers to Hi-Z state. All other register bits remain unchanged.
2 SFTSYNC R/W 0 2 Sync-Word Mode: Setting this bit to “1” will result in the INSYNC output pin going high when the
third of three consecutively occurring sync marks is detected.
1 NOSYNC R/W 0 No Synchronization - Setting this bit to “1” will result in all data captured being loaded into the
receive FIFO. WARNING: In this mode there is no way the HI-3717 can determine frame or sub-
frame boundaries. This sync mode overrides all the other sync modes when set to “1”.
0 TEST R/W 0 Test Mode - A “1” in this bit position will disable the line receiver and both line drivers and the digital
transmitted data will be looped back to the HBP or BPRZ data sampler selected by RXSEL .

TABLE 4.

HOLT INTEGRATED CIRCUITS

8
 HI-3717

RECEIVE FIFO STATUS REGISTER: RXFSTAT Y

C F PT F

LL
N C1 C0 AL M OV T

U
SY YN YN FH FE F S

FF
IN S S R R R TE

R
Read: SPI Op-code 0xE6 X X X X X X X X
Write: Read Only 7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 INSYNC R 0 Receive channel sync indicator. The bit is set to”1” when synchronization is achieved on the
receive channel.
4 Sync-Word Mode occurs when four consecutive valid sync marks (Octal 1107, 2670, 5107 and
6670 respectively) are received exactly 1 second apart. The bit is set when the next valid and
properly spaced subframe sync mark (Octal 1107) is detected.
2 Sync-Word Mode (CTRL1<2> = “1”) occurs when two consecutively valid sync marks are
received exactly 1 second apart and in the proper order but the first sync mark does not have to be
Octal 1107. The bit is set when the next valid and properly spaced subframe sync mark is
detected.
The bit remains set until synchronization is lost at which time the device automatically attempts to
re-synchronize. No data is passed to the receive FIFO until Synchronization is re-established.
Existing data in the FIFO remains intact and can be read at any time.
6-5 SYNC0:1 R 0 The two bits are realtime indicators of when each of the four ARINC 717 subframe sync marks are
received. They are updated when the sync mark is detected and passed to the Receive FIFO. The
two bits are only valid in 4 Sync-Word mode when the INSYNC pin is high. See Application Note
AN-170 for detecting SYNC phase in 2 Sync-Word mode (SFTSYNC).
00 Subframe SYNC1 mark received (Octal 1107)
01 Subframe SYNC2 mark received (Octal 2670)
10 Subframe SYNC3 mark received (Octal 5107)
11 Subframe SYNC4 mark received (Octal 6670)
4 RFFULL R 0 Bit is set when the Receive FIFO contains 32 words.
3 RFHALF R 0 Bit is set when the Receive FIFO contains exactly 16 words.
2 RFEMPTY R 1 Bit is set when the Receive FIFO is empty. It is reset to”0” when the first valid word is passed to the
Receive FIFO.
1 RFOVF R 0 FIFO Overflow bit and ROVF pin are set to “1” when devices attempts to load a valid word to a full
Receive FIFO. The Receive FIFO will ignore additional words if it is full.
0 - R 0 Not used, Always reads “0”

TABLE 5.

HOLT INTEGRATED CIRCUITS

9
 HI-3717

REGISTER DESCRIPTIONS (cont.)

TRANSMIT FIFO STATUS REGISTER: TXFSTAT Y Y
F PT F PT FW

LL
O AL EM AL M OV ST

U
F
FI H H E

F
TF TF FF FF FF TE

FF
T
Read: SPI Op-code 0xE8 X X X X X X X X
Write: Read Only 7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7 TFIFO R 0 This bit mirrors the status of the TFIFO pin. See register FSPIN below for TFIFO pin assignment.
6 TFHALF R 0 Set when the Transmit FIFO contains exactly 16 words
5 TFEMPTY R 1 Set when the Transmit FIFO is empty. Reset to “0” when at least one word is loaded to the Transmit
FIFO.
4-0 - R 0 Not used, Always reads “0”

TABLE 6.

FIFO STATUS PIN ASSIGNMENT 0 IGN TY

1 LF P VFW T

LL
REGISTER: FSPIN FO
O S A M

U
FI IF A H E O S

F
R RF TF FF FF FF TE

FF
Read: SPI Op-code 0xEA X X X X X X X X
Write: SPI Op-code 0x6A 7 6 5 4 3 2 1 0
MSB LSB

Bit Name R/W Default Description

7-6 RFIFO1:0 R/W 0 These bits program which Receive FIFO Status Register bit is represented by the RFIFO pin .
00 RFIFO pin is set “1” when Receive FIFO Status Register Bit 2, RFEMPTY, is “1”.
01 RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”.
10 RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”.
11 RFIFO pin is set “1” when Receive FIFO Status Register Bit 4, RFFULL, is “1”.
5 TFASIGN R/W 0 This bit programs the TFIFO pin to reflect the Transmit FIFO Status (FIFO Full or FIFO Half-Full).
0 TFIFO pin is set “1” when Transmit FIFO is Full (contains 32 words).
1 TFIFO pin is set “1” when Transmit FIFO is Half-Full (contains exactly 16 words).
4-0 - R 0 Not used, Always reads “0”

TABLE 7.

WORD COUNT UTILITY REGISTER: WRDCNT Y

PT
M
12 11 C10 8 7 C6 C5 4 3 C2 0 E O
C FF S1 S
9

Read: SPI Op-code 0xF2 C C C C C C

C

Write: SPI Op-code 0x72 X X X X X X X X X X X X X X X X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB

The Word Count Utility Register can be programmed to generate an interrupt on the MATCH pin when the data for the specified word
count of the specified subframe is loaded into the Receive FIFO. The Word Count Utility Register can used with any of the standard
ARINC 717 data rates and all of the expanded data rates, except 8192 wps.
Bit Name R/W Default Description
15 - 3 C12:0 R/W 0 Subframe Word Count - The value is compared to the current word count in the Receive FIFO and
sets the MATCH pin to “1” whenever there is a match. The MATCH pin will stay at “1” for one word
time.
2 - R/W 0 Not used, Always reads “0”
1-0 S1:0 R/W 0 Subframe ID
00 Subframe One
01 Subframe Two
10 Subframe Three
11 Subframe Four

TABLE 8.
HOLT INTEGRATED CIRCUITS
10
 HI-3717

ARINC 717 MESSAGE AND BIT ORDERING The first 12- bit word of a subframe that appears on the ARINC 717
bus is the synchronization code with the least significant bit (LSB)
ARINC 717 messages consist of 12-bit words sent in a 4 second first. This is immediately followed by up to 8191 12-bit data words,
frame divided into four 1 second subframes. Each subframe all within1 second from the start of the synchronization code. The
consists of 64 (basic rate), 128, 256, 512, 1024, 2048, 4096 or next three subframes immediately follow the first subframe with
8192 12 bit words, depending on the data rate of the target their synchronization code as the first 12-bit word of the subframe
system. followed by the same number of data words as the first subframe.

The first word of each subframe contains a unique Barker Code ARINC 717 data is transmitted between the HI-3717 and host
synchronization pattern that identifies the subframe. The octal microcontroller using the four-wire Serial Peripheral Interface
synchronization code for subframes 1 through 4 are 1107, 2670, (SPI). A read or write operation consists of a single-byte op-code
5107 and 6670 respectively. followed by 8-bit data words. Figure 5 shows examples of how the
SPI data bytes are mapped to the ARINC 717 message.

ARINC717 Message as received / transmitted on the ARINC 717 serial bus

Frame
Subframe 1 Subframe 2 Subframe 3 Subframe 4
LSB MSB LSB MSB LSB MSB LSB MSB
1 Second 1 Second 1 Second 1 Second
4 Seconds

ARINC717 Subframe Format

1st Subframe Sync Code (1107) 2nd Data Word Nth Data Word
1 1 1 0 0 0 1 0 0 1 0 0 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11
LSB MSB LSB MSB LSB MSB
1 Second

time

ARINC 717 Message as transferred on the SPI bus

SPI Op-Code Don’t Care Subframe Sync or Data Word Bits

0 1 1 1 0 1 0 0 X X X X 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB MSB LSB

Example 1. Write Transmit FIFO Subframe Sync or Data Word (Op-Code 0x74).
SPI Op-Code Always “0” Subframe Sync or Data Word Bits

1 1 1 0 0 1 1 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB MSB LSB

Example 2. Read Receive FIFO Subframe Sync or Data Word (Op-Code 0xF6).
SPI Op-Code Subframe Sync or Data Word Bits

0 0 1 0 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB

Example 3. Fast Write Transmit FIFO Subframe Sync or Data Word (Op-Code 0x2-) .
SPI Op-Code Word Count Bits Sync Bits

0 1 1 1 0 0 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 0
MSB LSB MSB LSB

Example 4. Write Word Count Utility Register, WRDCNT (Op-Code 0x72).

SPI Op-Code Always “0” Subframe Sync or Data Word Bits Word Count Bits Sync Bits

1 1 1 1 1 1 1 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0
MSB LSB MSB LSB MSB LSB
Always “0”
Example 5. Read Receive FIFO Data Word with Word Count (Op-Code 0xFE).

FIGURE 5. ARINC 717 & SPI Bit Ordering

HOLT INTEGRATED CIRCUITS

11
 HI-3717

FUNCTIONAL DESCRIPTION
OVERVIEW In order to avoid inadvertent transceiver operation, Control
Register 0, CTRL0, should be programmed last. Writing
ARINC 717 is a continuous transmission of 12-bit words in 4 second CTRL0 sets the desired data rate which, after one bit period,
frames divided into four 1 second subframes. The programmed enables the internal clocks. This in turn makes the transmitter
data rate (32 to 8192 wps) determines the number of words per or receiver operational. Changing the data rate on the fly may
subframe. The first word of each subframe is reserved for a unique
result in unpredictable operation during the transition to the
sync mark. Figure 5 illustrates the relationship between ARINC 717
frames, subframes and words. new programmed state. A full reset, POR or MR, should be
issued before reprogramming the data rate.
The HI-3717 is comprised of independent ARINC 717 receive and
transmit sections easily accessible via a four wire SPI Data Rate
communications bus. It supports the ARINC 717 Harvard Bi-Phase
(HBP) protocol as well as the Bi-Polar Return to Zero (BPRZ) For correct ARINC 717 date rate reception, transmission and bit
auxiliary protocol. timing, the HI-3717 requires a 24 MHz reference clock source
applied to the ACLK input. This clock is divided down to achieve the
The receiver accepts data from either a Harvard Bi-Phase (HBP) or data rate programmed with CTRL0<6:4>. The input receive data is
a Bi-Polar Return to Zero (BPRZ) bus, recovers the clock, decodes 8X oversampled relative to the programmed data rate.
the data, synchronizes the ARINC 717 data frames using the
unique subframe sync marks and stores the recovered data in a 32 ARINC 717 requires a basic data rate of 64 wps with support for
word x 12 bit Receive FIFO. 128, 256 and 512 wps. The HI-3717 offers an expanded range of
32 to 8192 wps for testing purposes and future expansion.
The ARINC 717 Transmitter accesses data from a 32 word x 12 bit CTRL0<3>, 32WPS, overrides the state of CTRL0<6:4> and sets
Transmit FIFO, encodes it into both HBP and BPRZ data streams at the data rate to 32 wps. The required 0.1% timing tolerance is
the selected data rate, and converts the digital data stream to maintained over all data rates.
ARINC 717 bus compatible outputs. There are separate outputs for
the HBP and BPRZ ARINC 717 buses. Line Driver Output Slew Rates

The receive and transmit sections operate at the same data rate The slew rate of the HBP and BPRZ outputs is controllable with
and they are configured and monitored via the SPI interface. CTRL0<2:1>. A 7.5µs slew rate conforms to all the required ARINC
717 data rates. In addition, a 1.5µs is provided for the higher data
Refer to Figure 1 for the Block Diagram of the HI-3717 rates and a 10µs for the 32 wps data rate.

INITIALIZATION AND RESET Receiver Format

The HI-3717 generates a full reset upon application power. The The ARINC 717 format of the receiver is selectable as HBP or
power-on-reset (POR) sets all registers to their default values, BPRZ by the state in CTRL0<0>, RXSEL, OR’d with the state of the
places the Receive and Transmit FIFOs to their empty state, and external RSEL input pin. A “0” on RSEL and CTRL0<0> selects
clears the sync detection logic. It also sets both the HBP and BPRZ HBP and a “1” on either RSEL or CTRL0<0> selects BPRZ.
outputs to the high impedance state and the input sampling and
Refer to Table 3 for the detail description of each bit in Control
decoders are disabled. See Register Descriptions for complete
Register 0.
definition of the default values.
The part can also be initialized to the full reset state by applying a Input Synchronization Mode
100ns active low pulse to the external MR pin. The HI-3717 has three different synchronization modes:
A software reset is also possible via the SPI communications 1. 4 Sync-Word Mode
interface by writing a “1” to the CTRL1<3>. This bit places both the
Receive and Transmit FIFO’s in the empty state, clears the sync This is the default synchronization mode. In this mode the
detection logic, and sets both the HBP and BPRZ line drivers to a HI-3717 searches for the four subframe sync marks:
high impedance state. All other registers remain unchanged. The SYNC1 = Octal 1107
device is held in the reset state until a “0” is written to CTRL1<3>. SYNC2 = Octal 2670
SYNC3 = Octal 5107
CONFIGURATION SYNC4 = Octal 6670
The HI-3717 is configured via the SPI communications bus by in the correct sequential order starting from SYNC1 and the
writing to Control Register 0, CTRL0, and Control Register 1, exact bit time determined by the programmed word rate. When
CTRL1. They are reset to 0x00 following a Power On Reset synchronization is achieved the INSYNC pin as well as the
(POR) or a Master Reset (MR) but remain unchanged on a INSYNC bit of the Receive FIFO Status Register, RXFSTAT<7>
Software Reset, CTRL1<3>, SRST. The function of each register are set to “1” on the next valid SYNC1 mark. The valid SYNC1
bit is shown in the Register Descriptions. mark and following data words are stored in the Receive FIFO.

HOLT INTEGRATED CIRCUITS

12
 HI-3717

FUNCTIONAL DESCRIPTION (cont.)

Sync time varies from 4 seconds to a worst case of 8 seconds Digital Loopback
for a valid data stream.
Normal HI-3717 operation is with CTRL1<0> set to “0”. Setting it
The first word stored in the Receive FIFO is available when to “1” places the part in digital loopback mode. In this mode the
RXFSTAT<2>, RFEMPTY, is reset to “0”, which is 12-bit periods analog line receivers are disconnected from the data samplers
(one word time) after INSYNC is set to “1”. and both output line drivers are placed in a high impedance state.
The output encoders are connected to input sampler / decoder.
The HI-3717 remains in sync as long as the proper sync
The part may be verified by selecting the desired receive decode
sequence is maintained. INSYNC is reset to “0” when the next
format with RSEL pin or CTRL0<0>, writing the transmit FIFO and
expected subframe sync mark is not present. The HI-3717 will
reading the receive FIFO. All status pins and registers reflect the
initiate a new synchronization process at the next valid SYNC1
status of the loopback operation.
mark.
Once the part falls out of sync, the whole previous subframe FIFO Status Pin Assignment Register, FSPIN
should be discarded. This register assigns the function of the external RFIFO and
NOTE: If the part does not synchronize in 8 seconds TFIFO pins. The RFIFO pin reflects the state of one of the three
(INSYNC = “0”), a Software Reset should be performed by Receive FIFO status flags (RFFULL, RFHALF and RFEMPTY) in
setting CTRL1<3>, SRST. the Receive FIFO Status Register, RXFSTAT. The TFIFO pin
reflects the state of one of two Transmit FIFO states (Transmit
2. 2 Sync-Word Mode FIFO Full or Transmit FIFO Half-Full). Refer to the FSPIN Register
Description in Table 7 for register assignment details.
In this mode the HI-3717 searches for any two subframe sync
marks in the correct sequential order and the exact starting time Word Count Utility Register, WRDCNT
for the sync mark. INSYNC is set to “1” when the third valid sync
mark is detected. The part must continue to detect each sync The MATCH pin goes high when the HI-3717 is in the INSYNC
mark in the correct order and with the correct starting time to condition and the word count and subframe count matches the
stay in sync. value programmed in the Word Count Utility Register. Note: The
INSYNC pin is set to “1” when the second consecutive SYNC1
3. No Sync Detect Mode mark of the proper sync sequence is received. The Word Count
In this mode, the INSYNC is set to “1” and all data is stored in Utility Register and Match pin function can be used for the
the Receive FIFO. Without sync detection, the Receive FIFO standard ARINC 717 data rates and all of the expanded data rates,
just records the sequential bits, not words, from the bus. It is up except 8192 wps.
to the user to detect the sync marks and determine the word
boundaries in this mode.
In both the 4 Sync-Word and 2 Sync-Word Modes, the HI-3717
uses a proprietary sync tracking and detection method which allows
correct synchronization to occur in the presence of up to three false
sync marks without increasing the sync time.

+5V
Harvard Bi-Phase
-5V

+10V

Bi-Polar Return to Zero

-10V

Data 1 0 1 1 0 1 0 1 0 0 1 1
LSB MSB

FIGURE 6. ARINC 717 HBP & BPRZ Differential Input Signal Format

HOLT INTEGRATED CIRCUITS

13
 HI-3717

FUNCTIONAL DESCRIPTION (cont.)

ARINC 717 RECEIVER Bit Timing & Input Sampling

The input data stream for ARINC 717 can be one of two formats. The bit timing for both the receive and transmit functions is the data
The main ARINC 717 bus to a Digital Flight Data Recorder (DFDR) rate programmed in CTRL0<6:3>. The HI-3717 allows the
uses Harvard Bi-phase (HBP) encoding and the auxiliary output following word / bit rates:
bus to an Aircraft Integrated Data System (AIDS) uses Bi-Polar 32 words/sec. = 384 Bits/sec
Return to Zero (BPRZ) encoding as shown in Figure 6. 64 words /sec. = 768 Bits/sec.
128 words/sec. = 1536 Bits/sec.
The HI-3717 has an independent ARINC 717 receive channel with a
256 words/sec. = 3072 Bits/sec.
selectable on-chip HBP analog line receiver for connection to the 512 words /sec. = 6144 Bits/sec.
main incoming ARINC 717 data bus or a BPRZ analog line receiver 1024 words/sec. = 12288 Bits/sec.
for connection to an auxiliary data bus. 2048 words/sec. = 24576 Bits/sec.
4096 words/sec. = 49152 Bits/sec.
The ARINC 717 specification requires the following detection levels
8192 words/sec. = 98304 Bits/sec.
for the HBP inputs:
STATE DIFFERENTIAL VOLTAGE The 32 WPS data rate is typically used for testing purposes.
HI +2 Volts to +8 Volts The input data from the selected analog line receiver is
NULL NA oversampled at 8X relative to the word rate programmed in
LO -2 Volts to -8 Volts CTRL0<6:3>. This is 4X oversample of the transition rate since the
code rate for both methods is double the data rate.
The auxiliary BPRZ input detection levels are the same as
standard ARINC 429 levels: The sampler uses three separate shift registers, one each for
Ones, Zero and Null detection. When the input signal is within the
STATE DIFFERENTIAL VOLTAGE
differential voltage range of one of the valid states (One, Zero or
ONE +6.5 Volts to +13 Volts Null) of the selected data format, the sampler clocks “1” into that
NULL +2.5 Volts to -2.5 Volts register and a “0” into the other two. When the signal is outside the
ZERO -6.5 Volts to -13 Volts
differential voltage ranges defined for all the shift registers, a “0” is
The HI-3717 guarantees recognition of these levels with a clocked into all three registers. Only one shift register can clock “1”
common mode voltage with respect to GND less than ±25V for the for a given sample. The Null shift register is only used for the BPRZ
worst case conditions (3.15V supply, 8V HBP signal level and 13V format.
BPRZ signal level).
For Havard Bi-phase, HBP, coding, the sampler validates a HI
Design tolerances guarantee detection of the above levels, so the (One) or LO (Zero) if the signal is in that state for at least two
actual acceptance ranges are slightly larger. If the signal (including samples. There is no Null state for the HBP format.
nulls) is outside the differential voltage ranges, the HI-3717 receiver
The Bi-Polar Return to Zero, BPRZ, coding sampler validates that
rejects the data.
at least two consecutive Ones or two consecutive Zeroes are
followed by at least two consecutive Null states.

DIFFERENTIAL COMPARATORS
VDD AMPLIFIERS
RINA-40

ONE
RINA

GND NULL
VDD

ZERO
RINB

RINB-40
GND
CNTL0<0>
RSEL

FIGURE 7. ARINC 717 Receiver Inputs

HOLT INTEGRATED CIRCUITS

14
 HI-3717

FUNCTIONAL DESCRIPTION (cont.)

Decoders In the 2 Sync-Word Mode, CTRL1<2> = “1”, once two consecutive
valid subframe sync marks are detected, the INSYNC bit is set to “1”
The decoder recovers the clock and resynchronizes each valid one at the next consecutive valid subframe sync mark if it occurs at the
or zero to the transition bit period. proper relationship to the previous valid sync marks. The first valid
The Harvard Bi-phase, HBP, decoder confirms the sampler only subframe sync mark does not have to be SYNC1 in this mode but
provided a valid One or Zero, not both, then detects the presence or each successive subframe sync marks must be the next in the
absence of an edge in the data bit period. The output of the decoder sequence and properly spaced from the preceding valid subframe
is a “1” if there was a transition, otherwise a “0”. sync mark.

The Bi-Polar Return to Zero, BPRZ, decoder confirms the sampler INSYNC is set to “0” when the next expected subframe sync mark is
only provided a valid One or Zero, followed by a valid Null. The missed in the 4 Sync-Word or 2 Sync-Word Modes. The HI-3717
decoder output is a “1” for a valid One and “0” for a valid Zero. sync detection logic is reset and the part initiates the full synchroni-
zation process again. The data from the subframe preceding the
Once the data is captured, it is re-sampled to the recovered first incorrect subframe sync mark should be discarded. No data is
transition rate clock (sample clock sent to the sync detector) and re- passed to the Receive FIFO until synchronization is reestablished.
sampled to recover the data bit rate clock.
There are also two bits in the Receive FIFO Status Register,
The decoders will operate correctly when the input data bit period is RXFSTAT<6:5> that provide a realtime indicator when each of the
not more than 2 sample clocks (25%) larger or 1 sample clock four ARINC 717 subframe sync marks are received. The bits are
(12.5%) smaller than the nominal value. The slower input frequency valid only when INSYNC is “1” and are updated when the subframe
causes a mismatch between the sampled data and the recovered sync word is loaded into the Receive FIFO.
clock. The faster input frequency causes issues with internal edge
detection logic. The final mode is No Synchronization, CRTL1<1> = “1”. In this
mode data is captured and loaded directly to the Receive FIFO in
the order it was received. It is the responsibility of the user to extract
the data from the FIFO and determine word, frame and subframe
SYNC Detect boundaries. The INSYNC bit remains “0” while in this mode.
The HI-3717 employs a proprietary, four level sync algorithm that Receive FIFO and Retrieving Data
samples each bit and compares each combination of 12-bits
against the four valid ARINC 717 subframe sync marks. Data is transferred from the Receive FIFO starting with the valid
subframe sync mark when INSYNC was set to “1” and continues
In 4 Sync-Word Mode, once a valid SYNC1 mark is discovered, it with each consecutive 12-bit word until INSYNC is set to “0”.
continues to look for each of the next three subframe sync marks in
the proper order and timing. If any one is not found, the search Each time a valid ARINC 717 word is loaded to the Receive FIFO the
starts over looking for SYNC1 again. Once all four sync marks are RFFULL, RFHALF and RFEMPTY bits in the Receive FIFO Status
detected in the proper order and location in a frame, the INSYNC Register (RXFSTAT<4:2>) are updated. Each word is retrieved
pin is set to “1” at the next SYNC1 subframe sync mark if it is the from the Receive FIFO via the SPI interface using SPI Op-code
correct value and it occurs at the proper relationship to the previous instruction 0xF6 (word only), 0xFE (word & word count) or 0xC
valid sync mark. This is the default synchronization mode for the (Fast Read).
HI-3717.

SYNC DETECTION
ONES SHIFT REGISTER INSYNC
HBP
DECODER
HBP / BPRZ 12-BIT SERIAL 12-BIT SERIAL
SELECT REGISTER INPUT REGISTER

NULL SHIFT REGISTER

12-BIT COMPARATOR
32 WORD x 12-BIT
RECEIVE FIFO
BPRZ WORD
DECODER WORD COUNT CLOCK
ZEROS SHIFT REGISTER &
SUBFRAME
12-BIT SERIAL to Line Drivers
DETECTION
INPUT REGISTER

ACLK DATA CLOCK CTRL0<0>

RFIFO
DIVIDER ROVF
SYNC0
CTRL0<6:4>
SYNC1
RSEL

FIGURE 8. ARINC 717 Receiver Block Diagram

HOLT INTEGRATED CIRCUITS

15
 HI-3717

FUNCTIONAL DESCRIPTION (cont.)

The SPI read instruction 0xF6 format is an 8-bit op-code followed by The Receive FIFO half-full flag, the RFHALF bit (RXFSTAT<3), is
two 8-bit data words. The four most significant bits (MSB) of the first set to “1” whenever the Receive FIFO contains exactly 16 words.
data word are always “0” followed by the first four MSB of the ARINC The RFHALF bit provides a useful indicator to the host CPU that the
717 word. The second data word contains the remaining 8-bits of FIFO is filling up.
the ARINC 717 word. The least significant bit (LSB) of the ARINC
717 word is the LSB of the second 8-bit data word. The Receive FIFO empty, the RFEMPTY bit (RXFSTAT<2>), is set
to “1” when the Receive FIFO is empty. It is reset to “0” when there
The format for read word and word count instruction 0xFE is the is at least one word in the Receive FIFO.
same as the read instruction with the addition of two additional 8-bit
data bytes that contain the word count and the corresponding sync When the HI-3717 attempts to load a valid word to a full Receive
subframe information. The third 8-bit SPI data byte contains the 8 FIF0, the RFOVF flag, RXFSTAT<1>, and the external RFOV pin
MSB bits of the word count. The fourth data byte is comprised of are set to “1”. The Receive FIFO ignores any attempt to load any
remaining 5 bits of the word count as well as the two bit code for the additional words if it is full. The RFOVF flag and RFOV pin are reset
subframe number in the same format as described in the RFXSTAT to “0” when either the INSYNC goes to “0” or the device is reset.
Register Description. Refer to Example 5 in Figure 5 for more The external RFIFO pin is programmable in the FIFO Status Pin
details on the format for this instruction. Assignment Register (FSPIN<7:6>) to reflect the value of the
The Fast Read instruction 0xC uses only one SPI data byte for a RFFULL, RFHALF or the RFEMPTY status bit. Refer to the FSPIN
read operation. This is accomplished by using only first four bits for Register Description for the bit values that assign the RFFULL,
the SPI op-code and placing the first four most significant bits of the RFHALF or RFEMPTY status bit to the RFIFO pin. The default
ARINC 717 word in the four remaining bit locations of what are state is assignment of the RFEMPTY bit to the RFIFO pin.
normally part of an op-code. The remaining 8-bits of the ARINC 717 Word Count Utility Register, WRDCNT, is used to cause the
word are in a normal SPI data byte. This method use one less SPI external MATCH pin to be set to”1” when a specific word count is
data byte than a normal read instruction. reached in a specific subframe. WRDCNT<15:3> specifies the
Up to 32 ARINC 717 words may be held in the Receive FIFO. The location in the subframe and WRDCNT<1:0> specifies the
RFFULL bit (RXFSTAT<4>) is set to “1” when the Receive FIFO is subframe that is monitored. MATCH is “1” until the next word is
full. Failure to unload the Receive FIFO when full will result in loss loaded into the Receive FIFO.
of new data words until there are less than 32 words in the FIFO. The Match word and subframe bit assignments of the Word Count
The RFOVF bit (RXFSTAT<1>) and external FROV pin are set to “1” Utility Register, WRDCNT, are found in Table 8.
when an attempt is made to write to a full Receive FIFO.

TXHA
TXHB
HBP HBP TXOUTHA, OUTHA
ENCODER SLEW RATE LINE DRIVER TXOUTHB, OUTHB
&
12 BIT PARALLEL LOOPBACK NOCONV
LOAD SHIFT REGISTER
TEST
BPRZ CONTROL BPRZ TXOUTBA, OUTBA
ENCODER LINE DRIVER TXOUTBB, OUTBB
TXBA
TXBB
BIT CLOCK
WORD CLOCK
&
WORD CLOCK
BIT CLOCK
START
SEQUENCE
32 word x 12 bit FIFO ADDRESS
WORD COUNTER TFIFO
&
LOAD FIFO CONTROL TEMPTY

INCREMENT
WORD COUNT

FIFO
LOADING
SEQUENCER
SCK SPI COMMANDS
CS SPI COMMANDS
SPI INTERFACE DATA
SI CLOCK DATA CLOCK
ACLK
SO CTRL0<6:4>
DIVIDER

FIGURE 9. ARINC 717 Transmitter Block Diagram

HOLT INTEGRATED CIRCUITS

16
 HI-3717

FUNCTIONAL DESCRIPTION (cont.)

TRANSMITTER SYSTEM OPERATION
FIFO Operation The receiver and transmitter always operate at the same data rate.
Otherwise, they operate completely independent of each other.
The HI-3717 Transmit FIFO is loaded with ARINC 717 words The only restrictions are:
awaiting transmission. SPI words are written to the next Transmit
FIFO location with op-code 0x74 or 0x2 (Fast Write). If Transmit 1. The Receive FIFO ignores any attempt to load any additional
FIFO Status Register empty flag, the TFEMPTY (TXFSTAT<5>) words if it is full and at least one location is not retrieved
bit, is “1” (FIFO empty), then up to 32 ARINC 717 12-bit words can before the next valid ARINC 717 is received.
be safely loaded via the SPI interface. If the TFEMPTY bit is “0”
2. The Transmit FIFO can store a maximum of 32 words and
then less than 32 positions are available. If all 32 positions are
ignores any attempt to store additional words when it is full.
filled, then the Transmit FIFO is full. Any further attempt to load the
Transmit FIFO is ignored until the FIFO contains less than 32 DC/DC Converter
words.
The HI-3717 requires only a single +3.3V power supply. An
The Transmit FIFO half-full flag, the TFHALF (TXFSTAT<6>) bit in integrated inverting / non-inverting voltage doubler generates the
the Transmit FIFO Status Register, is equal to “0” when there are rail voltages (±5.7V) which then power the line drivers to produce
less than or more than 16 ARINC 717 words in the Transmit FIFO the required +5V ARINC 717 HBP and ±5V ARINC 717 BPRZ
and equal to “1” when there are exactly 16 words in the FIFO. The signal levels.
host CPU can safely load 16 ARINC 717 words into the Transmit
FIFO only when TFHALF is “1”. The internal dual-polarity charge pump requires four external
capacitors, two for each polarity generated by the charge pump.
The Transmit FIFO status (Full or Half-Full) is available on the Pins C1+ and C1- connect the external “fly” capacitor, CFLY, to the
external TFIFO pin, depending on the value in FSPIN<5> of the positive portion of the charge pump, resulting in 5.7V at the V+ pin
FIFO Status Pin Assignment Register (See Table 7). The state of that is generated by an on-board bandgap reference voltage. An
the TFIFO pin is reflected in bit TFIFO in TXFSTAT<7>. The state output “hold” capacitor, COUT, is placed between V+ and GND.
of TFEMPTY flag is always on the external TEMPTY pin. The inverting negative portion of the converter works in a similar
It is the user’s responsibility to load the correct subframe sync fashion, with CFLY and COUT placed between C2+ / C2- and V- /
mark in the first word of each subframe and ensure the Transmit GND respectively (see block diagram page 2). See Converter
FIFO is not left empty for more than one word time for continuous Characteristics table for recommended capacitor specifications.
transmissions. Line Driver Operation
The SPI format for writing an ARINC 717 word and Fast Word to The line drivers in the HI-3717 directly drive the ARINC 717
the HI-3717 Transmit FIFO is the same as the read format, except buses. The two ARINC 717 HBP outputs (TXOUTHA and
the most significant bit of the op-code instruction is “0” rather than TXOUTHB) provide a differential voltage of ±5V in accordance
a “1”. with the Harvard Bi-Phase format. Control Register 0
Data Transmission (CTRL0<6:4) controls the transmitter data rate and CTRL0<2:1>
controls the output slew rate.
The ARINC 717 transmission begins when the first word is loaded
into the Transmit FIFO. Each word is serially fed to both the HBP The two auxillary ARINC 717 BPRZ outputs (TXOUTBA and
and BPRZ encoders at the data rate programmed in Control TXOUTBB) provide a differential voltage to produce a +10V One,
Register 0, CTRL0<6:4>. The output of each encoder drives its a -10V Zero, and a 0 Volt Null. The transmitter data rate is the
own ARINC 717 analog line driver. The slew rate of both the HBP same as the HBP output which is also controlled by the same bits
and the BPRZ auxiliary outputs is controllable with CTRL0<2:1>. in Control Register 0 (CTRL0<6:4). The slew rate of the differen-
Refer to the CTRL0 Register Description for the individual bit tial output signal is also controlled by Control Register 0
values required for setting the desired data and output slew rate. (CTRL0<2:1>. No additional hardware is required to control the
slope. Slope rate is set by on-chip resistors and capacitors.

HOLT INTEGRATED CIRCUITS

17
 HI-3717

FUNCTIONAL DESCRIPTION (cont.)

Line Driver Output Pins By keeping excessive voltage outside the device, the RINA/B-40
input option is helpful in applications where lightning protection is
The Harvard Bi-phase (HBP) TXOUTHA and TXOUTHB pins as required.
well as the Bi-Polar Return to Zero (BPRZ) TXOUTBA and
TXOUTBB pins have 37.5 Ohms in series with each line driver Please refer to the Holt AN-300 Application Note for additional in-
output, and may be directly connected to an ARINC 717 bus. formation and recommendations on lightning protection of Holt
The OUTHA, OUTHB, OUTBA and OUTBB pins have 5 Ohms of line drivers and line receivers.
internal series resistance and require an external 32.5 ohm
resistor in series with each pin. OUTHA, OUTHB, OUTBA and Master Reset
OUTBB pins are for applications where external series resis- Application of a Master Reset with a 100ns active low pulse to the
tance is applied, typically for lightning protection devices. external MR pin sets all registers to their default values, places
Either the TXOUTHA & TXOUTHB outputs or the OUTHA & the Receive and Transmit FIFOs to their empty state, and clears
OUTHB outputs are used in an application but not both sets at the sync detection logic. It also sets both the HBP and BPRZ out-
the same time. Likewise, only one set of the auxiliary BPRZ puts to the high impedance state and disables input sampling of
output pins (TXOUTBA & TXOUTBB or OUTBA & OUTBB) are both analog line receivers..
used. Using both set of pins on either output will produce Software Reset
unpredictable results.
A software reset is also possible via the SPI communications in-
The line driver outputs TXOUTHA, TXOUTHB, OUTHA, OUTHB,
terface by writing a “1” to the CTRL1<3>. This bit places both the
TXOUTBA, TXOUTBB, OUTBA & OUTBB are in a high imped-
Receive and Transmit FIFO’s in the empty state, clears the sync
ance state after any reset and when in the digital loopback test
detection logic, sets both the HBP and BPRZ line drivers to a high
mode (CTRL1<0> = “1”) allowing multiple line drivers to be
impedance state and disables the input sampling of both analog
connected to a single ARINC 717 bus. Note that both analog line
line receivers. Unlike POR and MR, ALL other registers remain
receivers are also disconnected from the HBP and BPRZ input
unchanged. The device is held in the reset state until a “0” is writ-
data samplers during reset and when in the digital loopback
ten to CTRL1<3>.
mode.
The HI-3717 also has digital outputs from both the HBP (TXHA &
No DC/DC Converter Option
TXHB) and the BPRZ (TXBA & TXBB) encoders allowing the use The NOCONV pin is set to “1” to disable the internal DC/DC Con-
of external ARINC 717 line drivers. All four of these output pins verter and supply +5V & -5V to the V+ & V- pins respectively from
are active all the time and reflect the digital data sent to the data an external power source. The “fly” capacitor pins can be left
sampler in the digital loopback mode. floating.
Line Receiver Input Pins No Internal Line Drive Option
The HI-3717 has two sets of Line Receiver input pins that are The HI-3717 can be used without the internal line drivers if only
shared with the HBP and BPRZ line receivers, RINA/B and the ARINC 717 receive function is required or if the user wants to
RINA/B-40. Only one pair may be used to connect to the ARINC use his own external ARINC 717 line drivers connected to the
717 bus. The unused pair must be left floating. The RINA/B pins TXHA, TXHB, TXBA & TXBB digital transmitter outputs. For this
may be connected directly to the ARINC 717 bus. option, NOCONV pin is set to “1” to disable the internal line driv-
The RINA/B-40 pins require an external 40K ohm resistor in se- ers, V+ is connected to VDD & V- is left unconnected.
ries with each ARINC 717 input. The resistors do not affect the
ARINC 717 receiver level detection thresholds .
When using the RINA/B-40 pins, each side of the ARINC 717
bus must be connected through a 40K ohm series resistor in or-
der for the chip to detect the correct ARINC 717 levels. The typi-
cal ARINC 717 differential signal is translated and input to a win-
dow comparator and latch. The comparator levels are set so
that with the external 40K ohm resistors, they are just below the
standard minimum data threshold and in the case of the auxil-
iary BPRZ line receiver, just above the standard 2.5 volt BPRZ
(ARINC 429) null threshold.

HOLT INTEGRATED CIRCUITS

18
 HI-3717

TIMING DIAGRAMS
t CPH

t CYC
CS
tCHH
t CES t SCKF t CEH
SCK
t DS t DH t SCKR
SI MSB LSB

FIGURE 10. SPI Serial Input Timing

t CPH

CS

t SCKH tSCKL
SCK

t DV t CHZ
SO
MSB LSB
Hi Impedance Hi Impedance

FIGURE 11. SPI Serial Output Timing

HBP DATA

BPRZ DATA

INSYNC
12 Data Bits

RFIFO (RFEMPTY) tREMPTY

RFIFO (RFFULL)

ROVF 12 Data Bits

tROVF

FIGURE 12. Receive FIFO Flag Timing

2nd to
LAST WORD LAST TRANSMIT FIFO WORD
Bit 10 Bit 11 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11
HBP DATA

BPRZ DATA

tTEMPTY

TEMPTY

FIGURE 13. Transmit FIFO Empty Flag Timing

HOLT INTEGRATED CIRCUITS

19
 HI-3717

TIMING DIAGRAMS (cont.)

HBP BIT HBP BIT HBP BIT

Data Bit 0 Data Bit 1 Data Bit 11
+5V +5V +5V
TXOUTHA & OUTHA
0V
0V
+5V +5V
TXOUTHB & OUTHB 0V 0V 0V

tfx trx
+5V +5V +5V
VDIFF
10% 90%
(TXOUTHA - TXOUTHB 0V
&
OUTHA - OUTHB) 90% -5V 10% -5V
one level zero level

FIGURE 14. Harvard Bi-Phase (HBP) Output Waveforms

BPRZ BIT BPRZ BIT BPRZ BIT

Data Bit 0 Data Bit 1 Data Bit 11
+5V +5V
TXOUTBA & OUTBA

-5V

+5V

TXOUTBB & OUTBB

-5V -5V

tfx
+10V +10V
90%
VDIFF tfx trx
10%
(TXOUTBA - TXOUTBB
&
OUTBA - OUTBB) trx 10%

one level zero level 90% null level

-10V

FIGURE 15. Bi-Polar Return to Zero (BPRZ) Output Waveforms

Data Bit 0 Data Bit 1 Data Bit 11

HARVARD BI-PHASE (HBP)
+3.3V +3.3V +3.3V
TXHA 90% 90%
10% 10% 0V 0V
tHr tHf +3.3V +3.3V
TXHB 0V 0V 0V

BI-POLAR RETURN ZERO (BPRZ)

+3.3V +3.3V
TXBA 90% 90%
10% 10% 0V 0V
tBr tBf
+3.3V
TXBB 0V 0V 0V

one level null level zero level

FIGURE 16. Harvard Bi-Phase (HBP) & Bi-Polar Return to Zero (BPRZ) Logic Output Waveforms

HOLT INTEGRATED CIRCUITS

20
 HI-3717

ABSOLUTE MAXIMUM RATINGS

Supply Voltages VDD ......................................... -0.3V to +5.0V Power Dissipation at 25°C
V+ ......................................................... +7.0V Plastic Quad Flat Pack ............... 1.5 W, derate 10mW/°C
V- ......................................................... -7.0V

Voltage at pins RINxx-xx .................................. -120V to +120V DC Current Drain per digital input pin ........................... ±10mA

Voltage at pins TXAOUT, TXBOUT, AMPA, AMPB ......... V- to V+ Storage Temperature Range ........................ -65°C to +150°C

Voltage at any other pin ...............................-0.3V to VDD +0.3V Operating Temperature Range (Industrial): ..... -40°C to +85°C
(Hi-Temp): ..... -55°C to +125°C

Solder temperature (Reflow) ............................................. 260°C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range (unless otherwise specified).

LIMITS
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX

HARVARD BI-PHASE (HBP) INPUTS - Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)

HBP Differential Input Voltage: (RINA to RINB) HI VIHH Common mode voltages less than 2.0 5.0 8.0 V
LO VILH ±25V with respect to GND -8.0 -5.0 -2.0. V

HBP Input Voltage (Ref. to DFDAU Signal Ground)

HI VIHHA 3.5 5.0 6.5 V
RINA
LO VILHA -1.5 0 +1.5 V
HI VIHHB -1.5 0 +1.5 V
RINB
LO VILHB 3.5 5.0 6.5 V

BI-POLAR RETURN TO ZERO (BPRZ) INPUTS - Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)

BPRZ Differential Input Voltage: (RINA to RINB) ONE VIHB Common mode voltages less than 6.5 10.0 13.0 V
ZERO VILB ±25V with respect to GND -13.0 -10.0 -6.5 V
NULL VINUL -2.5 0 +2.5 V

BPRZ Input Voltage (Ref. to DFDAU Signal Ground)

ONE VIHBA 3.25 5.0 6.5 V
RINA
ZERO VILBA -6.5 -5.0 -3.25 V
ONE VIHBB -6.5 -5.0 -3.25 V
RINB
ZERO VILBB 3.25 5.0 6.5 V

HARVARD BI-PHASE (HBP) & BI-POLAR RETURN TO ZERO (BPRZ) INPUTS

Input Resistance: Differential RI - 140 - KΩ

To GND RG - 140 - KΩ
To VDD RH - 100 - KΩ

Input Current: Input Sink IIH 200 µA

Input Source IIL -450 µA

Input Capacitance: Differential CI (RINA to RINB) 20 pF

(Guaranteed but not tested) To GND CG 20 pF
To VDD CH 20 pF

LOGIC INPUTS

Input Voltage: Input Voltage HI VIH 80% VDD V

Input Voltage LO VIL 20% VDD V

Input Current: Input Sink IIH 1.5 µA

Input Source IIL -1.5 µA
Pull-down Current (MR, SI, SCK, ACLK pins) IPD 60 µA
Pull-up current (CS pin) IPU -60 µA

HOLT INTEGRATED CIRCUITS

21
 HI-3717

DC ELECTRICAL CHARACTERISTICS (cont.)

VDD = 3.3V, TA = Operating Temperature Range (unless otherwise specified).

LIMITS
PARAMETER SYMBOL CONDITIONS UNIT
MIN TYP MAX

HARVARD BI-PHASE (HBP) OUTPUTS - Pins TXOUTHA, TXOUTHB, (or OUTHA, OUTHB with external 32.5 Ohms)

HBP output voltage (Differential) HI VOHH 600 ohm load 4.0 5.0 6.0 V
(TXOUTHA to TXOUTHB or OUTHA to OUTHB) LO VOLH -6.0 -5.0 -4.0 V

HBP output voltage (Ref to GND)

HI VOHHA 600 ohm load 4.5 5.0 5.5 V
TXOUTHA or OUTHA
LO VOLHA -0.5 0 +0.5 V
HI VOHHB -0.5 0 +0.5 V
TXOUTHB or OUTHB
LO VOLHB 4.5 5.0 5.5 V

BI-POLAR RETURN TO ZERO (BPRZ) OUTPUTS - Pins TXOUTBA, TXOUTBB, (or OUTBA, OUTBB with external 32.5 Ohms)

BPRZ output voltage (Differential) ONE VOHB No load 9.0 10.0 11.0 V
(TXOUTBA to TXOUTBB or OUTBA to OUTBB) ZERO VOLB -11.0 -10.0 -9.0 V
NULL VONUL -0.5 0 +0.5 V

BPRZ output voltage (Ref to GND)

ONE VOHBA No load 4.5 5.0 5.5 V
TXOUTBA or OUTBA
ZERO VOLBA -5.5 -5.0 -4.5 V
ONE VOHBB -5.5 -5.0 -4.5 V
TXOUTBB or OUTBB
ZERO VOLBB 4.5 5.0 5.5 V

HARVARD BI-PHASE (HBP) and BI-POLAR RETURN TO ZERO (BPRZ) OUTPUTS

Output current IOUT Momentary short-circuit current 80 mA

LOGIC OUTPUTS (Including TXHA, TXHB, TXBA & TXBB)

Output Voltage: Logic "1" Output Voltage VOH IOH = -100µA 90%VDD V
Logic "0" Output Voltage VOL IOL = 1.0mA 10% VDD V

Output Current: Output Sink IOL VOUT = 0.4V 1.6 mA

Output Source IOH VOUT = VDD - 0.4V -1.0 mA

Output Capacitance: CO 15 pF

OPERATING VOLTAGE RANGE

VDD 3.15 3.45 V

OPERATING SUPPLY CURRENT

Transmitting Data at 8192 words/sec. IDD Outputs Unloaded 35 mA

Transmitting Data in 8192 words/sec. IDDL 600 Ohm Differential Output Load HBP 120 mA
400 Ohm Differential Output Load BPRZ

HOLT INTEGRATED CIRCUITS

22
 HI-3717

AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, TA = Operating Temperature Range and ACLK=24MHz +0.1%
LIMITS
PARAMETER SYMBOL UNITS
MIN TYP MAX
SPI INTERFACE TIMING
SCK clock period tCYC 100 ns
CS active after last SCK rising edge tCHH 5 ns
CS setup time to first SCK rising edge tCES 5 ns
CS hold time after last SCK falling edge tCEH 5 ns
CS inactive between SPI instructions tCPH 55 ns
SPI SI Data set-up time to SCK rising edge tDS 10 ns
SPI SI Data hold time after SCK rising edge tDH 10 ns
SCK rise time tSCKR 10 ns
SCK fall ime tSCKF 10 ns
SCK pulse width high tSCKH 20 ns
SCK pulse width low tSCKL 25 ns
SO valid after SCK falling edge tDV 35 ns
SO high-impedance after CS inactive tCHZ 30 ns
MR pulse width tMR 40 ns
RECEIVER TIMING
Delay - INSYNC high to REMPTY low (plus 12 data bits) tREMPTY 100 ns
Delay - RFFULL high to ROVF high (plus 12 data bits) tROVF 100 ns
TRANSMITTER TIMING
TFEMPY flag high to beginningt of first data bit of last word in Transmit FIFO
32 words / sec. tTEMPTY (32 wps) 2604 µs
64 words / sec. tTEMPTY (64 wps) 1302 µs
128 words / sec. tTEMPTY (128 wps) 651 µs
256 words / sec. tTEMPTY (256 wps) 326 µs
512 words / sec. tTEMPTY (512 wps) 163 µs
1024 words / sec. tTEMPTY (1024 wps) 81.4 µs
2048 words / sec. tTEMPTY (2048 wps) 41.7 µs
4094 words / sec. tTEMPTY (4096 wps) 20.4 µs
8192 words / sec. tTEMPTY (8192 wps) 10.2 µs
Line driver transition differential times (Both the Harvard Bi-Phase and Bi-Polar Return to Zero are set to the same slew rate)
CNTL0<2:1> = 00 high to low tfx 5.0 7.5 10 µs
low to high trx 5.0 7.5 10 µs
CNTL0<2:1> = 01 or 10 high to low tfx 5.0 10 15 µs
low to high trx 5.0 10 15 µs
CNTL0<2:1> = 11 high to low tfx 1.0 1.5 2.0 µs
low to high trx 1.0 1.5 2.0 µs
Transmitter digital outputs transition times
Harvard Bi-Phase (HBP) high to low tHf 3.0 5.0 ns
low to high tHr 3.0 5.0 ns
Bi-Polar Return to Zero (BPRZ) high to low tBf 3.0 5.0 ns
low to high tBr 3.0 5.0 ns

HOLT INTEGRATED CIRCUITS

23
 HI-3717

CONVERTER CHARACTERISTICS
VDD = +3.3V, TA = Operating Temperature (unlesss otherwise stated)
LIMITS
PARAMETER SYMBOL TEST CONDITIONS UNITS
MIN TYP MAX
Start-up transient (V+, V-) tSTART - - 10 ms
Operating Switching Frequency fSW - 650 - kHz
Worst case maximum voltage doubler output VDD2+(max) VDD = 3.6V, T= -55C, Open load - 6.93 V
VDD2-(max) - -6.93 V
Capacitor Requirements (see block diagram on p. 2 for capacitor placement)

V+ Fly-back capacitor, non-polarized CFLY+ 0.47 - - µF

x7R MLCC, 10V minimum ESR(CFLY+) 500 kHz 500 mW
V- Fly-back capacitor, non-polarized CFLY- 2.2 - - µF
x7R MLCC, 10V minimum ESR(CFLY-) 500 kHz 500 mW
Two bulk storage capacitors, non-polarized COUT 10 - 47 µF
X7R MLCC or tantalum, 10V minimum ESR(COUT) 500 kHz 300 mW
Supply de-coupling capacitors, CSUPPLY Two parallel capacitors - 0.1 - µF
x7R MLCC or tantalum, 10V minimum 10 47 µF

HEAT SINK - CHIP-SCALE PACKAGE ONLY

The HI-3717PCx uses a 44-pin plastic chip-scale package. To enhance thermal dissipation, the heat sink can be
This package has a metal heat sink pad on its bottom soldered to matching circuit board pad.
surface. This heat sink is electrically isolated from the die.

HOLT INTEGRATED CIRCUITS

24
 HI-3717

ORDERING INFORMATION
HI - 3717 PQ x x PART LEAD
NUMBER FINISH
Blank Tin / Lead (Sn / Pb) Solder
F 100% Matte Tin (Pb-free, RoHS compliant)

PART TEMPERATURE BURN

NUMBER RANGE FLOW IN
I -40°C TO +85°C I No
T -55°C TO +125°C T No
M -55°C TO +125°C M Yes

PART PACKAGE
NUMBER DESCRIPTION

PQ 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PMQS)

HI - 3717 PC x x PART LEAD

NUMBER FINISH

Blank NiPdAu
F NiPdAu (Pb-free, RoHS compliant)

PART TEMPERATURE BURN

NUMBER RANGE FLOW IN

I -40°C TO +85°C I No
T -55°C TO +125°C T No
M -55°C TO +125°C M Yes

PART PACKAGE
NUMBER DESCRIPTION
PC 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)

HOLT INTEGRATED CIRCUITS

25
 HI-3717

REVISION HISTORY

P/N Rev Date Description of Change

DS3717 NEW 08/11/11 Initial Release
A 08/23/11 Corrected typographical errors. Deleted QFN power dissipation reference.
B 11/04/11 Updated SPI to 10MHz, added IDD limits, corrected example typographical error.
C 12/20/14 Clarify state of SYNC0:1 pins when INSYNC pin is high. Add converter
characteristics table. Update QFN-44 and PQFP-44 package drawings. Clarify
solder reflow temperature in Absolute Maximum Ratings.
D 07/08/14 Clarify function of bit 7 in Register TXFSTAT. This bit reflects the status of the
TFIFO pin.
E 10/06/14 Update Converter Characteristics table and text description. Correct converter
caps. ESR values from a “min.” to a max. value. Add CSUPPLY caps. to block
diagram.
F 05/4/15 Clarify that CS must be asserted for every word read from the FIFO (cannot hold
CS low and read multiple words). Remove reference to ARINC 573 standard.
G 08/07/15 Eliminate “Flight” and “Test” mode nomenclature and rename to 4 Sync-Word
mode and 2 Sync-Word mode respectively. Both modes are equally valid to
achieve synchronization. Add note on p. 13 regarding synchronization.
Correct numerous typos.
H 10/23/15 Update SPI Output timing diagram.
Update AC Characteristics for tCHZ description.
I 07/29/16 FIFO operation: TFIFO pin indicates Transmit FIFO status is Full or Half-Full
(not Full or Empty).
Correct labeling error on Figure 10, SPI Serial Input Timing Diagram.
J 07/02/2020 Correct typo in Barker Code on p. 11. “2507” should be “2670”.
Update QFN lead finish to NiPdAu.

HOLT INTEGRATED CIRCUITS

26
 HI-3717 PACKAGE DIMENSIONS

44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) millimeters (inches)

Package Type: 44PCS

7.00 5.50 ± 0.050

BSC
(0.276) (0.217 ± 0.002)

0.50 BSC
(0.0197)

7.00 Top View 5.50 ± 0.050 Bottom

BSC
(0.276) (0.217 ± 0.002) View
0.25 ± 0.050
(0.010 ± 0.002)

0.400 ± 0.050
1.00 Electrically isolated heat (0.016 ± 0.002)
max 0.200 typ sink pad on bottom of
(0.039)
(0.008) package
Connect to any ground or
power plane for optimum
BSC = “Basic Spacing between Centers” thermal dissipation
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

44-PIN PLASTIC QUAD FLAT PACK (PQFP) millimeters (inches)

Package Type: 44PMQS
0.230 MAX.
(0.009)

0.80
BSC
(0.031)
13.200 BSC 10.000 BSC
(0.520) (0.394
SQ. SQ. 0.370 ± 0.080
(0.015 ± 0.003)

0.880 ± 0.150
(0.035 ± 0.006)
1.60
typ
(0.063) 0.20
min
(0.008)

See Detail A
0.30
R MAX.
2.70 2.00 ± 0.20 (0.012)
MAX.
(0.106) (0.079 ± 0.008)
0° £ Q £ 7°
BSC = “Basic Spacing between Centers” 0.13
R MIN. Detail A
is theoretical true position dimension and (0.005)
has no tolerance. (JEDEC Standard 95)

HOLT INTEGRATED CIRCUITS

27