Product Order Technical Tools & Support &

Folder Now Documents Software Community

TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

TPS53513 1.5-V to 18-V (4.5-V to 25-V Bias) Input,

8-A Single Synchronous Step-Down SWIFT™ Converter
1 Features 3 Description
1• Integrated 13.8-mΩ and 5.9-mΩ MOSFETs With The TPS53513 device is a small-sized, synchronous
8-A Continuous Output Current buck converter with an adaptive on-time D-CAP3
control mode. The device offers ease-of-use and low
• Supports All Ceramic Output Capacitors external-component count for space-conscious power
• Reference Voltage 600 mV ±0.5% Tolerance systems.
• Output Voltage Range: 0.6 V to 5.5 V This device features high-performance integrated
• D-CAP3™ Control Mode With Fast Load-Step MOSFETs, accurate 0.5% 0.6-V reference, and an
ResponseSWIFT™ integrated boost switch. Competitive features include
• Auto-Skipping Eco-mode™ for High Light-Load very low external-component count, fast load-
transient response, auto-skip mode operation,
Efficiency
internal soft-start control, and no requirement for
• FCCM for Tight Output Ripple and Voltage compensation.
Requirements
A forced continuous conduction mode (FCCM) helps
• Eight Selectable Frequency Settings from meet tight voltage regulation accuracy requirements
250 kHz to 1 MHz for performance DSPs and FPGAs. The TPS53513
• Precharged Start-up Capability device is available in a 28-pin VQFN package and is
• Built-in Output Discharge Circuit specified from –40°C to +85°C ambient temperature.
• Open-Drain Power-Good Output Device Information(1)
• 3.5 mm × 4.5 mm, 28-Pin, VQFN Package PART NUMBER PACKAGE BODY SIZE (NOM)
• Create a Custom Design Using the TPS53513 TPS53513 VQFN-CLIP (28) 4.50 mm × 3.50 mm
With the WEBENCH® Power Designer
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Server and Cloud-Computing POLs
• Broadband, Networking, and Optical
Communications Infrastructure
• I/O Supplies
Simplified Schematic Efficiency
PGOOD 100
VIN

23 22 21 20 19 18 17 16 15 90
FB

GND

MODE

VREG

VDD

NC

VIN

VIN

VIN

Efficiency (%)

24 VO
PGND 14
25 TRIP
PGND 13 80
26 DNC TPS53513 PGND 12 fSW = 500 KHz, VIN = 12 V, VDD = 5 V
27 GND1
PGND 11 TA = 25°C, L OUT = 1 H, Mode = Auto-skip
PGOOD

28 GND2 70 Vout
VOUT = 0.6 V Vout
V OUT = 1 V
VBST

PGND 10
SW

SW

SW
N/C

SW
EN
RF

Vout
VOUT = 1.2 V Vout
V OUT = 1.5 V
1 2 3 4 5 6 7 8 9 VOUT = 1.8 V
Vout V OUT = 2.5 V
Vout
VOUT = 3.3 V
Vout V OUT = 5 V
Vout
60
VOUT
0 2 4 6 8 10 12
Thermal EN
Pad
Output Current (A) C003
VREG

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 25
2 Applications ........................................................... 1 8.1 Application Information............................................ 25
3 Description ............................................................. 1 8.2 Typical Application ................................................. 25
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 29
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 30
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 30
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 31
6.2 ESD Ratings.............................................................. 4 10.3 Thermal Performance ........................................... 32
6.3 Recommended Operating Conditions....................... 5 11 Device and Documentation Support ................. 33
6.4 Thermal Information .................................................. 5 11.1 Documentation Support ....................................... 33
6.5 Electrical Characteristics........................................... 6 11.2 Documentation Support ........................................ 33
6.6 Typical Characteristics .............................................. 8 11.3 Receiving Notification of Documentation Updates 33
7 Detailed Description ............................................ 14 11.4 Community Resources.......................................... 33
7.1 Overview ................................................................. 14 11.5 Trademarks ........................................................... 33
7.2 Functional Block Diagram ....................................... 15 11.6 Electrostatic Discharge Caution ............................ 33
7.3 Feature Description................................................. 16 11.7 Glossary ................................................................ 34
7.4 Device Functional Modes........................................ 23 12 Mechanical, Packaging, and Orderable
Information ........................................................... 34

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2014) to Revision C Page

• Added links for WEBENCH ................................................................................................................................................... 1

• Added content to Power-Good ............................................................................................................................................ 22

Changes from Revision A (November 2013) to Revision B Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
• Changed MODE pin configuration reference from "Table 3" to "Table 4" in the D-CAP3 Mode section. ........................... 19

Changes from Original (September 2013) to Revision A Page

• Added updates to front page graphics ................................................................................................................................... 1

• Added updates to Pin Descriptions ........................................................................................................................................ 3
• Added 5-V LDO and VREG Start-Up section ....................................................................................................................... 16
• Added Enable, Soft Start, and Mode Selection section ....................................................................................................... 16
• Added updates to Application Information section ............................................................................................................... 24
• Added Thermal Performance section ................................................................................................................................... 32

2 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

5 Pin Configuration and Functions

RVE Package
28-Pin VQFN-CLIP
Top View

GND2

GND1

TRIP
DNC

VO
28 27 26 25 24

RF 1 23 FB

PGOOD 2 22 GND

EN 3 21 MODE

VBST 4 20 VREG
TPS53513
NC 5 19 VDD

SW 6 18 NC

SW 7 17 VIN

SW 8 16 VIN
Thermal Pad
SW 9 15 VIN

10 11 12 13 14
PGND

PGND
PGND

PGND
PGND

Pin Functions
PIN
I/O (1) DESCRIPTION
NAME NO.
EN 3 I The enable pin turns on the DC-DC switching converter.
FB 23 I VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND.
This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane
GND 22 G with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the
thermal pad to PGND pins and PGND plane).
GND1 27 I Connect this pin to ground. GND1 is the input of unused internal circuitry and must connect to ground.
GND2 28 I Connect this pin to ground. GND2 is the input of unused internal circuitry and must connect to ground.
The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also
MODE 21 I
selects the ramp coefficient of D-CAP3 mode.
5
NC — Not connected. These pins are floating internally.
18
DNC 26 O Do not connect. This pin is the output of unused internal circuitry and must be floating.
10
11
PGND 12 G These ground pins are connected to the return of the internal low-side MOSFET.
13
14
Open-drain power-good status signal which provides startup delay after the FB voltage falls within the
PGOOD 2 O
specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs.
RF is the SW-frequency configuration pin. Connect this pin to a resistor divider between VREG and
RF 1 I
GND to program different SW frequency settings.
6
7
SW I/O SW is the output switching terminal of the power converter. Connect this pin to the output inductor.
8
9

(1) I = Input, O = Output, P = Supply, G = Ground

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Pin Functions (continued)

PIN
I/O (1) DESCRIPTION
NAME NO.
TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at room temp, 3000 ppm/°C current is
TRIP 25 I/O sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for
detailed OCP setting.
VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor
VBST 4 P
from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch.
VDD 19 P Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V.
15
VIN 16 P VIN is the conversion power-supply input pins.
17
VREG 20 O VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver.
VO 24 I VOUT voltage input to the controller.

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
EN –0.3 7.7
DC –3 30
SW
Transient < 10 ns –5 32
VBST –0.3 36
(2) (3)
Input voltage range VBST –0.3 6 V
VBST when transient < 10 ns 38
VDD –0.3 28
VIN –0.3 30
VO, FB, MODE, RF –0.3 6
PGOOD –0.3 7.7
Output voltage range V
VREG, TRIP –0.3 6
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Voltage values are with respect to the SW terminal.

6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2500
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
EN –0.1 7
SW –3 27
VBST –0.1 28
Input voltage range VBST (1) –0.1 5.5 V
VDD 4.5 25
VIN 1.5 18
VO, FB, MODE, RF –0.1 5.5
Output voltage range PGOOD –0.1 7
V
VREG, TRIP –0.1 5.5
TA Operating free-air temperature –40 85 °C

(1) Voltage values are with respect to the SW pin.

6.4 Thermal Information

TPS53513
(1)
THERMAL METRIC RVE (VQFN-CLIP) UNIT
28 PINS
RθJA Junction-to-ambient thermal resistance (2) 37.5
(3)
RθJC(top) Junction-to-case (top) thermal resistance 34.1
RθJB Junction-to-board thermal resistance (4) 18.1
°C/W
ψJT Junction-to-top characterization parameter (5) 1.8
ψJB Junction-to-board characterization parameter (6) 18.1
(7)
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

6.5 Electrical Characteristics

over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TA = 25°C, No load
IVDD VDD bias current 1350 1850 µA
Power conversion enabled (no switching)
TA = 25°C, No load
IVDDSTBY VDD standby current 850 1150 µA
Power conversion disabled
IVIN(leak) VIN leakage current VEN = 0 V 0.5 µA
VREF OUTPUT
VVREF Reference voltage FB w/r/t GND, TA = 25°C 597 600 603 mV
FB w/r/t GND, TJ = 0°C to 85°C –0.6% 0.5%
VVREFTOL Reference voltage tolerance
FB w/r/t GND, TJ = –40°C to 85°C –0.7% 0.5%
OUTPUT VOLTAGE
IFB FB input current VFB = 600 mV 50 100 nA
IVODIS VO discharge current VVO = 0.5 V, Power Conversion Disabled 10 12 15 mA
SMPS FREQUENCY
VIN = 12 V, VVO = 3.3 V, RDR < 0.041 250
VIN = 12 V, VVO = 3.3 V, RDR = 0.096 300
VIN = 12 V, VVO = 3.3 V, RDR = 0.16 400
VIN = 12 V, VVO = 3.3 V, RDR = 0.229 500
fSW VO switching frequency (1) kHz
VIN = 12 V, VVO = 3.3 V, RDR = 0.297 600
VIN = 12 V, VVO = 3.3 V, RDR = 0.375 750
VIN = 12 V, VVO = 3.3 V, RDR = 0.461 850
VIN = 12 V, VVO = 3.3 V, RDR > 0.557 1000
tON(min) Minimum on-time TA = 25°C (2) 60 ns
tOFF(min) Minimum off-time TA = 25°C 175 240 310 ns
INTERNAL BOOTSTRAP SW
VF Forward Voltage VVREG–VBST, TA = 25°C, IF = 10 mA 0.15 0.25 V
IVBST VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 µA
LOGIC THRESHOLD
VENH EN enable threshold voltage 1.3 1.4 1.5 V
VENL EN disable threshold voltage 1.1 1.2 1.3 V
VENHYST EN hysteresis voltage 0.22 V
VENLEAK EN input leakage current –1 0 1 µA
SOFT START
tSS Soft-start time 1 ms
PGOOD COMPARATOR
PGOOD in from higher 104% 108% 111%
PGOOD in from lower 89% 92% 96%
VPGTH VDDQ PGOOD threshold
PGOOD out to higher 113% 116% 120%
PGOOD out to lower 80% 84% 87%
IPG PGOOD sink current VPGOOD = 0.5 V 4 6 mA
Delay for PGOOD going in 0.8 1.0 1.2 ms
tPGDLY PGOOD delay time
Delay for PGOOD coming out 2 µs
IPGLK PGOOD leakage current VPGOOD = 5 V –1 0 1 µA

(1) Resistor divider ratio (RDR) is described in Equation 1.

(2) Specified by design. Not production tested.

6 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

Electrical Characteristics (continued)

over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT DETECTION
RTRIP TRIP pin resistance range 20 50 kΩ
RTRIP = 34.8 kΩ 6.2 8.0 9.8
IOCL Current limit threshold, valley A
RTRIP = 25.5 kΩ 4.2 6.2 8.2
Negative current limit threshold, RTRIP = 34.8 kΩ –10.5 –7.9 –5.3
IOCLN A
valley RTRIP = 25.5 kΩ –8.7 –6.1 –3.5
VZC Zero cross detection offset 0 mV
PROTECTIONS
VREG undervoltage-lockout Wake-up 3.25 3.34 3.41
VVREGUVLO V
(UVLO) threshold voltage Shutdown 3.00 3.12 3.19
Wake-up (default) 4.15 4.25 4.35
VVDDUVLO VDD UVLO threshold voltage V
Shutdown 3.95 4.05 4.15
VOVP Overvoltage-protection (OVP) OVP detect voltage 116% 120% 124%
threshold voltage
tOVPDLY OVP propagation delay With 100-mV overdrive 300 ns
VUVP Undervoltage-protection (UVP) UVP detect voltage 64% 68% 71%
threshold voltage
tUVPDLY UVP delay UVP filter delay 1 ms
THERMAL SHUTDOWN
Shutdown temperature 140
TSDN Thermal shutdown threshold (2) °C
Hysteresis 40
LDO VOLTAGE
VREG LDO output voltage VIN = 12 V, ILOAD = 10 mA 4.65 5 5.45 V
VDOVREG LDO low droop drop-out voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C 365 mV
ILDOMAX LDO overcurrent limit VIN = 12 V, TA = 25°C 170 200 mA
INTERNAL MOSFETS
RDS(on)H High-side MOSFET on- TA = 25°C 13.8 15.5 mΩ
resistance
RDS(on)L Low-side MOSFET on- TA = 25°C 5.9 7.0 mΩ
resistance

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

6.6 Typical Characteristics

100 100

90 90
Efficiency (%)

Efficiency (%)
80 80

fSW = 500 KHz, VIN = 12 V, VDD = 5 V fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = Auto-skip TA = 25°C, L OUT = 1 H, Mode = FCCM
70 Vout
VOUT = 0.6 V Vout
V 70 Vout
VOUT = 0.6 V Vout
OUT = 1 V V OUT = 1 V
Vout
VOUT = 1.2 V Vout
V OUT = 1.5 V Vout
VOUT = 1.2 V Vout
V OUT = 1.5 V
VOUT = 1.8 V
Vout V OUT = 2.5 V
Vout VOUT = 1.8 V
Vout V OUT = 2.5 V
Vout
VOUT = 3.3 V
Vout V OUT = 5 V
Vout VOUT = 3.3 V
Vout V OUT = 5 V
Vout
60 60
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Output Current (A) C003 Output Current (A) C004

Figure 1. Efficiency vs Output Current Figure 2. Efficiency vs Output Current

100 100

90 90
Efficiency (%)

Efficiency (%)

80 80

70 fSW = 1 MHz, VIN = 12 V, VDD = 5 V 70 fSW = 1 MHz, VIN = 12 V, VDD = 5 V

TA = 25°C, L OUT = 1 H, Mode = Auto-Skip TA = 25°C, L OUT = 1 H, Mode = FCCM
Vout
V OUT = 0.6 V Vout
V OUT = 11V Vout
V OUT = 0.6 V Vout
V OUT = 11V
60 V 60
OUT = 1.2 V
Vout V OUT = 1.5
Vout 1.5 V V OUT = 1.2 V
Vout V OUT = 1.5
Vout 1.5 V
V OUT = 1.8 V
Vout V OUT = 2.5
Vout 2.5 V V OUT = 1.8 V
Vout V OUT = 2.5
Vout 2.5 V
V OUT =
Vout = 3.3
3.3 V
V V OUT =
Vout = 55 V
V V OUT =
Vout = 3.3
3.3 V
V V OUT =
Vout = 55 V
V
50 50
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Output Current (A) C005 Output Current (A) C006

Figure 3. Efficiency vs Output Current Figure 4. Efficiency vs Output Current

1.3 1.3
fSW = 500 KHz fSW = 1 MHz
VDD = 5 V VDD = 5 V
VOUT = 1.2 V VOUT = 1.2 V
1.25 TA = 25°C 1.25 TA = 25°C
LOUT = 1 H LOUT = 1 H
Mode = Auto-skip Mode = Auto-skip
VOUT (V)

VOUT (V)

1.2 1.2

1.15 V 1.15
IN ==55VV
VIN V IN ==55VV
VIN
VIN
V IN ==12
12VV VIN
V IN ==12
12VV
VIN
V = 18 V
IN = 18 V
VIN
V = 18 V
IN = 18 V
1.1 1.1
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Output Current (A) C007 Output Current (A) C008

Figure 5. Output Voltage vs Output Current Figure 6. Output Voltage vs Output Current

8 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

Typical Characteristics (continued)

1.3 1.3
fSW = 500 KHz fSW = 1 MHz
VDD = 5 V VDD = 5 V
TA = 25°C TA = 25°C
1.25 LOUT = 1 H 1.25 LOUT = 1 H
Mode = FCCM Mode = FCCM
VOUT = 1.2 V VOUT = 1.2 V
VOUT (V)

VOUT (V)
1.2 1.2

1.15 V 1.15
IN ==55VV
VIN V IN ==55VV
VIN
VIN
V IN ==12
12VV VIN
V IN ==12
12VV
VIN
V = 18 V
IN = 18 V
VIN
V = 18 V
IN = 18 V
1.1 1.1
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Output Current (A) C009 Output Current (A) C010

Figure 7. Output Voltage vs Output Current Figure 8. Output Voltage vs Output Current
1200 600
VIN = 12 V, VDD = 5 V, TA = 25°C fSW = 500 kHz
LOUT = 1 H, Mode = FCCM, VOUT = 1.2 V VDD = 5 V
1000 VOUT = 1.2 V
550 TA = 25°C
LOUT = 1 H
Frequency (KHz)

Frequency (KHz)
Fsw
fSW ==250
250KHz
KHz Mode = FCCM
800
Fsw
fSW ==500
500KHz
KHz
fSW ==11MHz 500
Fsw MHz
600

450 V
400 IN ==55VV
VIN
VIN
V IN ==12
12VV
VIN
V = 18 V
IN = 18 V
200 400
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) C011 Output Current (A) C012

Figure 9. Switching Frequency vs Output Current Figure 10. Switching Frequency vs Output Current
90 90
85 85
80 80
75 75
70 70
65 65
60 60
Ta (°C)

Ta (ºC)

55 55
50 50
45 45
40 40
35 35
30 200LFM 30 200LFM
25 Nat conv 25 Nat conv
20 20
0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12
Iout (Amps) D001
Iout (Amps) D002
VIN = 12 V Switching frequency VIN = 12 V Switching frequency
= 600kHz = 600kHz

Figure 11. Safe Operating Area, VO = 1.2 V Figure 12. Safe Operating Area, VO = 5 V

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Typical Characteristics (continued)

VIN = 12 V fSW = 1 MHz VIN = 12 V fSW = 1 MHz

VOUT = 1.2 V IOUT = 0 A VOUT = 1.2 V IOUT = 0 A
Mode = Auto-skip Mode = FCCM

Figure 13. Auto-Skip Mode Steady-State Operation Figure 14. FCCM Steady-State Operation

VIN = 12 V fSW = 1 MHz VIN = 12 V fSW = 1 MHz

VOUT = 1.2 V IOUT = 0.1 A VOUT = 1.2 V IOUT = 0.1 A
Mode = Auto-skip Mode = FCCM

Figure 15. Auto-Skip Mode Steady-State Operation Figure 16. FCCM Steady-State Operation

VIN = 12 V fSW = 1 MHz VIN = 12 V fSW = 1 MHz

VOUT = 1.2 V IOUT = 6 A VOUT = 1.2 V IOUT = 6 A
Mode = Auto-skip Mode = FCCM

Figure 17. Auto-Skip Mode Steady-State Operation Figure 18. FCCM Steady-State Operation

10 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

Typical Characteristics (continued)

fSW = 1 MHz fSW = 1 MHz
VIN = 12 V VIN = 12 V
IDYN = 0 A to 6 A I = 0 A to 6 A
VOUT = 1.2 V
Mode = Auto-skip VOUT = 1.2 V DYN
Mode = FCCM

Figure 19. Auto-Skip Mode Load Transient Figure 20. FCCM Load Transient

VIN = 12 V VIN = 12 V
VOUT = 1.2 V VOUT = 1.2 V
fSW = 1 MHz fSW = 1 MHz
IOUT = 0 A IOUT = 0 A
Mode = Auto-skip Mode = FCCM

Figure 21. Auto-Skip Mode Start-Up Figure 22. FCCM Start-Up

VIN = 12 V VIN = 12 V
VOUT = 1.2 V VOUT = 1.2 V
fSW = 1 MHz fSW = 1 MHz
IOUT = 6 A IOUT = 6 A
Mode = Auto-skip Mode = FCCM

Figure 23. Auto-Skip Mode Start-Up Figure 24. FCCM Start-Up

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Typical Characteristics (continued)

VIN = 12 V VIN = 12 V
VOUT = 1.2 V VOUT = 1.2 V
fSW = 1 MHz fSW = 1 MHz
IOUT = 0 A IOUT = 0 A
Mode = Auto-skip Mode = FCCM

Figure 25. Auto-Skip Mode Shutdown Operation Figure 26. FCCM Shutdown Operation

VIN = 12 V VIN = 12 V
VOUT = 1.2 V VOUT = 1.2 V
fSW = 1 MHz fSW = 1 MHz
IOUT = 6 A IOUT = 6 A
Mode = Auto-skip Mode = FCCM

Figure 27. Auto-Skip Mode Shutdown Operation Figure 28. FCCM Shutdown Operation

VIN = 12 V
VOUT = 1.2 V
VIN = 12 V fSW = 500 kHz
VOUT = 1.2 V IOUT = 0 A
fSW = 1 MHz Mode = Auto-skip
IOUT = 0 A
Pre-bias = 0.6 V
Mode = Auto-skip

Figure 29. Prebias Operation Figure 30. Overvoltage Protection

12 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

Typical Characteristics (continued)

VIN = 12 V
VOUT = 1.2 V
fSW = 500 kHz
Mode = FCCM

fSW = 500 kHz VI = 12 V VO = 5 V

IO = 12 A COUT= 10 × 22 µF (1206, 6.3 V, X5R)
SNB = 3 Ω+ 470 pF RBOOT= 0 Ω
Inductor: LOUT = 1 µH 2.1 mΩ (typical)
PCMC135T-1R0MF 12.6 mm × 13.8 mm × 5 mm

Figure 31. Overcurrent Protection ℃, SP2: 57.7℃

Figure 32. SP1: 75.6℃ ℃ (Inductor)

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

7 Detailed Description

7.1 Overview
The TPS53513 device is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-
output voltage point-of-load applications with 8-A or lower output current in computing and similar digital
consumer applications. The TPS53513 device features proprietary D-CAP3 mode control combined with adaptive
on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC
converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage
ranges from 1.5 V to 18 V and the VDD input voltage ranges from 4.5 V to 25 V. The D-CAP3 mode uses
emulated current information to control the modulation. An advantage of this control scheme is that it does not
require a phase-compensation network outside which makes the device easy-to-use and also allows low-external
component count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and
output voltage while increasing switching frequency as needed during load-step transient.

14 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

7.2 Functional Block Diagram

PGOOD
0.6 V + 8/16% +
0.6 V ± 32% + UV Delay
Delay
+
+ OV 0.6 V ± 8/16% VREG

0.6 V+20%
Internal Ramp Control Logic

UVP / OVP RF
0.6 V +
Logic
SS + PWM
VFB VBST

VIN
10 µA
GND +
1 SHOT
TRIP
LL + OCP

SW
XCON

+ Control
ZC
PGND Logic
PGND

SW

FCCM / SKIP x On/Off time VO

MODE Fault
RC time Constant x Minimum On/Off
x Light load Shut Down
x OVP/UVP LDO VREG
x FCCM/SKIP +
x Soft-Start VREGOK 3.34 V /
3.12 V
EN + + VDD
Enable VDDOK
4.3 V /
1.4 V / 1.2 V
+ 140°C / 4.03 V
GND THOK
100°C NC
GND1

GND2
DPA02259

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

7.3 Feature Description

7.3.1 5-V LDO and VREG Start-Up
The TPS53513 device has an internal 5-V LDO feature using input from VDD and output to VREG. When the
VDD voltage rises above 2.8 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG
voltage provides the bias voltage for the internal analog circuitry. The VREG voltage also provides the supply
voltage for the gate drives.

2.8 V

VDD

VREG

EN
0.6 V

VREF/VDAC

~ 400 µs tSS (1 ms)

VOUT

Figure 33. Power-up Sequence Waveforms

7.3.2 Enable, Soft Start, and Mode Selection

The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin.
When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-
up sequence. The controller then uses the first 400 μs to calibrate the switching frequency setting resistance
attached to the RF pin and stores the switching frequency code in internal registers. During this period, the
MODE pin also senses the resistance attached to this pin to determine the operation mode. In the second phase,
an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. the ramping up time is 1 ms. The
device maintains smooth and constant ramp-up of the output voltage during start-up regardless of load current.

7.3.3 Frequency Selection

TPS53513 device lets users select the switching frequency by using the RF pin. Table 1 lists the divider ratio and
some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical
temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more
reliable SW-frequency detection, use higher performance resistors.

16 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

Table 1. Switching Frequency Selection

SWITCHING RESISTOR EXAMPLE RF FREQUENCY COMBINATIONS
FREQUENCY DIVIDER RATIO (1)
(fSW) (kHz) (RDR) RRF_H (kΩ) RRF_L (kΩ)
1000 > 0.557 1 300
850 0.461 180 154
750 0.375 200 120
600 0.297 249 105
500 0.229 240 71.5
400 0.16 249 47.5
300 0.096 255 27
250 < 0.041 270 11.5

(1) Resistor divider ratio (RDR) is described in Equation 1.

space
RRF _ L
RDR =
(RRF _ L + RRF _ H )
where
• RRF_L is the low-side resistance of the RF pin resistor divider
• RRF_H is the high-side resistance of the RF pin resistor divider (1)

7.3.4 D-CAP3 Control and Mode Selection

RR
SW To comparator

CR

VOUT
Figure 34. Internal RAMP Generation Circuit

The TPS53513 device uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-
use feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The
amplitude of the ramp is determined by the R-C time-constant as shown in Figure 34. At different switching
frequencies, (fSW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.

7.3.4.1 D-CAP3 Mode

From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified
as shown in Figure 35.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

VO CC1 SW
RC1

CC2 VIN
RC2
Sample
and Hold DRVH
PWM Lx
RFBH
Comparator
G + Control
VRAMP VOUT
+ Logic
FB and
Driver DRVL
RCO
+
VREF RLOAD
RFBL COUT

Copyright © 2016, Texas Instruments Incorporated

Figure 35. D-CAP3 Mode

The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR
output capacitors such as multilayered ceramic capacitors (MLCC). No external current sensing network or
voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation
network is to emulate the ripple component of the inductor current information and then combine it with the
voltage feedback signal to regulate the loop operation. For any control topologies supporting no external
compensation design, there is a minimum and/or maximum range of the output filter it can support. The output
filter used with the TPS53513 device is a lowpass L-C circuit. This L-C filter has double pole that is described in
Equation 2.
1
fP =
2 ´ p ´ LOUT ´ COUT (2)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS53513 device. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and increases the phase to 90 degree one decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 2 is
located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero
provides adequate phase margin for the stability requirement.

Table 2. Locating the Zero

SWITCHING
FREQUENCIES ZERO (fZ) LOCATION (kHz)
(fSW) (kHz)
250 and 300 6
400 and 500 7
600 and 750 9
850 and 1000 12

After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max) (peak current in the
application). Use Table 2 to help locate the internal zero based on the selected switching frequency. In general,
where reasonable (or smaller) output capacitance is desired, Equation 3 can be used to determine the necessary
output capacitance for stable operation.

18 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

1
fP = = fZ
2 ´ p ´ LOUT ´ COUT (3)
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and
AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this
case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be
used in the system/applications.
Table 3 shows the recommended output filter range for an application design with the following specifications:
• Input voltage, VIN = 12 V
• Switching frequency, fSW = 600 kHz
• Output current, IOUT = 8 A
The minimum output capacitance is verified by the small-signal measurement conducted on the EVM using the
following two criteria:
• Loop crossover frequency is less than one-half the switching frequency (300 kHz)
• Phase margin at the loop crossover is greater than 50 degrees
For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high
output capacitance for this type of converter design, then verify the small-signal response on the EVM using the
following one criteria:
• Phase margin at the loop crossover is greater than 50 degrees
As indicated by the phase margin, the actual maximum output capacitance (COUT(max)) can continue to go higher.
However, small-signal measurement (bode plot) should be done to confirm the design.
Select a MODE pin configuration as shown in Table 4 to in double the R-C time-constant option for the maximum
output capacitance design and application. Select a MODE pin configuration to use single R-C time constant
option for the normal (or smaller) output capacitance design and application.
The MODE pin also selects skip-mode or FCCM-mode operation.

Table 3. Recommended Component Values

COUT(min) CROSS- PHASE COUT(max) INTERNAL
VOUT RLOWER RUPPER LOUT INDUCTOR ICC(max)
(µF) OVER MARGIN (µF) RC SETTING
(V) (kΩ) (kΩ) (µH) (1) (1) ΔI/ICC(max) (A)
(kHz) (°) (µs)
0.36 3 × 100 247 70 40
0.6 0 33%
PIMB065T-R36MS 48 62 30 x 100 80
0.68 9 × 22 207 53 40
1.2 10 33%
PIMB065T-R68MS 25 84 30 x 100 80
1.2 4 × 22 185 57 40
2.5 10 31.6 34% 8
PIMB065T-1R2MS 11 63 30 x 100 80
1.5 3 × 22 185 57 40
3.3 45.3 33%
PIMB065T-1R5MS 9 59 30 x 100 80
2.2 2 × 22 185 51 40
5.5 82.5 28%
PIMB065T-2R2MS 7 58 30 x 100 80

(1) All COUT(min) and COUT(max) capacitor specifications are 1206, X5R, 10 V.

For higher output voltage at or above 2.0 V, additional phase boost might be required to secure sufficient phase
margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed on time topology
based operation.
A feedforward capacitor placing in parallel with RUPPER is found to be very effective to boost the phase margin at
loop crossover. Refer to TI application note SLVA289 for details.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Table 4. Mode Selection and Internal RAMP R-C Time Constant

SWITCHING
MODE RMODE R-C TIME
ACTION FREQUENCIES
SELECTION (kΩ) CONSTANT (µs)
fSW (kHz)
60 250 and 300
50 400 and 500
0
40 600 and 750
30 850 and 1000
Skip Mode Pull down to GND
120 250 and 300
100 400 and 500
150
80 600 and 750
60 850 and 1000
60 250 and 300
50 400 and 500
20
40 600 and 750
Connect to 30 850 and 1000
FCCM (1)
PGOOD 120 250 and 300
100 400 and 500
150
80 600 and 750
60 850 and 1000
120 250 and 300
100 400 and 500
FCCM Connect to VREG 0
80 600 and 750
60 850 and 1000

(1) Device goes into Forced CCM (FCCM) after PGOOD becomes high.
7.3.4.2 Sample and Hold Circuitry

CSP Sampled_CSP
C1 C2
Buffer 1 Buffer 2

Figure 36. Sample and Hold Logic Circuitry (Patent Pending)

The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry,
which is an advance control scheme to boost output voltage accuracy higher on the device, is one of features of
the device. The sample and hold circuitry generates a new DC voltage of CSN instead of the voltage which is
produced by RC2 and CC2 which allows for tight output-voltage accuracy and makes the device more competitive.

20 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

CSP CSP
CSN CSN
CSN_NEW CSN_NEW
(sample at valley of CSP) (sample at valley of CSP)

Figure 37. Continuous Conduction Mode (CCM) With Figure 38. Discontinuous Conduction Mode (DCM) With
Sample and Hold Circuitry Sample and Hold Circuitry

CSP CSP
CSN CSN

Figure 39. Continuous Conduction Mode (CCM) Without Figure 40. Discontinuous Conduction Mode (DCM) Without
Sample and Hold Circuitry Sample and Hold Circuitry

1.25 1.25

1.23 1.23

1.21 1.21
VOUT (V)

VOUT (V)

1.19 VIN = 12 V 1.19 VIN = 12 V

VDD = 5 V VDD = 5 V
VOUT = 1.2 V VOUT = 1.2 V
fSW = 500 kHz fSW = 500 kHz
1.17 TA = 25°C 1.17 TA = 25°C
D-CAP3 D-CAP3
LOUT = 1 H LOUT = 1 H
Mode = FCCM D-CAP2 Mode = Auto-skip D-CAP2
1.15 1.15
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) C013 Output Current (A) C014

Figure 41. Output Voltage vs Output Current Figure 42. Output Voltage vs Output Current

7.3.4.3 Adaptive Zero-Crossing

The TPS53513 device uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current
detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function
also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.
Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode
conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

7.3.5 Power-Good
The TPS53513 device has power-good output that indicates high when switcher output is within the target. The
power-good function is activated after the soft-start operation is complete. If the output voltage becomes within
±8% of the target value, internal comparators detect the power-good state and the power-good signal becomes
high after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good
signal becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be
pulled up externally.
In applications or end systems where PGOOD signal is needed by the load to sequence additional voltage
supplies, take care to ensure both threshold and noise level/duration are within the design specification. This is
especially true when the PGOOD signal is pulled up to the VREG supply. Because VREG is also being used to
supply the internal FET gate drivers, during the active switching of the FETs, switching spikes associated with
charging and discharging of the input parasitic capacitance of the FETs can be coupled on the VREG supply.
There are 3 intrinsic factors to consider:
1. Level of the spike. The typical spike level could be a few hundred millivolts below VREG. For worst case
design, consider using –500 mV.
2. Duration of the spike. The worst case spike duration could reach 150 ns.
3. DC level of the VREG supply. The DC variation of VREG supply can be found in Electrical Characteristics.
Last, when laying out the TPS53513, follow the Layout Guidelines closely to minimize the noise impact to the
VREG supply. In situations where layout cannot be optimized further, secure real-time measurement to ensure
PGOOD design has sufficient margin.

7.3.6 Current Sense and Overcurrent Protection

The TPS53513 device has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during
the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than
the overcurrent trip level. To provide good accuracy and a cost-effective solution, the TPS53513 device supports
temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage
setting resistor, RTRIP. The TRIP pin sources ITRIP current, which is 10 μA typically at room temperature, and the
trip level is set to the OCL trip voltage VTRIP as shown in Equation 4.
VTRIP = RTRIP ´ ITRIP
where
• VTRIP is in mV
• RTRIP is in kΩ
• ITRIP is in µA (4)
The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly
connected to the drain pin of the low-side MOSFET. ITRIP has a 3000-ppm/°C temperature slope to compensate
the temperature dependency of RDS(on). The GND pin acts as the positive current-sensing node. Connect the
GND pin to the proper current sensing device, (for example, the source pin of the low-side MOSFET.)
Because the comparison occurs during the OFF state, VTRIP sets the valley level of the inductor current. Thus,
the load current at the overcurrent threshold, IOCP, is calculated as shown in Equation 5.

IOCP =
VTRIP
+
IIND(ripple)
=
VTRIP
+
1
´
(VIN - VOUT )´ VOUT
(
8 ´ RDS(on) ) 2 (
8 ´ RDS(on)L )2 ´ L ´ fSW VIN

where
• RDS(on)L is the on-resistance of the low-side MOSFET
• RTRIP is in kΩ (5)
Equation 5 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be
used); to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should be used.
During an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the
output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold
and shuts down.
For the TPS53513 device, the overcurrent protection maximum is recommended up to 12 A only.
22 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

7.3.7 Overvoltage and Undervoltage Protection

The TPS53513 device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage.
When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1 ms, the TPS53513 device latches OFF both
high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS53513 device operates in this cycle until the output
voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side
FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the
EN pin.

7.3.8 Out-Of-Bounds Operation

The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so
the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltage-
protection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning
on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output
capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-by-
cycle negative current limit is also activated to ensure the safe operation of the internal FETs.

7.3.9 UVLO Protection

The TPS53513 device monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-
threshold voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-
threshold voltage, the controller turns back on. UVLO is a nonlatch protection.

7.3.10 Thermal Shutdown

The TPS53513 device monitors internal temperature. If the temperature exceeds the threshold value (typically
140°C), TPS53513 device shuts off. When the temperature falls approximately 40°C below the threshold value,
the device turns on. Thermal shutdown is a nonlatch protection.

7.4 Device Functional Modes

7.4.1 Auto-Skip Eco-mode Light Load Operation
While the MODE pin is pulled to GND directly or through 150-kΩ resistor, the TPS53513 device automatically
reduces the switching frequency at light-load conditions to maintain high efficiency. This section describes the
operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so
that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation IO(LL) (for example: the threshold between continuous-
and discontinuous-conduction mode) is calculated as shown in Equation 6.

IOUT(LL ) =
1
´
(VIN - VOUT )´ VOUT
2 ´ L ´ fSW VIN
where
• fSW is the PWM switching frequency (6)
Using only ceramic capacitors is recommended for Auto-skip mode.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Device Functional Modes (continued)

7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous
conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency at the cost of lower efficiency.

24 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS53513 device is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-
output voltage point-of-load applications with 8-A or lower output current in computing and similar digital
consumer applications.

8.2 Typical Application

This design example describes a D-CAP3-mode, 8-A synchronous buck converter with integrated MOSFETs.
The device provides a fixed 1.2-V output at up to 8 A from a 12-V input bus.

R1
PGOOD
6.65 NŸ
R2 C3 C4
2 kŸ Thermal R6 1 µF 1 µF VIN
Pad 150 NŸ
CIN CIN
23 22 21 20 19 18 17 16 15 2.2 nF 3 × 22 µF
FB

GND

MODE

VREG

VDD

NC

VIN

VIN

VIN
24 VO
PGND 14
25 TRIP
PGND 13
R8 26 DNC
34.8 NŸ TPS53513
PGND 12
27 GND1
PGND 11
PGOOD

28 GND2
VBST

SW

SW

SW
N/C

SW
EN
RF

PGND 10

1 2 3 4 5 6 7 8 9
PIMB065T±1R0MS-63
R4 R10 VOUT
249 NŸ 100 NŸ R7 C2 1 µH
Thermal Pad 0Ÿ 0.1 µF R3 COUT
COUT
3Ÿ
6 × 22 µF 4 × 10 µF
R5
105 NŸ VREG EN
C1
470 pF

Figure 43. Application Circuit Diagram

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

Typical Application (continued)

8.2.1 Design Requirements
This design uses the parameters listed in Table 5.

Table 5. Design Example Specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTIC
VIN Voltage range 5 12 18 V
IMAX Maximum input current VIN = 5 V, IOUT = 8 A 2.5 A
No load input current VIN = 12 V, IOUT = 0 A with auto skip mode 1 mA
OUTPUT CHARACTERISTICS
VOUT Output voltage 1.2 V
Line regulation,
0.2%
5 V ≤ VIN ≤ – 14 V with FCCM
Output voltage regulation
Load regulation,
0.5%
VIN = 12 V, 0 A ≤ IOUT≤ 8 A with FCCM
VRIPPLE Output voltage ripple (VIN = 12 V, IOUT = 8 A with FCCM 10 mVPP
ILOAD Output load current 0 8
A
IOVER Output over current 11
tSS Soft-start time 1 ms
SYSTEMS CHARACTERISTICS
fSW Switching frequency 1 MHz
η Peak efficiency VIN = 12 V, VOUT = 1.2 V ,IOUT = 4 A 88.5%
Full load efficiency VIN = 12 V, VOUT = 1.2 V , IOUT = 8 A 86.9%
TA Operating temperature 25 ºC

8.2.2 Detailed Design Procedure

The external components selection is a simple process using D-CAP3 mode. Select the external components
using the following steps

8.2.2.1 Choose the Switching Frequency

The switching frequency is configured by the resistor divider on the RF pin. Select one of eight switching
frequencies from 250 kHz to 1 MHz. Refer to Table 1 for the relationship between the switching frequency and
resistor-divider configuration.

8.2.2.2 Choose the Operation Mode

Select the operation mode using Table 4.

8.2.2.3 Choose the Inductor

Determine the inductance value to set the ripple current at approximately ¼ to ½ of the maximum output current.
Larger ripple current increases output ripple voltage, improves signal-to-noise ratio, and helps to stabilize
operation.

L=
1
´
(V
IN(max ) - VOUT )´V OUT
=
3
´
(VIN(max ) - VOUT )´V OUT

IIND(ripple ) ´ fSW VIN(max ) IOUT(max ) ´ fSW VIN(max)

3 (12 V - 1.2 V ) ´ 1.2 V

= ´ = 1.08 mH
6 ´ 500kHz 12 V (7)
The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above peak
inductor current before saturation. The peak inductor current is estimated using Equation 8.

26 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

IIND(peak ) =
VTRIP
+
1
´
(
VIN(max ) - VOUT ´ VOUT 10 mA ´ R
=
)
TRIP
+
1
´
(12 V - 1.2 V ) ´ 1.2 V
8 ´ RDS(on ) L ´ fSW VIN(max ) 8 ´ 5.9mW 1mH ´ 500kHz 12 V
(8)

8.2.2.4 Choose the Output Capacitor

The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has two components as shown in Equation 9. Equation 10 and Equation 11 define these
components.
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) (9)
IL(ripple )
VRIPPLE(C ) =
8 ´ COUT ´ fSW (10)
VRIPPLE(ESR ) = IL(ripple ) ´ ESR
(11)

8.2.2.5 Determine the Value of R1 and R2

The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in Equation 12. Connect
R1 between the VFB pin and the output, and connect R2 between the VFB pin and GND. The recommended R2
value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 12.
V - 0.6 1.2 V - 0.6
R1 = OUT ´ R2 = ´ 10kW = 10kW
0.6 0.6 (12)

8.2.3 Application Curves

100 1.3
fSW = 1 MHz
VDD = 5 V
VOUT = 1.2 V
90 1.25 TA = 25°C
LOUT = 1 H
Efficiency (%)

Mode = Auto-skip
VOUT (V)

80 1.2

fSW = 500 KHz, VIN = 12 V, VDD = 5 V

TA = 25°C, L OUT = 1 H, Mode = FCCM
70 Vout
VOUT = 0.6 V Vout
V 1.15
OUT = 1 V V IN ==55VV
VIN
Vout
VOUT = 1.2 V Vout
V OUT = 1.5 V
VIN
V IN ==12
12VV
VOUT = 1.8 V
Vout V OUT = 2.5 V
Vout
VOUT = 3.3 V
Vout V OUT = 5 V
Vout VIN
V = 18 V
IN = 18 V
60 1.1
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Output Current (A) C004 Output Current (A) C008

Figure 44. Efficiency vs Output Current Figure 45. Output Voltage vs Output Current

1.3 600
fSW = 500 KHz fSW = 500 kHz
VDD = 5 V VDD = 5 V
TA = 25°C VOUT = 1.2 V
1.25 LOUT = 1 H 550 TA = 25°C
Mode = FCCM LOUT = 1 H
Frequency (KHz)

VOUT = 1.2 V Mode = FCCM

VOUT (V)

1.2 500

1.15 V 450
IN ==55VV
VIN V IN ==55VV
VIN
VIN
V IN ==12
12VV VIN
V IN ==12
12VV
VIN
V = 18 V
IN = 18 V
VIN
V = 18 V
IN = 18 V
1.1 400
0 2 4 6 8 10 12 1 2 3 4 5 6 7 8 9 10 11 12
Output Current (A) C009 Output Current (A) C012

Figure 46. Output Voltage vs Output Current Figure 47. Switching Frequency vs Output Current

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

PGOOD
PGOOD

VOUT VOUT

SW 50% 50% 50%

SW
CTNL
CTNL

ILOAD = 6 A ILOAD = 6 A

Figure 48. Start-Up Sequence Figure 49. Shutdown Sequence

VOUT VOUT

SW SW

IOUT
IOUT

ILOAD from 0 A to 6 A ILOAD from 6A to 0 A

Figure 50. Load Transient Figure 51. Load Transient

VOUT
VOUT

SW

IOUT SW

ILOAD from 0 A to 6A to 0 A ILOAD = 0 A

Figure 52. Full Cycle Load Transient Figure 53. Output Voltage Ripple

28 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

PGOOD
VOUT
VOUT

SW
SW
EN

ILOAD = 6 A Preset VOUT = 0.5 V

Figure 54. Output Voltage Ripple Figure 55. Prebias Start-Up

9 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 1.5 V and 18 V (4.5 V to 25 V
biased). This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is
also critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in the
Layout section.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

10 Layout

10.1 Layout Guidelines

Before beginning a design using the TPS53513 device, consider the following:
• Place the power components (including input and output capacitors, the inductor, and the DPA02259 device)
on the solder side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert and
connect at least one inner plane to ground.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF must be placed
away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as
ground planes and shield the feedback trace from power traces and components.
• GND (pin 22) must be connected directly to the thermal pad. Connect the thermal pad to the PGND terminals
and then to the GND plane.
• The GND1 terminal (pin 27) and the GND2 terminal (pin 28) are not actual GND terminals and neither of
these terminals should be used for dedicated ground connection. The recommendation is to connect GND1
terminal (pin 27) and the GND2 terminal (pin 28) to the nearby ground.
• Place the VIN decoupling capacitors as close to the VIN and PGND terminals as possible to minimize the
input AC-current loop.
• Place the feedback resistor near the device to minimize the VFB trace distance.
• Place the frequency-setting resistor (RRF), OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE)
close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.
• Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for
each decoupling capacitor and ensure the loop is as small as possible.
• This design defines the PCB trace as a switch node, which connects the SW terminals and high-voltage side
of the inductor. The switch node should be as short and wide as possible.
• Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection
resistor. Do not combine these connections.
• Place one more small capacitor (2.2-nF, 0402 size) between the VIN and PGND terminals. This capacitor
must be placed as close to the device as possible.
• TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction.
The value of snubber design starts at 3 Ω + 470 pF.
• Consider R-C-CC network (ripple injection network) component placement and place the AC coupling
capacitor, CC, close to the device, and R and C close to the power stage. (Application designs with output
capacitance lower than the minimum may require only an R-C-C network. In this case, Bode plot verification
is needed to validate the design).
• See Figure 56 for the layout recommendation.

30 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

10.2 Layout Example

To inner GND plane VIN Shape

CIN

HF cap.

MODE
VREG
GND

VDD
Cc

VIN
VIN
VIN
NC
FB
To VOUT Shape 2 2 2 2 1 1 1 1 1
3 2 1 0 9 8 7 6 5
VO

1
4
PGND
4
2

TRIP

1
3
PGND
5
2

DNC

1
2
PGND
6
2

GND Shape
Trace on inner layer

GND1

1
1
PGND COUT
7
2

1
0
GND2 PGND
8
2
Trace on bottom layer

1 2 3 4 5 6 7 8 9
PGOOD
RF

EN

SW
SW
SW
SW
VBST
NC

VOUT Shape
SW Shape LOUT

To VREG Pin

Cap. Res.
Trace on bottom layer
Trace of top layer
RCC On Bottom layer
Trace of bottom layer

Trace on inner layer

Figure 56. Layout Recommendation

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 31

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

10.3 Thermal Performance

TA = 23°C, fSW = 500 kHz, VIN = 12 V, VOUT = 1.24 V, IOUT = 8 A, RBOOT= 0 Ω, SNB = 3 Ω + 470 pF
Inductor: LOUT = 1 µH, PIMB103T-1R0MS-63, 10 mm × 11.2 mm × 3 mm, 5.3 mΩ

℃ (TPS53513), SP2: 35.1℃

Figure 57. SP1: 43℃ ℃ (Inductor)

32 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 TPS53513
www.ti.com SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS53513 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation see the following:
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.5 Trademarks
D-CAP3, SWIFT, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback 33

Product Folder Links: TPS53513
TPS53513
SLUSBP9C – SEPTEMBER 2013 – REVISED JUNE 2018 www.ti.com

11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

34 Submit Documentation Feedback Copyright © 2013–2018, Texas Instruments Incorporated

Product Folder Links: TPS53513

 PACKAGE OPTION ADDENDUM

www.ti.com 9-Jul-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DPA02259RVER ACTIVE VQFN-CLIP RVE 28 3000 RoHS-Exempt NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS53513
& Green
TPS53513RVER ACTIVE VQFN-CLIP RVE 28 3000 RoHS-Exempt NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 TPS53513
& Green
TPS53513RVET ACTIVE VQFN-CLIP RVE 28 250 RoHS-Exempt NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 TPS53513
& Green

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Jul-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS53513RVER VQFN- RVE 28 3000 330.0 12.4 3.8 4.8 1.18 8.0 12.0 Q1
CLIP
TPS53513RVER VQFN- RVE 28 3000 330.0 12.4 3.71 4.71 1.1 8.0 12.0 Q1
CLIP
TPS53513RVET VQFN- RVE 28 250 180.0 12.4 3.8 4.8 1.18 8.0 12.0 Q1
CLIP
TPS53513RVET VQFN- RVE 28 250 180.0 12.4 3.71 4.71 1.1 8.0 12.0 Q1
CLIP

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jan-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53513RVER VQFN-CLIP RVE 28 3000 367.0 367.0 38.0
TPS53513RVER VQFN-CLIP RVE 28 3000 367.0 367.0 35.0
TPS53513RVET VQFN-CLIP RVE 28 250 213.0 191.0 35.0
TPS53513RVET VQFN-CLIP RVE 28 250 210.0 185.0 35.0

Pack Materials-Page 2
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated