Chapter 1

DIGITAL HARDWARE DESIGN

USING FPGA

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 I. INTRODUCTION TO FPGA
1.1. FPGA (Field Programmable Gate Array)
- FPGA is an integrated circuit designed to be
configured by a customer or a designer after
manufacturing.
- FPGA includes 4 components:
• an array of programmable logic blocks
• a hierarchy of reconfigurable
interconnects
• IO Pads
• Hard blocks: DSP slice, RAM, ROM,
soft cores.
- Configure FPGA using HDL (hardware
description language), or schematic
(circuit diagram).

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 I. INTRODUCTION TO FPGA
1.1. FPGA (Field Programmable Gate Array)
- Logic element
LE in Cyclone IV
(Altera)
- LUT : look
up table

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 I. INTRODUCTION TO FPGA
1.1. FPGA (Field Programmable Gate Array)
- LAB structure:
(logic array block)
• Has 16 LEs
• Control signals
• Local inteconnect

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 I. INTRODUCTION TO FPGA
1.1. FPGA (Field Programmable Gate Array)
- Cyclone IV family of Altera

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 I. INTRODUCTION TO FPGA
1.2. CPLD (Complex Programmable Logic Device)
- Simpler structure than FPGA and fewer logic blocks than FPGA
- Non-volatile storage is EEPROM
- Fast propagation delay

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 I. INTRODUCTION TO FPGA
1.2. CPLD (Complex Programmable Logic Device)

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 I. INTRODUCTION TO FPGA
1.2. CPLD (Complex Programmable Logic Device)
The MAX II CPLD has the following features (MAX II Device Handbook):
• Low-cost, low-power CPLD
• Instant-on, non-volatile architecture
• Standby current as low as 25 μA
• Provides fast propagation delay and clock-to-output times
• Provides four global clocks with two clocks available per logic array block
(LAB)
• UFM block up to 8 Kbits for non-volatile storage
• MultiVolt core enabling external supply voltages to the device of either 3.3V,
2.5V or 1.8V
• MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels

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 I. INTRODUCTION TO FPGA
1.2. CPLD (Complex Programmable Logic Device)
- MAX II family of Altera

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 I. INTRODUCTION TO FPGA
1.3. FPGA manufacturers

ALTERA - FPGA XILINX - FPGA

• SoC FPGA (FPGA + Cortex • Zynq-7000 (FPGA + Cortex
A9 Dual-Core 800Mhz) A9 Dual-Core 800Mhz)
• Stratix V, Stratix IV • 7 series FPGAs
• Arria V, Arria II • Virtex-6, Virtex-5, Virtex-4
• Cyclone V, Cyclone IV • Spartan-6, Spartan-3A, 3E

CPLD CPLD
• MAX V, MAX II - CoolRunner II

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)

WR RD

CS CS
Hi-Z Hi-Z
D[7:0] D[7:0]
Hi-Z Hi-Z
A[7:0] A[7:0]

2 19
2 19 3 D1 Q1 18 2 18 2 18
3 D0 Q0 18 4 D2 Q2 17 4 A1 Y1 16 3 A0 B0 17
4 D1 Q1 17 D3 Q3 6 A2 Y2 14 4 A1 B1 16
5 16
5 D2 Q2 16 D4 Q4 8 A3 Y3 12 5 A2 B2 15
6 15
6 D3 Q3 15 D5 Q5 11 A4 Y4 9 6 A3 B3 14
7 14
7 D4 Q4 14 D6 Q6 13 A5 Y5 7 7 A4 B4 13
8 13
8 D5 Q5 13 D7 Q7 15 A6 Y6 5 8 A5 B5 12
9 12
9 D6 Q6 12 D8 Q8 17 A7 Y7 3 9 A6 B6 11
D7 Q7 A8 Y8 A7 B7
11
11 CLK 1 1
1 LE 19 1OE 19 DIR
1
OE OE 2OE G

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)

WR RD

CS CS
Hi-Z Hi-Z
D[7:0] D[7:0]
Hi-Z Hi-Z
A[7:0] A[7:0]
74574
74573 2 19 74244 74245
2 19 3 D1 Q1 18 2 18 2 18
3 D0 Q0 18 4 D2 Q2 17 4 A1 Y1 16 3 A0 B0 17
4 D1 Q1 17 D3 Q3 6 A2 Y2 14 4 A1 B1 16
5 16
5 D2 Q2 16 D4 Q4 8 A3 Y3 12 5 A2 B2 15
6 15
6 D3 Q3 15 D5 Q5 11 A4 Y4 9 6 A3 B3 14
7 14
7 D4 Q4 14 D6 Q6 13 A5 Y5 7 7 A4 B4 13
8 13
8 D5 Q5 13 D7 Q7 15 A6 Y6 5 8 A5 B5 12
9 12
9 D6 Q6 12 D8 Q8 17 A7 Y7 3 9 A6 B6 11
D7 Q7 A8 Y8 A7 B7
11
11 CLK 1 1
1 LE 19 1OE 19 DIR
1
OE OE 2OE G

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
- Schematic for data read (MCU side) : CS, RD are used to enable OE pin

74LS244 74LS245

2 18 2 18
4 A1 Y1 16 3 A0 B0 17
6 A2 Y2 14 4 A1 B1 16
8 A3 Y3 12 5 A2 B2 15
11 A4 Y4 9 6 A3 B3 14
13 A5 Y5 7 7 A4 B4 13
15 A6 Y6 5 8 A5 B5 12
17 A7 Y7 3 9 A6 B6 11
RD 2 A8 Y8 A7 B7
1 1 RD 2 1
CS 3 19 1OE 1 19 DIR
2OE CS 3 G

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
- Schematic for data write (MCU side) : CS, WR are used to enable LATCH pin

74LS574
74LS573
2 19
2 19 3 D1 Q1 18
3 D0 Q0 18 4 D2 Q2 17
4 D1 Q1 17 5 D3 Q3 16
5 D2 Q2 16 6 D4 Q4 15
6 D3 Q3 15 7 D5 Q5 14
7 D4 Q4 14 8 D6 Q6 13
8 D5 Q5 13 9 D7 Q7 12
9 D6 Q6 12 WR 2 D8 Q8
WR 2 D7 Q7 1 11
1 11 CS 3 CLK
CS 3 1 LE 1
OE OE

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
* Example 1: Address decoding using IC 74138
- MCU has 8-bit address bus A7-A0,
U1
8-bit data bus D7-D0. Let do address
decoding for peripherals: 1 15
2 A Y0 14
• ADC: 4 channels, 8-bit data 3 B Y1 13
C Y2 12
• DAC: 2 channels, 8-bit data 6 Y3 11
• PWM: 6 channels, 8-bit data 4 G1 Y4 10
5 G2A Y5 9
• Encoder: 6 channels, 8-bit data G2B Y6 7
Y7
• DI: 2 channels, 8-bit data
74LS138

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
* Procedure:
- Step 1: Calculate the maximum number of channels in a module to
determine the number of addresses to decode channels.
6 channels -> need 3 address lines A[2:0]
- Step 2: Calculate the number of modules to determine the number of
addresses to decode modules. (It is not necessary to assign consecutive
addresses to modules).
5 modules -> need 3 address lines A[5:3], or A[6:4], or A[7:5]
- Step 3: Draw a module connection diagram: connect chip select, address bus,
and data bus to the modules, determine the address range of each module.
- Step 4: Draw the channel connection diagram: connect chip select, address
bus, and data bus to the channels in a module. Specify the address of each
channel in a module.

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
- Schematic for module connection

CS_ADC: 0x00 – 0x03

CS_DAC: 0x10 – 0x11
CS_PWM: 0x20 – 0x25
CS_ENC: 0x30 – 0x35
CS_DI: 0x40 – 0x41

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
- Schematic for channel address decoding in the DI module

CS_DI1: 0x40
CS_DI2: 0x41

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 II. ADDRESS DECODING
2.1. WR & RD signals are separate (Intel’s bus architecture)
* Example 2:
- MCU has 8-bit address bus A7-A0, 8-bit data bus D7-D0. Let do address
decoding for peripherals :
• ADC: 16 channels, 8-bit data U1

• DAC: 2 channels, 8-bit data 1 15

2 A Y0 14
• PWM: 4 channels, 8-bit data 3 B Y1 13
C Y2 12
• Encoder: 4 channels, 8-bit data Y3 11
6
• DI: 4 channels, 8-bit data 4 G1 Y4 10
5 G2A Y5 9
• DO: 2 channels, 8-bit data G2B Y6 7
• CAP: 6 channels, 8-bit data Y7

• SPI: 1 channel, 8-bit data 74LS138

• I2C: 1 channel, 8-bit data

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 II. ADDRESS DECODING
2.2. WR & RD signals are combined in one pin (Motorola’s architecture)

STROBE STROBE

RD/WR RD/WR
Hi-Z Hi-Z
D[7:0] D[7:0]
Hi-Z Hi-Z
A[7:0] A[7:0]

Timing diagram for write cycle Timing diagram for read cycle

- How to convert Motorola’s bus architecture to Intel’s bus architecture?

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 II. ADDRESS DECODING
2.2. WR & RD signals are combined in one pin (Motorola’s architecture)

STROBE
D[7..0] D[7..0]
RD/WR
Hi-Z A[7..0] A[7..0]
D[7:0]
Hi-Z
A[7:0]
CONVERTER
STROBE RD

STROBE WR/RD WR

RD/WR CS
Hi-Z
D[7:0]
Hi-Z
A[7:0]

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 II. ADDRESS DECODING
2.2. WR & RD signals are combined in one pin (Motorola’s architecture)
- Printer interface with EPP (Enhanced Parallel Port)

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 II. ADDRESS DECODING
2.3. Different data widths U14
31 39
- MCU has 8-bit address bus A7-A0, EA/VP P0.0 38
P0.1
8-bit data bus D7-D0. Let do address 19
X1 P0.2
37
36
P0.3
decoding for peripherals : 18 P0.4
35
34
X2 P0.5
• ADC: 4 channels, 12-bit data P0.6
33
32
9 P0.7
• DAC: 4 channels, 12-bit data RESET
P2.0
21
22
• PWM: 6 channels, 10-bit data 12
13 INT0
P2.1
P2.2
23
24
INT1 P2.3
• Encoder: 6 channels, 16-bit data 14
15 T0 P2.4
25
26
T1 P2.5 27
• DI: 2 channels, 8-bit data 1
P1.0
P2.6
P2.7
28
2
3 P1.1 17
- Address decoding for 4 channels ADC, 4 P1.2
P1.3
RD
WR
16
5 29
P1.4 PSEN
DAC; then read and write data: 6
P1.5 ALE/P
30
7 11
8 P1.6 TXD 10
int read_adc (int channel) P1.7 RXD
AT9C52
void write_dac (int channel, int value)

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 III. QUARTUS/ BLOCK DIAGRAM
3.1. Implementation procedure

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 III. QUARTUS/ BLOCK DIAGRAM
3.1. Implementation procedure
- Create a new project: File -> New project wizard.
- Create a new design using Block Diagram:
File -> New -> Block Diagram / Schematic File
- Compile a project: Processing -> Start Compilation
- Pin assignment for Input, Output, Bidir signals:
Assignments -> Assignment Editor
- Simulate a project: File -> New -> Vector Waveform File
- Program and config FPGA: Tools -> Programmer
- Validate the design

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 III. QUARTUS/ BLOCK DIAGRAM
3.2. Re-use a module in other design files
- Create a new design: File -> New -> Block Diagram / Schematic File
- Create symbol file for a design file (module): File -> Create/Update ->
Create Symbol File for Current File
- Use the symbol file in other design files: Double Click -> Libraries

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