LE TE

CA1524, CA2524
BSO
CA2
524
IS A
PRO
NO
DUC
T CA3524
Regulating Pulse Width Modulator
October 2000

Features Description
• Complete PWM Power Control Circuitry The CA1524 and CA3524 are silicon monolithic integrated
circuits designed to provide all the control circuitry for use in
• Separate Outputs for Single-Ended or Push-Pull
a broad range of switching regulator circuits.
Operation
The CA1524 and CA3524 have all the features of the indus-
• Line and Load Regulation . . . . . . . . . . . . . . . 0.2% (Typ)
try types SG1524, SG2524, and SG3524, respectively. A
• Internal Reference Supply with 1% (Max) Oscillator block diagram of the CA1524 series is shown in Figure 1.
and Reference Voltage Variation Over Full The circuit includes a zener voltage reference, transconduc-
Temperature Range tance error amplifier, precision R-C oscillator, pulse-width
modulator, pulse-steering flip-flop, dual alternating output
• Standby Current of Less Than 10mA switches, and current-limiting and shutdown circuitry. This
• Frequency of Operation Beyond 100kHz device can be used for switching regulators of either polarity,
transformer-coupled dc-dc converter, transformerless volt-
• Variable-Output Dead Time of 0.5µs to 5µs age doublers, dc-ac power inverters, highly efficient variable
• Low VCE(sat) Over the Temperature Range power supplies, and polarity converter, as well as other
power-control applications.
Applications
Ordering Information
• Positive and Negative Regulated Supplies
PART TEMPERATURE
• Dual-Output Regulators NUMBER RANGE PACKAGE
• Flyback Converters CA1524E -55oC to +125oC 16 Lead Plastic DIP
• DC-DC Transformer-Coupled Regulating Converters CA1524F -55oC to +125oC 16 Lead CerDIP

• Single-Ended DC-DC Converters CA2524E 0oC to +70oC 16 Lead Plastic DIP

• Variable Power Supplies CA2524F 0oC to +70oC 16 Lead CerDIP

CA3524E 0oC to +70oC 16 Lead Plastic DIP

CA3524F 0oC to +70oC 16 Lead CerDIP

Pinout
CA1524, CA3524
(PDIP, CERDIP)
TOP VIEW

INV. INPUT 1 16 VREF

NON-
2 15 V+
INV. INPUT
OSC OUT 3 14 EMITTER B
(+) C.L.
4 13 COLLECTOR B
SENSE
(-) C.L. 5 12 COLLECTOR A
SENSE
RT 6 11 EMITTER A

CT 7 10 SHUTDOWN
COMPENSATION
GND 8 9
AND COMPARATOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 1239.4
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
1
 CA1524, CA2524, CA3524

Functional Block Diagram

REFERENCE
REGULATOR +5V TO ALL
15 INTERNAL CIRCUITS
V+ 5V

+5V CA
12
16
VREF
FLIP SA
FLOP

3 11
OSC OUT EA
+5V
CB
13
6 OSCILLATOR
RT
SB
+5V

7 14
CT COMPARATOR EB
+5V +5V
1 -
+ 4
INV. INPUT ERROR + SENSE
C.L.
AMP -
2 + 5
NON-INV. - SENSE
INPUT

1kΩ
10 9
SHUTDOWN COMPENSATION AND COMPARATOR

10kΩ

8
GND

Test Circuit
8 - 40V
2kΩ 2kΩ
ls 1W 1W

V+ 12 OUT A

15
13 OUT B
CA1524
3 11

16 14

8 6 7 2 1 9 10 4 5

2kΩ 2kΩ
10
kΩ

0.1µF RT CT 10kΩ

1kΩ
2kΩ

2
 Specifications CA1524, CA2524, CA3524
Absolute Maximum Ratings Thermal Information
Input Voltage (Between VIN and GND Terminals). . . . . . . . . . . . 40V Thermal Resistance θJA
Operating Voltage Range (VIN to GND) . . . . . . . . . . . . . . . . 8 to 40V Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W
Output Current Each Output: Device Dissipation
(Terminal 11, 12 or 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Up to TA = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Output Current (Reference Regulator) . . . . . . . . . . . . . . . . . . . 50mA Above TA = +25oC . . . . . . . . . . . . . . .Derate Linearly at 10mW/oC
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± in. (1.59mm ±0.79mm)
from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and
f = 20kHz, Unless Otherwise Stated.

CA1524, CA2524 CA3524

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

REFERENCE SECTION

Output Voltage 4.8 5 5.2 4.6 5 5.4 V

Line Regulation V+ = 8 to 40V - 10 20 - 10 30 mV

Load Regulation IL = 0 to 20mA - 20 50 - 20 50 mV

Ripple Rejection f = 120Hz, TA = 25oC - 66 - - 66 - db

Short Circuit Current Limit VREF = 0, TA = 25oC - 100 - - 100 - mA

Temperature Stability Over Operating Temperature - 0.3 1 - 0.3 1 %

Range

Long Term Stability TA = 25oC - 20 - - 20 - mV/khr

OSCILLATOR SECTION

Maximum Frequency CT = 0.001µF, RT = 2KΩ - 300 - - 300 - kHz

Initial Accuracy RT and CT Constant - 5 - - 5 - %

Voltage Stability V+ = 8 to 40V, TA = 25oC - - 1 - - 1 %

Temperature Stability Over Operating Temperature - - 2 - - 2 %

Range

Output Amplitude Terminal 3, TA = 25oC - 3.5 - - 3.5 - V

Output Pulse Width (Pin 3) CT = 0.01µF, TA = 25oC - 0.5 - - 0.5 - µs

Ramp Voltage Low (Note 1) Pin 7 - 0.6 - - 0.6 - V

Ramp Voltage High (Note 1) Pin 7 - 3.5 - - 3.5 - V

Capacitor Charging Current Range Pin 7 (5-2 VBE)/RT 0.03 - 2 0.03 - 2 mA

Timing Resistance Range Pin 6 1.8 - 120 1.8 - 120 kΩ

Charging Capacitor Range Pin 7 0.001 - 0.1 0.001 - 0.1 µF

Dead Time Expansion Capacitor on Pin 3 100 - 1000 100 - 1000 pF

Pin 3 (when a small osc. cap is used)

ERROR AMPLIFIER SECTION

Input Offset Voltage VCM = 2.5V - 0.5 5 - 2 10 mV

Input Bias Current VCM = 2.5V - 1 10 - 1 10 µA

Open Loop Voltage Gain 72 80 - 60 80 - dB

Common Mode Voltage TA = 25oC 1.8 - 3.4 1.8 - 3.4 V

Common Mode Rejection Ratio TA = 25oC - 70 - - 70 - dB

Small Signal Bandwidth AV = 0dB, TA = 25oC - 3 - - 3 - MHz

3
 Specifications CA1524, CA2524, CA3524

Electrical Specifications TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and
f = 20kHz, Unless Otherwise Stated. (Continued)

CA1524, CA2524 CA3524

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Output Voltage TA = 25oC 0.5 - 3.8 0.5 - 3.8 V

Amplifier Pole - 250 - - 250 - Hz

Pin 9 Shutdown Current External Sink - 200 - - 200 - µA

COMPARATOR SECTION

Duty Cycle % Each Output On 0 - 45 0 - 45 %

Input Threshold Zero Duty Cycle - 1 - - 1 - V

Input Threshold Max. Duty Cycle - 3.5 - - 3.5 - V

Input Bias Current - 1 - - 1 - µA

CURRENT LIMITING SECTION

Sense Voltage for 25% Output Duty Terminal 9 = 2V with Error 190 200 210 180 200 220 mV
Cycle Amplifier Set for Max Out,
TA = 25oC

Sense Voltage T.C. - 0.2 - - 0.2 - mV/oC

Common Mode Voltage -1 - +1 -1 - +1 V

Rolloff Pole of R51 C3 + Q64 - 300 - - 300 - Hz

OUTPUT SECTION (EACH OUTUT)

Collector-Emitter Voltage 40 - - 40 - - V

Collector Leakage Current VCE = 40V - 0.1 50 - 0.1 50 µA

Saturation Voltage V+ = 40V, IC = 50mA - 0.8 2 - 0.8 2 V

Emitter Output Voltage V+ = 20V 17 18 - 17 18 - V

Rise Time RC = 2KΩ, TA = 25oC - 0.2 - - 0.2 - µs

Fall Time RC = 2KΩ, TA = 25oC - 0.1 - - 0.1 - µs

Total Standby Current: (Note 2) IS V+ = 40V - 4 10 - 4 10 mA

NOTES: High
1. Ramp voltage at Pin 7 Low where t = OSC period in microseconds
t t ≅ RTCT with CT in microfarads and RT in ohms.
Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency
when each output is connected in parallel.
2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.

4
 CA1524, CA2524, CA3524

Schematic Diagram
15 VIN

A
R1 R5 R7
500 1K 1K
B
Q1
Q2 Q7 Q13

Q17
Q6 Q18
R12
10K
Q3 Q4 Q9 C1 Q16
20pF R11
500 R13
R2 RD 6Ω
2.7K R16
16.2K
Q10 16
RC 10K 1.9K
10K Q11 VREF
R14 +5V
R3 450
6.3K C4 R17 R18
D2 18.7 18.7
D1
Q19 K K

PULSE
RA STEERING Q21 Q23
5.3K FLIP-FLOP
R8 C
8.4K
QA R19 R18
18.7 18.7
K K D
RB C2 E
4.8K Q5 Q12 20pF
Q14 Q15 Q20
N+ P Q22 Q24
R4 R6 R9 R10 R15
500 500 500 1K 25K
8 F
GND G
OSC SECTION H
I
ERROR
AMP
Q42 Q43 Q47 Q48
Q59 Q60
R43
7.4K

6 Q44 Q61
Q55 INV. NON-INV.
RT IN INPUT
Q49 Q50 1 Q56 Q57 2 J
R44
7 1.8K
CT Q51 Q58 Q62
Q46 OSC.
R41 OUT
Q45
24K Q52 3
R45 R47 R48
R39 R40 R42 25K 1K 2K
1K 560 19.8K Q53 Q54
R46
3.3K K
L

5
 CA1524, CA2524, CA3524

Schematic Diagram (Continued)

A
OUTPUT B
OUTPUT A
B Q33

COLL. A 12 R33 R36 13 COLL. B

200 Q35 Q40 200
Q34 Q41

R32 R37
1K CA CB 1K
1pF 1pF
Q36 Q39
R34 R35
500 D3 D4 500
R31 R38
RE RF
4.7Ω 4.7Ω
500 500

EMIT A 11 14 EMIT B

Q37 Q38

C
R21 NOR NOR R30
43.3K 43.3K

D
E R25 R26
R23 5K 5K R28
R24 Q29
8.7K 5K 8.7K
Q26 Q30
R27
Q27 5K Q31
F
G
H
I
R52 R54 COMPARATOR
1.96K 1.96K

COMP Q65 Q67

10 9

Q68 Q70
J Q68 Q71
C3
45pF
R53
R49 1.8K
1K
Q64
R51
Q63 10K
Q66

R50 CURRENT Q72 Q73

10K LIMIT
SECTION
K
L

5 4
(-) C.L. (+) C.L.
SENSE SENSE

6
 CA1524, CA2524, CA3524

Circuit Description Osclllator Section

Voltage Reference Section Transistors Q42, Q43 and Q44, in conjunction with an
external resistor RT, establishes a constant charging current
The CAl524 series contains an internal series voltage regu- into an external capacitor CT to provide a linear ramp voltage
lator employing a zener reference to provide a nominal 5-volt at terminal 7. The ramp voltage has a value that ranges from
output, which is used to bias all internal timing and control 0.6V to 3.5V and is used as the reference for the comparator
circuitry. The output of this regulator is available at terminal in the device. The charging current is equal to (5-2VBE)/RT or
l6 and is capable of supplying up to 50mA output current. approximately 3.6/RT and should be kept within the range of
Figure 1 shows the temperature variation of the reference 30pA to 2mA by varying RT. The discharge time of CT deter-
voltage with supply voltages of 8V to 40V and load currents mines the pulse width of the oscillator output pulse at termi-
up to 20mA. Load regulation and line regulation curves are nal 3. This pulse has a practical range of 0.5µs to 5µs for a
shown in Figures 2 and 3, respectively. capacitor range of 0.001 to 0.1µF. The pulse has two internal
uses: as a dead-time control of blanking pulse to the output
stages to assure that both outputs cannot be on simulta-
5.02
V+ = 40V, IL = 0mA neously and as a trigger pulse to the internal flip-flop which
REFERENCE VOLTAGE (V)

V+ = 20V, IL = 0mA controls the switching of the output between the two output
5.00 V+ = 40V, IL = 20mA channels. The output dead-time relationship is shown in Fig-
V+ = 8V, IL = 0mA ure 4. Pulse widths less than 0.5µs may allow false trigger-
V+ = 20V, IL = 20mA
ing of one output by removing the blanking pulse prior to a
4.98 V+ = 8V, IL = 20mA
stable state in the flip-flop.

4.96 100
TA = +25oC
V+ = 8V - 40V

OUTPUT DEAD TIME (µs)

-60 -40 -20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE (oC) 10
FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
OF AMBIENT TEMPERATURE

5.1 1.0
V+ = 40V
4.9
REFERENCE VOLTAGE (V)

4.7
0.1
4.5
V+ = 20V 0.0001 0.001 0.01 0.1 1.0
4.3 TIMING CAPACITOR, CT (µF)
TA = +25oC
4.1
V+ = 20V FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A
3.9 FUNCTION OF TIMING CAPACITOR VALUE
V+ = 8V
3.7 If a small value of CT must be used, the pulse width can be
3.5 further expanded by the addition of a shunt capacitor in the
0 8 16 24 32 40 48 56 64 72 80 order of 100pF but no greater than 1000pF, from terminal 3
REFERENCE OUTPUT CURRENT (mA) to ground. When the oscillator output pulse is used as a sync
input to an oscilloscope, the cable and input capacitances
FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION
may increase the pulse width slightly. A 2-KΩ resistor at
OF REFERENCE OUTPUT CURRENT
terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulse width is determined by the
8
maximum duty cycle acceptable.
7 TA = +25oC
REFERENCE VOLTAGE (V)

The oscillator period is determined by RT and CT, with an

6
approximate value of t = RTCT, where RT is in ohms, CT is in
5 µF, and t is in µs. Excess lead lengths, which produce stray
4
capacitances, should be avoided in connecting RT and CT to
their respective terminals. Figure 5 provides curves for
3 selecting these values for a wide range of oscillator periods.
2 For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
1
the output stage frequency the same as the oscillator
0 frequency. Since the outputs are separate, push-pull and
0 10 20 30 40
flyback applications are possible. The flip-flop divides the
SUPPLY VOLTAGE, V+ (V)
frequency such that the duty cycle of each output is 0-45%
FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION and the overall frequency is half that of the oscillator. Curves
OF SUPPLY VOLTAGE

7
 CA1524, CA2524, CA3524

of the output duty cycle as a function of the voltage at The output amplifier terminal is also used to compensate the
terminal 9 are shown in Figure 7. To synchronize two or system for ac stability. The frequency response and phase
more CAl524’s, one must be designated as master, with RT shift curves are shown in Figure 7. The uncompensated
CT set for the correct period. Each of the remaining units amplifier has a single pole at approximately 250Hz and a
(slaves) must have a CT of 1/2 the value used in the master unity gain cross-over at 3MHz.
and approximately a 1010 longer RTCT period than the mas- Since most output filter designs introduce one or more
ter. Connecting terminal 3 together on all units assures that additional poles at a lower frequency, the best network to
the master output pulse, which occurs first and has a wider stabilize the system is a series RC combination at terminal9
pulse width, will reset the slave units. to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good start-
TA = +25oC
105
ing point to determine the external poles is a 1000-pF
V+ = 8V - 40V
TIMING RESISTANCE, RT (Ω)

capacitor and a variable series 50-KΩ potentiometer from

CT = 0.001µF terminal 9 to ground. The compensation point is also a
CT = 0.002µF convenient place to insert any programming signal to
CT = 0.005µF override the error amplifier. internal shutdown and current
104
limiting are also connected at terminal 9. Any external circuit
CT = 0.02µF that can sink 200µA can pull this point to ground and shut off
CT = 0.05µF both output drivers.
CT = 0.1µF While feedback is normally applied around the entire regula-
CT = 0.01µF
tor, the error amplifier can be used with conventional
103 operational amplifier feedback and will be stable in either the
1 10 102 103 104 inverting or non-inverting mode. Input common-mode limits
OSCILLATOR PERIOD, t (µs) must be observed; if not, output signal inversion may result.
FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION The internal 5V reference can be used for conventional regu-
OF RT AND CT lator applications if divided as shown in Figure 8. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
Error AmplIfIer Section
cycle application results.
The error amplifier consists of a differential pair (Q56,Q57)
with an active load (Q61 and Q62) forming a differential
TA = +25oC
transconductance amplifier. Since Q61 is driven by a
V+ = 20V
constant current source, Q62, the output impedance ROUT,
OUTPUT DUTY CYCLE (%)

terminal 9, is very high (≅ 5MΩ). 48

CT = 2700pF
40
The gain is: RT = 6.19k
fOSC = 60kHz
AV = gmR = 8 lC R/2KT = 104, 32

ROUT RL 24
CT =1000pF
where R = ROUT + , RL = ∞, AV ∝ 104 16 RT = 5k
fOSC = 20kHz
RL 8

Since ROUT is extremely high, the gain can be easily 0

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
reduced from a nominal 104 (80dB) by the addition of an
COMPARATOR VOLTAGE (V)
external shunt resistor from terminal 9 to ground as shown in
Figure 6. FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF
COMPARATOR VOLTAGE (AT TERMINAL 9).
80
RL = ∞
70 OPEN LOOP GAIN 1.1
OUTPUT SATURATION VOLTAGE (V)

RL = 3MΩ
PHASE ANGLE (DEGREES)

60 RL = 1MΩ
VOLTAGE GAIN (dB)

1.0
RL = 300kΩ
50

40 RL =100kΩ 0.9
0o

0.8

90o
OPEN LOOP PHASE
50 0.7
10 102 103 104 105 -75 -50 -25 0 25 50 75 100 125 150 175

FREQUENCY (Hz) AMBIENT TEMPERATURE (oC)

FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A
CHARACTERISTICS. FUNCTION OF AMBIENT TEMPERATURE.

8
 CA1524, CA2524, CA3524

Output Section The internal 5V reference can be used for conventional regu-
The CA1524 series outputs are two identical n-p-n lator applications if divided as shown in Figure 11. If the error
transistors with both collectors and emitters uncommitted. amplifier is connected as a unity gain amplifier, a fixed duty
Each output transistor has antisaturation circuitry that cycle application results.
enables a fast transient response for the wide range of
oscillator frequencies. Current limiting of the output section VREF R2 POSITIVE
is set at 100mA for each output and 100mA total if both OUTPUT
outputs are paralleled. Having both emitters and collectors 5K VOLTAGES

available provides the versatility to drive either n-p-n or p-n-p

2
external transistors. Curves of the output saturation voltage +
as a function of temperature and output current are shown in 1 -
Figures 8 and 9, respectively. There are a number of output 5K
configurations possible in the application of the CA1524 to R1
2.5V (R1 + R2)
voltage regulator circuits which fall into three basic GND
VO
R1
classifications: VREF
R1R2
1. Capacitor-diode coupled voltage multipliers = 2.5KW
R1 + R2
2. Inductor-capacitor single-ended circuits R1
5K
3. Transformer-coupled circuits 2 +
-
1
2.0
OUTPUT SATURATION VOLTAGE (V)

TA = +25oC 5K NEGATIVE
V+ = 8V to 40V OUTPUT
1.5 GND R2 VOLTAGES

FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS

1.0

0.5
16 VREF

0 VT CA1524
0 20 40 60 80 100 15 REFERENCE
OUTPUT CURRENT, IL (mA) SECTION

FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A

FUNCTION OF OUTPUT CURRENT V+ CANNOT 8
EXCEED 6V
Device Application Suggestions
For higher currents, the circuit of Figure 10 may be used with NOTE: V+ Should Be in the 5V Range
an external p-n-p transistor and bias resistor. The internal And Must Not Exceed 6V
regulator may be bypassed for operation from a fixed 5V FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE
supply by connecting both terminals 15 and 16 to the input REFERENCE REGULATION
voltage, which must not exceed 6V.
To provide an expansion of the dead time without loading the
oscillator, the circuit of Figure 13 may be used.
Q1

IL TO IA
DEPENDING 16
ON CHOICE
100Ω CA1524 FOR Q1
15 REFERENCE 16
V+ SECTION VREF 5KΩ 9
+
10µF
-
8

GND 8

FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITH-

FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE OUT USING A CAPACITOR ON PIN 3 OR WHEN A
CURRENT CAPABILITY LOW VALUE OSCILLATOR CAPACITOR IS USED

9
 CA1524, CA2524, CA3524

VO = 5V
TABLE 1. INPUT vs. OUTPUT VOLTAGE, AND FEEDBACK
SA//SB RESISTOR VALUES FOR IL = 40mA (FOR CAPACI-
R1 TOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)
VO (V) R2 (KΩ) V+ (Min.) (V)
R2
IMAX = I
RS ( VTH +
VOR2
R1 + R2 ) -0.5
-2.5 10
6 8
9
- RS VTH
ISC = WHERE
5 RS -3 11 10
+ SENSE -4 13 11
VTH = 200mV
4
-5 15 12
-6 17 13
FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED -7 19 14
TO REDUCE POWER DISSIPATION UNDER
-8 21 15
SHORTED OUTPUT CONDITIONS
-9 23 16

D1 -10 25 17
-11 27 18
V+ +VO
SA -12 29 19
SB V+ > VO
-13 31 20
-14 33 21
-15 35 22
D1
-16 37 23
V+ +VO
SA -17 39 24
SB V+ < VO
-18 41 25
-19 43 26

D1
-20 45 27
V+ -VO
SA V+
SB | V+ | > | VO | VO

NOTE: Diode D1 Is Necessary To Prevent Reverse SA-B

Emitter-Base Breakdown of Transistor Switch SA.
FLYBACK
FIGURE 15. CAPACITOR-DIODE COUPLED VOLTAGE
MULTIPLIER OUTPUT STAGES SA VO

V+
SA/SB
SB
V+ +VO
PUSH-PULL
V+ > VO
+ CAN BE SA OR
VO SA CAN DRIVEQ1
SA Q1

V+ CAN BE SB OR
V+ +VO SB CAN DRIVEQ2
SB Q2
SA/SB V+ < VO -
V+

SA/SB
+
V+ -VO VO
-

| V+ | < | VO |

FIGURE 16. SINGLE-ENDED INDUCTOR CIRCUITS WHERE THE FULL BRIDGE

TWO OUTPUTS OF THE 1524 ARE CONNECTED IN
PARALLEL FIGURE 17. TRANSFORMER-COUPLED OUTPUTS

10
 CA1524, CA2524, CA3524

Applications (Note 1) Single-Ended Switching Regulator

The CA1524 in the circuit of Figure 19 has both output
A capacitor-diode output filter is used in Figure 19 to convert
stages connected in parallel to produce an effective 0% -
+15VDC to -5VDC at output currents up to 50mA. Since the
90% duty cycle. Transistor Q1 is pulsed on and off by these
output transistors have built-in current limiting, no additional
output stages. Regulation is achieved from the feedback
current limiting is needed. Table 1 gives the required
provided by R1 and R2 to the error amplifier which adjusts
minimum input voltage and feedback resistor values, R2, for
the on-time of the output transistors according to the load
an output voltage.
current being drawn. Various output voltages can be
Capacitor-Diode Output Circuit obtained by adjusting R1 and R2. The use of an output
A capacitor-diode output filter is used in Figure18 to convert inductor requires an R-C phase compensation network to
+15VDC to -5VDC at output currents up to 50mA. Since the stabilize the system. Current limiting is set at 1.9 amperes by
output transistors have built-in current limiting, no additional the sense resistor R3.
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for NOTE:
an output voltage range of -0.5V to -20V with an output 1. For additional information on the application of this device and a
current of 40mA. further explanation of the circuits below, see Intersil Application
Note AN6915 “Application of the CA1524 series PWM lC”.

V+
+15V
R2
15KΩ 61
5KΩ
1 12
1
IN4001
5KΩ 21 11
1
R1 20µF IN4001
0.1µF
5KΩ -5V
161 13
1
CA3524 20mA
2KΩ
61 14
1

71 41
IN4001
0.01µF
31 15 50µF

10
1 9
1 R1 = 5KΩ

0.01µF R1 ( | VO | + 2.5)
18 R2 =
(VREF - 2.5)

FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT

V+
+28V +5V IA
R1 0.9mH
R2 5KΩ 15
5KΩ 1 2N6388

5KΩ Q1
1 12
1 500µF
21 11
1
5KΩ
0.1µF 2KΩ
16
1 13
1 RURD410
CA3524
3KΩ
61 14
1

71 41
0.02µF
31 15

10
1 9
1
0.001µF
18 50KΩ

V- 0.1Ω

FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT

11
 CA1524, CA2524, CA3524

Flyback Converter Low-Frequency Pulse Generator

Figure 20 shows a flyback converter circuit for generating a Figure 22 shows the CA1524 being used as a low-frequency
dual 15V output at 20mA from a 5V regulated line. pulse generator. Since all components (error amplifier,
Reference voltage is provided by the input and the internal oscillator, oscillator reference regulator, output transistor
reference generator is unused. Current limiting in this circuit drivers) are on the lC, a regulated 5-V (or 2.5-V) pulse of 0%
is accomplished by sensing current in the primary line and - 45% (or 0% - 90%) on time is possible over a frequency
resetting the soft-start circuit. range of 150 to 500Hz. Switch S1 is used to go from a 5-V
output pulse (S1 closed) to a 2.5-V output pulse (S1 open)
Push-Pull Converter
with a duty cycle range of 0% to 45%. The output frequency
The output stages of the CA1524 provide the drive for will be roughly half of the oscillator frequency when the
transistors Q1 and Q2 in the push-pull application of Figure output transistors are not connected in parallel (75Hz to
21. Since the internal flip-flop divides the oscillator frequency 250Hz, respectively). Switch S2 will allow both output stages
by two, the oscillator must be set at twice the output to be paralleled for an effective duty cycle of 0%-90% with
frequency. Current limiting for this circuit is done in the the output frequency range from 150 to 500Hz. The
primary of transformer T1 so that the pulse width will be frequency is adjusted by R1; R2 controls duty cycle.
reduced if transformer saturation should occur.

V+ RURD620
+5V +15V
+
100µF 25K 5K 15
1 300Ω 1MΩ 200Ω 50T
Ω Ω 50µF
20T
1 12
1 50T
5KΩ 0.1µF
21 11
1 50µF
5KΩ -15V
16
1 13
1
CA3524 RURD620
2KΩ
61 14
1 2N6290

71 41 CORE: FEROX CUBE

0.02µF 2213P - A250 - 387
620Ω OR EQUIVALENT
31 15
IN914
10
1 9
1 510Ω
+
2N2102 1Ω
18 0.001µF 4.7µF

FIGURE 20. FLYBACK CONVERTER CIRCUIT

V+
+28V

5K 15
1 1KΩ 1KΩ
Ω 1W 1W RURD620 1mH
2N6292
5KΩ
1 12
1
5KΩ + 5V
21 11
1 20T 1500µF
5KΩ 1KΩ 5T 5A
0.1µF
16
1 13
1
2KΩ 5T
1KΩ 20T
61 14
1
0.01µF
71 41
2N6292 RURD620
31 15

10
1 9
1 +
0.001µF 0.1µF
100µF
18 20KΩ

FIGURE 21. PUSH-PULL TRANSFORMER-COUPLED CONVERTER

12
 CA1524, CA2524, CA3524
+5
VREFERENCE

TO PIN 9 1.1K 1.1K

2K

1/ S2
DUTY CYCLE 1 16 2
R2 ADJUSTMENT TO PIN 12 TO PIN 13
10K 2 15 V+ = 9V OUTPUT 1 OUTPUT 2
3 14 OUTPUT 1A
2K 1/
4 13 1.5K 2S1
CA3524 1/
2S2
5 12
6 11 OUTPUT 2A
R1 1.5K 1/
50K 7 10 2S1
FREQUENCY
ADJUSTMENT 9
0.1µF 8

20K
OUTPUT DUTY
TO PIN 1
SILVER SWITCH PULSES CYCLE
MICA
S1 0V - 5V 0% - 45%

S2 - 0% - 90%

FIGURE 22. LOW-FREQUENCY PULSE GENERATOR

The Variable Switcher

The circuit diagram of the CA1524, used as a variable output varied, the feedback voltage will track that level and cause
voltage power supply is shown in Figure 23. By connecting the output voltage to change according to the change in
the two output transistors in parallel, the duty cycle is reference voltage.
doubled, i.e., 0% - 90%. As the reference voltage level is

D1 D3
2N6385 7V - 30V
(PNP DARLINGTON) 0A - 3A
36 VDC
AC Q1
IN VOUT
L1 C5
R2 20mH 25µF
1.5
D2 D4 R1 10W D5
RURD410 C4
1K 0.1µF NON-POLAR
5100µF C3
100V 1W
0.01µF 10000µF L2
D1-D4 - A15A 100V 50mH
RETURN
BIFILAR C6
WINDING 25µF

NON-POLAR

C7
0.1µF
16 15 14 13 12 11 10 9
R3 R10
10K 16K
R6 CA1524
2K
C11
1 2 3 4 5 6 7 8 0.01µF
R4
5K
R7
10K C10
R9 C9 1100pF
15K 3300 SILVER
R5 1% pF MICA
2K R8 C8 1%
2K 0.1µF

VOLTAGE
CONTROL fOSC = 20KHz

FIGURE 23. THE CA1524 USED AS A 0-5A, 7-30 V LABORATORY SUPPLY

13
 CA1524, CA2524, CA3524

Digital Readout Scale

The CA1524 can be used as the driving source for an object’s weight, a change in capacitance is noted between
electronic scale application. The circuit shown in Figures 24 PL1, S and PL2. This change is reflected as a voltage to the
and 25 uses half (Q2) of the CA1524 output in a low-voltage ac amplifier (CA3160). At the null position the signals from
switching regulator (2.2V) application to drive the LED’s PL1 and PL2 as detected by S are equal in amplitude, but
displaying the weight. The remaining output stage (Q1) is opposite in phase. As S is driven by the scale mechanism
used as a driver for the sampling plates PL1 and PL2. Since down toward PL2, the signal at S becomes greater. The
the CA1524 contains a 5V internal regulator and a wide CA3160 ac amplifier provides a buffer for the small signal
operating range of 8V to 40V, a single 9V battery can power change noted at S. The output of the CA3160 is converted to
the total system. The two plates, PL1 and PL2, are driven a dc voltage by a peak-to-peak detector. A peak-to-peak
with opposite phase signals (frequency held constant but detector is needed, since the duty cycle of the sampled
duty cycle may change) from the pulse-width modulator lC waveform is subject to change. The detector output is filtered
(CA1524). The sensor, S, is located between the two plates. further and displayed via the CA3161E and CA3162E digital
Plates PL1, S and PL2 form an effective capacitance bridge- readout system, indicating the weight on the scale.
type divider network. As plate S is moved according to the

PL1 DC
VOLTAGE
OSCILLATOR ≈ 20KHz AC PEAK TO PEAK LOW PASS
S AMP DETECTOR FILTER
(PART OF CA1524)

PL2 CA3130

COUPLED TO
MECHANICAL
SCALE MECHANISM DISPLAY DRIVE
(PART OF CA1524)

FULL SCALE

NO WEIGHT
DIGITAL METER
AND DISPLAY

FIGURE 24. BASIC DIGITAL READOUT SCALE

2.5V
+5V

0.27 0.1
50K µF µF
ZERO
ADJUSTMENT POWER 2N2907
OR EQUIVALENT
8 9 12 14 16
MSD NSD LSD COMMON-
ANODE LED
A DISPLAYS
B (NOTE 1)
C 5

4 13
CA3162E CA3161E 12
DIGIT
DRIVERS 11
11 16 6 10
HIGH
15 2 9
INPUTS:
1 1 15
LOW
10 2 7 14

13 7 8 3
BCD NOTE:
OUTPUTS
GAIN 10KΩ 1. FAIRCHILD FND507 OR EQUIVALENT
ADJUSTMENT

FIGURE 25. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE (CONT’D)

14
 CA1524, CA2524, CA3524
9V
10K
200pF

100µF
PL1
9V 1
8
7
TO SCALE S 3 + 0.1µF 910K 910K
MECHANISM
100 CA3160 6
22MΩ
PL2 MΩ -
39K 2 68K 6.2K 0.47
4 2µF 2µF
µF
430K 22MΩ 10K 10µF
30K

300K A
2N4037 2.5V
9V B
125µH
C
470µF
200Ω
4.7K
5V

16 15 14 13 12 11 10 9

CA1524
4.7K

1 2 3 4 5 6 7 8 0.01µF

24K
6.2K
4.7K
4700pF
4.7K

FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE

DIMENSIONS AND PAD LAYOUT FOR CA3524RH CHIP

NOTE: Dimensions in parentheses are in millimeters and are de- the wafer. When the wafer is cut into chips, the cleavage angles are
rived from the basic inch dimensions as indicated. Grid graduations 57o instead of 90o with respect to the face of the chip. Therefore, the
are in mils (10-3 inch). The layout represents a chip when it is part of isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

15
 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

File Number
16