EE3002/E314

Microprocessors

Advanced Microprocessors
386, 486, Pentium, Pentium Pro,
Pentium II, III, IV

386 Architecture
ƒ Full 32-bit microprocessor: 32-bit ALU, 32-bit registers, 32-bit
address bus, 32-bit data bus.
ƒ Supports up to 232 = 4GB of byte-addressable memory.
ƒ 32-bit offset (EIP, ESI etc): segment size up to 232 = 4GB.
ƒ Three modes of operations:
∗ Real-mode: backward compatible with 8086, uses 8086
address translation formula.
∗ Protected-mode: compatible and extends from 286
protected mode to support multitasking.
∗ Virtual 8086 mode: for running multiple 8086 machine, or
multiple DOSes in the same processor.

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 386 Registers
31 16 15 0
EAX AH AL Accumulator Segment Registers
AX 15 0
BH BL
EBX B X Base CS Code
CH CL
ECX CX Count DS Data
DH DL
EDX DX Data Port ES Extra (Data)
EBP EP Base Pointer SS Stack
ESP SP Stack Pointer FS (data)
ESI SI Source Index GS (data)
EDI DI Destination Index
15 0
EIP IP Instruction Pointer
LDTR
EFlags Flags Flags
GDTR
* shaded for 386 and above Base31-
31-0 Limit15-
15-0
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386 Protected-mode Descriptor

ƒ 286 protected-mode descriptor:
+7 Reserved (0000 for 386 compatibility) +6
+5 Access-Right BASE23-
23-16
+4

+3 BASE15-
15-0 +2
+1 LIMIT15-
15-0
+0

ƒ 386 descriptor: downward compatible with 286

+7 BASE31-
31-24 G D 0 AV LIMIT19-16 +6
+5 Access-Right BASE23-
23-16
+4

+3 BASE15-
15-0 +2
+1 LIMIT15-
15-0
+0

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 Granularity & Segment Limit
ƒ 386 has 32-bit offset registers (ESI, EIP etc), hence, segment
size can be up to 232 = 4GB.
ƒ However, only 20 bits are available in the 386 descriptor to
specify segment’s LIMIT.
ƒ A G (Granularity) bit is used to allow 32-bit segment:
∗ When G=0 (byte granularity), the 20-bit LIMIT is the actual
segment limit. This permits segment size of 1 byte to 220
= 1MB in step of 1 byte.
∗ When G=1 (4KB granularity), the actual segment limit is
20-bit Limit × 4KB (i.e. padded with twelve 1’s or FFFH).
This permits segment size of 4KB to 4GB in step of 4KB.
eg. G=1 and LIMIT=FFFFFH,
⇒ Actual segment LIMIT = FFFFF FFFH.
⇒ size of segment = 4GB, which is the maximum size.
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Example 1: Byte-granularity Segment

+7 3 0 0 F +6
+5 F B 0 0 +4
Descriptor
+3 0 0 0 0 +2 300FFFFF
+1 F F F F +0

CS 30000000
Code Segment
Descriptor Table
ƒ Access-right Byte = FBH = 1111 1011B
⇒ code segment, present, privilege-level 3, non-conforming,
readable, has-been accessed.
ƒ BASE = segment beginning address = 30000000H
ƒ G = 0 & LIMIT = FFFFFH (actual segment LIMIT)
⇒ Segment ending address = Base + Limit = 300FFFFFH.
⇒ Size of segment = Limit + 1 = 100000H = 1MB.
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 Example 2: 4KB-granularity Segment
+7 1 0 C 0 +6
+5 9 2 0 0 +4 Descriptor
1FFFFFFF
+3 0 0 0 0 +2
+1 F F F F +0
DS 10000000
Data Segment
Descriptor Table
ƒ Access-right Byte = 92H = 1001 0010B
⇒ data segment, present, privilege level 0, expand-up,
writable, has-not-been accessed.
ƒ BASE = segment beginning address = 10000000H
ƒ G = 1 & LIMIT = 0FFFFH,
⇒ Actual Segment Limit = 0FFFF FFFH
⇒ Segment ending address = Base + Limit = 1FFFFFFFH.
⇒ Size of segment = Limit + 1 = 10000000H = 256MB. 7

Example 3
ƒ Give the content of a data segment descriptor for a 80386
running in protected mode. The segment starts at
40000000H, already present, privilege level is 0, expand-up,
writeable, has been accessed and its size is 4 MB.
ƒ AR = 1 00 10 0 1 1 = 93H
ƒ Since its size is 4 MB,
G = 1, high byte of +6 byte = 1--- (eg. 8H)
ƒ Size = 4 MB = 400 000H, 4 MB -1 = 3FF FFFH, hence
Limit = 003FFH

+7 4 0 8 0 +6
+5 9 3 0 0 +4
+3 0 0 0 0 +2
+1 0 3 F F +0

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 486 (1989)
ƒ Like 386, full 32-bit architecture: 32-bit address bus, 32-bit
data bus, 32-bit registers, 32-bit offset.
ƒ new core (4th generation core): many instructions take 2
clocks in 386 run in 1 clock.
ƒ Integrated 8KB of Unified (Instruction & Date) Level-1 cache.
ƒ Integrated floating point processor (except SX model).
ƒ 168-pin PGA.

486 = 386 (new core) + 387 (floating point processor)

+ 8KB Level-1 Unified Cache

486 Architecture

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 486 Pin-out

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Pentium™ (1993)
ƒ 64-bit data bus, 32-bit registers, 32-bit address bus, supports
up to 4GB of memory.
ƒ Three pipelined Execution Units: Two integer unit and one
floating point unit. Two scalar instructions can be executed
simultaneously in one clock - superscalar.
ƒ 386 supports external cache through a external cache
controller. 486 has 8KB of level-1 unified cache. Pentium has
8KB (or 16KB) of Instruction cache (I-cache) and 8KB (or
16KB) of Data cache (D-cache).
ƒ Branch Prediction logic to avoid flushing of pipe.
ƒ New P5 core, 5 times faster than 486.
ƒ 237-pin PGA.

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 Pentium Architecture

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Pentium Pro (1995)

ƒ New P6 core.
ƒ 5.5 millions transistors in the CPU core, closely coupled with
the Level-2 cache
∗ 15.5 millions transistors for 256KB L2 cache
∗ 31 millions transistors for 512KB L2 cache
∗ 62 millions transistors for 1MB L2 cache
ƒ 8KB/16KB 2-way set-associative Level-1 I-cache, 8KB/16KB
4-way set-associative Level-1 D-cache.
ƒ 3-way superscalar in 6-instruction pipes.
ƒ 256KB/512KB/1MB Level-2 cache, closely coupled.
ƒ out-of-order execution, dynamic branch prediction, and
speculative execution, to avoid flushing of pipes.
ƒ Dual Independent Bus (DIB):
∗ system bus for the processor and memory.
∗ L2 cache bus for the processor and L2 cache.
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 P6 Architecture

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Pentium MMX (1996)

ƒ P5 core.
ƒ 57 new instructions and 8 new registers that are optimized
for multimedia operations.
ƒ SIMD (Single Instruction Multiple Data) enables one
instruction to perform the same function on multiple pieces of
data – parallel processing.
ƒ More Level-1 cache than Pentium, 32KB (16-KB of I-cache &
16KB of D-cache).

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 Pentium II (1997)
ƒ P6 core.
ƒ Single Edge Contact (SEC) cartridge replacing the PGA
packaging.
ƒ Dual Independent Bus (DIB) architecture: L2 cache bus and
the processor-to-main-memory bus.
ƒ 32KB built-in Level-1 cache (16KB I-cache & 16KB D-cache).
ƒ 512KB Level-2 cache (external).

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Pentium II Interior

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 Pentium III (1999)
ƒ P6 core, 650MHz to 1 GHz, System Bus 100-133MHz.
ƒ 70 new MMX instructions – Steaming SIMD Extension (SSE)
for multimedia operations such as advanced imaging, 3D,
streaming audio and video.
ƒ Intel processor identification number.
ƒ 32KB Level-1 cache (16KB of Instruction-cache and 16KB of
Data-cache), 256KB or 512KB of Level-2 cache.
ƒ Uses SDRAM (Synchronous Dynamic RAM)

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Pentium IV (2000+)
ƒ 1.3, 1.4, 1.5, 1.7GHz, with 400MHz system bus.
ƒ 144 new MMX instructions – Streaming SIMD Extension 2
(SSE2) – for digital video and online gaming.
ƒ Intel NetBurst microarchitecture:
∗ hyper pipeline doubles the pipeline depth to 20 stages.
∗ improve advance dynamic execution.
ƒ Uses DDRAM.

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