8 7 6 5 4 3 2 1

D6990
J30 POWER SYSTEM ARCHITECTURE
2 ENABLE
PPDCIN_G3H
R6990 PPDCIN_S5_P3V42G3H
3.425V G3HOT
PM6640 PP3V42_G3H_REG 3 SMC PWRGD
SN0903048 SMC_RESET_L 4
U6990
R6905
(PAGE 63)
U5010
(PAGE 44)
Q5300

1 V R5400 15 R7640

D J6900
Q5310
F7040 PP5V_S0_CPUVCCIOS0
PPCPUVCCIO_S0_REG D
F6905
PPBUS_G3H
A
VCC 1.05VVOUT
ISL95870
A 22
AC DCIN(16.5V)
6A FUSE V R7020 CPUVCCIOS0_EN EN
U7600 SMC_CPU_FSB_ISENSE

ADAPTER A VIN
U7000
PPVBAT_G3H 21 (PAGE 70)
PGOOD
CPUVCCIOS0_PGOOD
22-1
VOUT
IN ISL6259HRTZ
SMC_DCIN_ISENSE

PBUS SUPPLY/
1 VIN
V R5320
SMC_CPU_VSENSE
25 TPS22924
R7050 PPVCORE_S0_CPU_REG U4202 PP1V0_FW_FWPHY
VOUT

SMC_RESET_L
BATTERY CHARGER
A 24 CPU VCORE
MAX15119GTM
(PAGE 39)
EN
SMC_BATT_ISENSE
R5330
(PAGE 63)
CPUIMVP_VR_ON
VR_ON
U7400
V SMC_GFX_VSENSE FW_PWR_EN

PPVCORE_S0_AXG_REG
J6950
Q7055
(PAGE 68)
VOUT 26
PPVBATT_G3H_CONN PPVBAT_G3H_CHGR_R
CPUIMVP_PGOOD 25-1
(9 TO 12.6V)

PGOOD
3S2P

CPUIMVP_AXG_PGOOD COUGAR-POINT
CHGR_BGATE
PGOODG
26-1 PM_PWRBTN_L

(PCH) PWRBTN#
SYS_RERST# PM_SYSRST_L

RSMRST# PM_RSMRST_L
VIN VLDOIN
DDRREG_EN
S5
1.5V
VOUT1
PPDDR_S3_REG 16 27 U1800 PM_DSW_PWRGD

C DDRVTT_EN
S3 0.75V
VOUT2
PPVTT_S0_DDR_LDO
PM_PCH_PWRGD PLT_RERST_L 29 C
PLTRST#

TPS51916 CPU_PWRGD 28
SMC U7300 PGOOD
DDRREG_PGOOD U2850 PROCPWRGD

PM_MEM_PWRGD
(PAGE 67) Q7801 DRAMPWROK
PP1V5S0FET_GATE (PAGE 16~21)
U4900
6 RC P3V3S5_EN
7 PP1V5_S3RS0_FET 30
P60
PP5V_S0_FET
DELAY VCC
SMC_PM_G2_EN PPVCCSA_S0_REG
(PAGE 44)
22 PVCCSA_EN EN
ISL95870A
VOUT
23
CPU_VCCSA_VID<1> U7100
VID0
R7916 PVCCSA_PGOOD
CPU_VCCSA_VID<0> PGOOD SM_DRAMPWROK
P3V3S4_EN PG73 VID1 (PAGE 65) CPUIMVP_AXG_PGOOD
11 R5410
23-1 P1V8S0_PGOOD
CPU
PPBUS_S5_HS_OTHER_ISNS U1000 UNCOREPWRGOOD
SLP_S5#(E4)
PM_SLP_S5_L PG 17

11 A VIN
14 P5V3V3_PGOOD

P5VS3_EN_L PP5V_S3_REG Q7860 RESET*

COUGAR-POINT 5V CPUVCCIOS0_PGOOD
(PCH) R7917
P5V_3V3_SUS_EN
10-1 13 EN1
(L/H)
VOUT1

PP5V_S0_FET PVCCSA_PGOOD
(PAGE 9~13)

SLP_SUS PG73
P3V3S5_EN_L 3.3V
PP3V3_S5_REG PP3V3_S5
15
RC P5VS3_EN PG73
7 EN2
(R/H)
VOUT2
8 ALL_SYS_PWRGD

DELAY 13-1 TPS51125

U7200
P5VS0_EN

VREG5
(PAGE 66)
Q4590
SMC PM_DSW_PWRGD 10
RC DDRREG_EN PG73
15 PGOOD PP5V_SW_ODD
25
PP5V_S5_LDO

PWRGD(P12)

B U1800
DELAY

Q9706
P5V3V3_PGOOD
RSMRST_PWRGD
9 12 B
P3V3S3_EN PG73
13-2 F9700
14-1
ODD_PWR_EN_L

BCM57765 PP1V2_ENET_PHY PP3V3_S0_VMON

RSMRST_IN(P13)
RSMRST_OUT(P15) PM_RSMRST_L

PP3V3_ENET SMC_ONOFF_L 99ms DLY

PP5V_SUS_FET
EN U3900
5
PWR_BUTTON(P90)
IMVP_VR_ON(P16)
CPUIMVP_VR_ON
26
SLP_S4#(H4)
PM_SLP_S4_L PG 17
13 LCD_BKLT_EN
Q7922
CAESAR IV
(PAGE 36) PM_SYSRST_L
&& BKLT_PLT_RST_L Q7840
10-2 SYSRST(PA2)

SLP_S3#(F4)
PM_SLP_S3_L PG 17
14 VIN P5V_3V3_SUS_EN
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN//WOL_EN
R7803
PP5V_S0_VMON

PP1V5_S3RS0_VMON
VMON_Q2 U7960
ISL88042IRTEZ PM_PWRBTN_L
6-1
VMON_Q3 P17(BTN_OUT)
LP8550
PP1V05_S0_VMON PM_SLP_S5_L
(PAGE 16~21) PPBUS_SW_LCDBKLT_PWR U9701 PP3V3_S4_FET
VMON_Q4 SLP_S5_L(P95)
SMC_RESET_L 4
EN
VOUT
PPVOUT_SW_LCDBKLT
Q7800
12 (PAGE 73)
PM_SLP_S4_L
SLP_S4_L(P94)
RES*

PM_SLP_S3_L
(PAGE 76) SLP_S3_L(P93)

R7978 PG73 P3V3S4_EN

U4900
(PAGE 43)
Q4260
F4260
PP3V3_S3
14 PP3V3_S0
16
Q7810
PPBUS_FW_FET
PM_SLP_S3_L_R
P3V3S3_EN MAX15053EWL
P1V8_S0_EN PP1V8_S0_REG
EN
U7760 18
FWP5ORT_PWR_EN
PP3V3_SUS_FET
10-3 17 (PAGE 71)

Q3880
Q7820
TPS720105 19
1V05_S0_LDO_EN
21 P5V_3V3_SUS_EN
P1V05_S0_LDO_EN
EN U7780
PP1V05_S0_LDO

A RC CPUVCCIOS0_EN
21 P5VS0_EN 14-1 (PAGE 71) SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009 A
DELAY PAGE TITLE
TPS720105 TPS62201
U7740
PP1V05_SUS_LDO 9 P1V5S0_EN
EN U7770
PP1V5_S0_REG
20 Revision History
RC PVCCSA_EN 22 P3V3S0_EN
14-1
T29_A_HV_EN
(PAGE 71) 19 (PAGE8 71) DRAWING NUMBER SIZE
DELAY
VIN Apple Inc. 051-9058 D
Q7830 REVISION
PBUSVSENS_EN LT3957
RC P1V5S0_EN 19 14-1 U3890 PP3V3_FW_P3V3FWFET TPS22924
PP3V3_FW_FE5T
R
6.0.0
DELAY PM_SLP_S3_L_R 14 EN U4201
(PAGE 39)
NOTICE OF PROPRIETARY PROPERTY: BRANCH
VOUT PP15V_T29_REG THE INFORMATION CONTAINED HEREIN IS THE
(PAGE 35) PROPRIETARY PROPERTY OF APPLE INC.
P1V8S0_EN
RC
DELAY
17 THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PAGE
3 OF 109
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 86
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