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Adm202e - Adm1181a (RS232)

The document describes an RS-232 line driver/receiver chip that provides ESD protection and complies with EMC standards. It operates from a single 5V supply and supports data rates up to 230kbps. It provides a robust upgrade for existing similar chips and is available in various package options.

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0% found this document useful (0 votes)
60 views12 pages

Adm202e - Adm1181a (RS232)

The document describes an RS-232 line driver/receiver chip that provides ESD protection and complies with EMC standards. It operates from a single 5V supply and supports data rates up to 230kbps. It provides a robust upgrade for existing similar chips and is available in various package options.

Uploaded by

SERVICE WEB
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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a EMI/EMC-Compliant, 15 kV ESD Protected,

RS-232 Line Drivers/Receivers


ADM202E/ADM1181A
FEATURES FUNCTIONAL BLOCK DIAGRAMS
Complies with 89/336/EEC EMC Directive
ESD Protection to IEC1000-4-2 (801.2) 5V INPUT

8 kV: Contact Discharge 0.1F


1 C1+ +5V TO +10V VCC 16
C3
15 kV: Air-Gap Discharge 10V 3 C1–
VOLTAGE
DOUBLER V+ 2 0.1F
C5
0.1F
15 kV: Human Body Model 6.3V
0.1F 4 C2+ +10V TO –10V V– 6
EFT Fast Transient Burst Immunity (IEC1000-4-4) 10V VOLTAGE C4
5 C2– INVERTER 0.1F
Low EMI Emissions (EN55022) 10V
230 kbits/s Data Rate Guaranteed T1IN 11 T1 14 T1OUT
TSSOP Package Option CMOS EIA/TIA-232
INPUTS OUTPUTS
Upgrade for MAX202E, 232E, LT1181A T2IN 10 T2 7 T2OUT

APPLICATIONS R1OUT 12 R1 13 R1IN


General-Purpose RS-232 Data Link CMOS EIA/TIA-232
OUTPUTS INPUTS*
Portable Instruments R2OUT 9 R2 8 R2IN
PDAs
GND ADM202E
15

GENERAL DESCRIPTION
The ADM202E and ADM1181A are robust, high speed, *INTERNAL 5k PULL-DOWN RESISTOR ON EACH RS-232 INPUT
2-channel RS232/V.28 interface devices that operate from a
single 5 V power supply. Both products are suitable for opera- 5V INPUT
tion in harsh electrical environments and are compliant with the
0.1F
1
C1+ +5V TO +10V VCC 16
EU directive on EMC (89/336/EEC). Both the level of electro- 10V
VOLTAGE C5
3 C1–
DOUBLER V+ 2 0.1F
magnetic emissions and immunity are in compliance. EM C3 10V
immunity includes ESD protection in excess of ± 15 kV on all 0.1F 4 C2+ +10V TO –10V V– 6
VOLTAGE C4
0.1F
10V
10V
I/O lines, Fast Transient burst protection (1000-4-4) and Radi- 5 C2– INVERTER 0.1F
10V
ated Immunity (1000-4-3). EM emissions include radiated and
T1IN 11 T1 14 T1OUT
conducted emissions as required by Information Technology CMOS EIA/TIA-232
Equipment EN55022, CISPR22. INPUTS
T2IN 10 T2 7 T2OUT
OUTPUTS

The ADM202E and ADM1181A conform to the EIA-232E


12 R1 13 R1IN
and CCITT V.28 specifications and operate at data rates up to CMOS
R1OUT
EIA/TIA-232
230 kbps. OUTPUTS
9 8
INPUTS*
R2OUT R2 R2IN
Four external 0.1 µF charge pump capacitors are used for the
voltage doubler/inverter permitting operation from a single ADM1181A
GND
5 V supply. 15

The ADM202E provides a robust pin-compatible upgrade for


*INTERNAL 5k PULL-DOWN RESISTOR ON EACH RS-232 INPUT
existing ADM202, ADM232L or MAX202E/MAX232E sock-
ets. It is available in a 16-lead DIP, wide and narrow SO and
also a space saving TSSOP package. The TSSOP package gives
ORDERING GUIDE
a 44% space saving over SOIC.
The ADM1181A provides a robust pin compatible upgrade for Temperature Package Package
the LTC1181A, and it is available in 16-lead DIP and 16-lead Model Range Description Option
SO packages.
ADM202EAN –40°C to +85°C Plastic DIP N-16
ADM202EARW –40°C to +85°C Wide SOIC R-16W
ADM202EARN –40°C to +85°C Narrow SOIC R-16N
ADM202EARU –40°C to +85°C TSSOP RU-16
ADM1181AAN –40°C to +85°C Plastic DIP N-16
ADM1181AARW –40°C to +85°C Wide SOIC R-16W
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001
= 5.0 V  10%, C1–C4 = 0.1 F. All specifications
ADM202E/ADM1181A–SPECIFICATIONS T(V CC
MIN to TMAX unless otherwise noted.)
Parameter Min Typ Max Unit Test Conditions/Comments
DC CHARACTERISTICS
Operating Voltage Range 4.5 5.0 5.5 Volts
VCC Power Supply Current 2.5 6.0 mA No Load
13 18 mA RL = 3 kΩ to GND
LOGIC
Input Logic Threshold Low, VINL 0.8 V TIN
Input Logic Threshold High, VINH 2.4 V TIN
CMOS Output Voltage Low, VOL 0.4 V IOUT = 3.2 mA
CMOS Output Voltage High, VOH 3.5 V IOUT = –1 mA
Logic Pull-Up Current 12 ± 25 µA TIN = 0 V
RS-232 RECEIVER
EIA-232 Input Voltage Range –30 +30 V
EIA-232 Input Threshold Low 0.4 1.2 V
EIA-232 Input Threshold High 1.6 2.4 V
EIA-232 Input Hysteresis 0.4 V
EIA-232 Input Resistance 3 5 7 kΩ TA = 0°C to 85°C
RS-232 TRANSMITTER
Output Voltage Swing ± 5.0 ± 9.0 Volts All Transmitter Outputs
Loaded with 3 kΩ to Ground
Transmitter Output Resistance 300 Ω VCC = 0 V, VOUT = ± 2 V
RS-232 Output Short Circuit Current ± 10 ± 60 mA
TIMING CHARACTERISTICS
Maximum Data Rate 230 kbps RL = 3 kΩ to 7 kΩ, CL = 50 pF to 1000 pF
Receiver Propagation Delay
TPHL 0.1 1 µs
TPLH 0.3 1 µs
Transmitter Propagation Delay 1.0 1.5 µs RL = 3 kΩ, CL = 1000 pF
Transition Region Slew Rate 3 8 30 V/µs RL = 3 kΩ, CL = 1000 pF
Measured from +3 V to –3 V or
–3 V to +3 V
EM IMMUNITY
ESD Protection (I/O pins) ± 15 kV Human Body Model
± 15 kV IEC1000-4-2 Air Discharge
± 8 kV kV IEC1000-4-2 Contact Discharge
EFT Protection (I/O pins) ±2 kV IEC1000-4-4
EMI Immunity 10 V/m IEC1000-4-3
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* Power Dissipation R-16 . . . . . . . . . . . . . . . . . . . . . . . 450 mW


(TA = 25°C unless otherwise noted) (Derate 6 mW/°C above 50°C)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 158°C/W
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VCC – 0.3 V) to +14 V Power Dissipation RU-16 . . . . . . . . . . . . . . . . . . . . . 500 mW
V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –14 V (Derate 6 mW/°C above 50°C)
Input Voltages θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 158°C/W
TIN . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V+, +0.3 V) Operating Temperature Range
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 V Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Output Voltages Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 15 V Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . 300°C
ROUT . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V) ESD Rating (MIL-STD-883B) (I/O Pins) . . . . . . . . . . ± 15 kV
Short Circuit Duration ESD Rating (IEC1000-4-2 Air) (I/O Pins) . . . . . . . . . ± 15 kV
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating (IEC1000-4-2 Contact) (I/O Pins) . . . . . . ± 8 kV
Power Dissipation EFT Rating (IEC1000-4-4) (I/O Pins) . . . . . . . . . . . . . ± 2 kV
Power Dissipation N-16 . . . . . . . . . . . . . . . . . . . . . . 450 mW *This is a stress rating only and functional operation of the device at these or any
(Derate 6 mW/°C above 50°C) other conditions above those indicated in the operation sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W periods of time may affect reliability.

–2– REV. B
ADM202E/ADM1181A
PIN FUNCTION DESCRIPTION PIN CONNECTIONS

Mnemonic Function
C1+ 1 16 VCC
VCC Power Supply Input: 5 V ± 10%. V+ 2 15 GND
V+ Internally Generated Positive Supply C1– 3 ADM202E 14 T1OUT
(+9 V nominal). ADM1181A
C2+ 4 13 R1IN
V– Internally Generated Negative Supply C2– 5 TOP VIEW 12 R1OUT
(Not to Scale)
(–9 V nominal). V– 6 11 T1IN

GND Ground Pin. Must Be Connected to 0 V. T2OUT 7 10 T2IN

C1+, C1– External Capacitor 1 is connected between R2IN 8 9 R2OUT

these pins. 0.1 µF capacitor is recommended


but larger capacitors up to 47 µF may be used.
C2+, C2– External Capacitor 2 is connected between
these pins. 0.1 µF capacitor is recommended
but larger capacitors up to 47 µF may be used.
TIN Transmitter (Driver) Inputs. These inputs
accept TTL/CMOS levels.
TOUT Transmitter (Driver) Outputs. These are
RS-232 signal levels (typically ± 9 V).
RIN Receiver Inputs. These inputs accept RS-232
signal levels. An Internal 5 kΩ pull-down resis-
tor to GND is connected on each input.
ROUT Receiver Outputs. These are CMOS output
logic levels.

5V INPUT 5V INPUT

0.1F C1+ +5V TO +10V VCC 0.1F C1+ +5V TO +10V VCC
VOLTAGE C3 VOLTAGE C5
10V C5 10V
C1– DOUBLER V+ 0.1F C1– DOUBLER V+ 0.1F
0.1F C3
6.3V 10V
0.1F
0.1F C2+ +10V TO –10V V– 0.1F C2+ +10V TO –10V V– C4
VOLTAGE C4 VOLTAGE 10V
10V 10V 0.1F
C2– INVERTER 0.1F C2– INVERTER
10V 10V

T1IN T1 T1OUT T1IN T1 T1OUT


CMOS EIA/TIA-232 CMOS EIA/TIA-232
INPUTS OUTPUTS INPUTS OUTPUTS
T2IN T2 T2OUT T2IN T2 T2OUT

R1OUT R1 R1IN R1OUT R1 R1IN


CMOS EIA/TIA-232 CMOS EIA/TIA-232
OUTPUTS INPUTS* OUTPUTS INPUTS*
R2OUT R2 R2IN R2OUT R2 R2IN

ADM202E GND
ADM1181A
GND

*INTERNAL 5k PULL-DOWN RESISTOR ON EACH RS-232 INPUT *INTERNAL 5k PULL-DOWN RESISTOR ON EACH RS-232 INPUT

ADM202E Typical Operating Circuit ADM1181A Typical Operating Circuit

REV. B –3–
ADM202E/ADM1181A
GENERAL DESCRIPTION VCC
S1 S3
V+ = 2VCC
The ADM202E/ADM1181E are ruggedized RS-232 line drivers/
C1 C3
receivers. Step-up voltage converters coupled with level shifting S2 S4
transmitters and receivers allow RS-232 levels to be developed GND VCC
while operating from a single 5 V supply.
Features include low power consumption, high transmission INTERNAL
OSCILLATOR
rates and compatibility with the EU directive on Electromag-
netic compatibility. EM compatibility includes protection NOTE: C3 CONNECTS BETWEEN V+ AND GND ON THE ADM1181A
against radiated and conducted interference including high Figure 1. Charge Pump Voltage Doubler
levels of Electrostatic Discharge.
All inputs and outputs contain protection against Electrostatic
Discharges up to ± 15 kV and Electrical Fast Transients up to S1 S3
V+ GND
± 2 kV. This ensures compliance to IE1000-4-2 and IEC1000-4-4 FROM
VOLTAGE C2 C4
requirements. DOUBLER S2 S4
GND V– = –(V+)
The devices are ideally suited for operation in electrically harsh
environments or where RS-232 cables are frequently being
plugged/unplugged. They are also immune to high RF field INTERNAL
OSCILLATOR
strengths without special shielding precautions.
CMOS technology is used to keep the power dissipation to an Figure 2. Charge Pump Voltage Inverter
absolute minimum allowing maximum battery life in portable Transmitter (Driver) Section
applications. The drivers convert 5 V logic input levels into RS-232 output
The ADM202E/ADM1181A is a modification, enhancement levels. With VCC = 5 V and driving an RS-232 load, the output
and improvement to the AD230–AD241 family and its deriva- voltage swing is typically ± 9 V.
tives. It is essentially plug-in compatible and does not have Receiver Section
materially different applications. The receivers are inverting level shifters which accept RS-232
input levels and translate them into 5 V logic output levels.
CIRCUIT DESCRIPTION The inputs have internal 5 kΩ pull-down resistors to ground
The internal circuitry consists of four main sections. These are: and are also protected against overvoltages of up to ± 30 V.
1. A charge pump voltage converter Unconnected inputs are pulled to 0 V by the internal 5 kΩ pull-
2. 5 V logic to EIA-232 transmitters down resistor. This, therefore, results in a Logic 1 output level
for unconnected inputs or for inputs connected to GND.
3. EIA-232 to 5 V logic receivers.
4. Transient protection circuit on all I/O lines The receivers have Schmitt trigger inputs with a hysteresis level
of 0.5 V. This ensures error-free reception for both noisy inputs
Charge Pump DC-DC Voltage Converter and for inputs with slow transition times.
The charge pump voltage converter consists of an 200 kHz
oscillator and a switching matrix. The converter generates a HIGH BAUD RATE
± 10 V supply from the input 5 V level. This is done in two The ADM202E/ADM1181A feature high slew rates permitting
stages using a switched capacitor technique as illustrated below. data transmission at rates well in excess of the EIA/RS-232-E
First, the 5 V input supply is doubled to 10 V using capacitor C1 specifications. RS-232 voltage levels are maintained at data rates
as the charge storage element. The 10 V level is then inverted to up to 230 kb/s even under worst case loading conditions. This
generate –10 V using C2 as the storage element. allows for high speed data links between two terminals or indeed
Capacitors C3 and C4 are used to reduce the output ripple. it is suitable for the new generation ISDN modem standards which
Their values are not critical and can be increased if desired. On requires data rates of 230 kbps. The slew rate is internally con-
the ADM202E, capacitor C3 is shown connected between V+ trolled to less than 30 V/µs in order to minimize EMI interference.
and VCC, while it is connected between V+ and GND on the
ADM1181A. It is acceptable to use either configuration with both
the ADM202E and ADM1181A. If desired, larger capacitors
(up to 47 µF) can be used for capacitors C1–C4. This facilitates
direct substitution with older generation charge pump RS-232
transceivers.

–4– REV. B
ADM202E/ADM1181A
ESD/EFT TRANSIENT PROTECTION SCHEME.
The ADM202E/ADM1181A use protective clamping structures R1
RECEIVER RX
INPUT
on all inputs and outputs which clamp the voltage to a safe level D1
and dissipate the energy present in ESD (Electrostatic) and EFT RIN
D2
(Electrical Fast Transients) discharges. A simplified schematic
of the protection structure is shown in Figure 3. Each input and
output contains two back-to-back high speed clamping diodes.
During normal operation with maximum RS-232 signal levels, Figure 3a. Receiver Input Protection Scheme
the diodes have no effect as one or the other is reverse biased
depending on the polarity of the signal. If however the volt-
age exceeds about 50 V in either direction, reverse breakdown TOUT
occurs and the voltage is clamped at this level. The diodes are RX TRANSMITTER
OUTPUT
large p-n junctions that are designed to handle the instanta- D1

neous current surge which can exceed several amperes. D2


The transmitter outputs and receiver inputs have a similar pro-
tection structure. The receiver inputs can also dissipate some of
the energy through the internal 5 kΩ resistor to GND as well as Figure 3b. Transmitter Output Protection Scheme
through the protection diodes.
The protection structure achieves ESD protection up to ± 15 kV
and EFT protection up to ± 2 kV on all RS-232 I/O lines. The
methods used to test the protection scheme are discussed later.

Typical Performance Characteristics


80 80

70 70

60 60 LIMIT

50 50
dBV
dBV

40 LIMIT 40

30 30

20 20

10 10

0 0
START 30.0MHz STOP 200.0MHz 0.3 0.6 1 3 6 10 30
LOG FREQUENCY – MHz

TPC 1. EMC Radiated Emissions TPC 2. EMC Conducted Emissions

REV. B –5–
ADM202E/ADM1181A –Typical Performance Characteristics
9 15
115KBPS
7
230KBPS 10
5
TX O/P HI
3 460KBPS 5

TX O/P – V
TX O/P – V

1
0
–1

–3 460KBPS –5
TX O/P LO
–5 230KBPS
–10
–7 115KBPS

–9 –15
0 500 1000 1500 2000 2500 3000 0 2 4 6 8 10 12 14
LOAD CAPACITANCE – pF ILOAD – mA

TPC 3. Transmitter Output Voltage High/Low vs. TPC 6. Transmitter Output Voltage Low/High vs.
Load Capacitance @ 115 kbps, 230 kbps and 460 kbps Load Current

15

TX O/P HI
10
1 T
TX O/P HI LOADED

5
TX O/P – V

0 2

–5 T
TX O/P LO LOADED

–10
TX O/P LO

–15
4 4.5 5 5.5 Ch1 5.00V Ch2 5.00V M 2.00s Ch1 400mV
VCC – V

TPC 4. Transmitter Output Voltage High/Low vs. VCC TPC 7. 230 kbps Data Transmission

15 300

10 250

V–
5 200
IMPEDANCE – 
V+, V– – V

0 150
V+

–5 100

–10 50

–15 0
0 5 10 15 20 25 30 4 4.5 5 5.5 6
ILOAD – mA VCC – V

TPC 5. Charge Pump V+, V– vs. Current TPC 8. Charge Pump Impedance vs. VCC

–6– REV. B
ADM202E/ADM1181A
ESD TESTING (IEC1000-4-2)
IEC1000-4-2 (previously 801-2) specifies compliance testing 100

using two coupling methods, contact discharge and air-gap 90

discharge. Contact discharge calls for a direct connection to the


unit being tested. Air-gap discharge uses a higher test voltage

IPEAK – %
but does not make direct contact with the unit under test. With
air discharge, the discharge gun is moved towards the unit under
test developing an arc across the air gap, hence the term air-gap 36.8
discharge. This method is influenced by humidity, temperature,
barometric pressure, distance and rate of closure of the discharge
gun. The contact-discharge method while less realistic is more 10

repeatable and is gaining acceptance in preference to the air- tRL tDL TIME t
gap method.
Figure 5. Human Body Model ESD Current Waveform
Although very little energy is contained within an ESD pulse,
the extremely fast rise time coupled with high voltages can cause
failures in unprotected semiconductors. Catastrophic destruc-
tion can occur immediately as a result of arcing or heating. Even 100

if catastrophic failure does not occur immediately, the device 90


may suffer from parametric degradation which may result in

IPEAK – %
degraded performance. The cumulative effects of continuous
exposure can eventually lead to complete failure.
I/O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I/O cable can result in a static dis-
charge which can damage or completely destroy the interface
product connected to the I/O port. Traditional ESD test meth-
10
ods such as the MIL-STD-883B method 3015.7 do not fully
test a product’s susceptibility to this type of discharge. This test 0.1 TO 1ns TIME t
30ns
was intended to test a product’s susceptibility to ESD damage 60ns
during handling. Each pin is tested with respect to all other
pins. There are some important differences between the tradi- Figure 6. IEC1000-4-2 ESD Current Waveform
tional test and the IEC test: The ADM202E/ADM1181E products are tested using both the
a. The IEC test is much more stringent in terms of discharge above mentioned test methods. All pins are tested with respect
energy. The peak current injected is over four times greater. to all other pins as per the MIL-STD-883B specification. In
b. The current rise time is significantly faster in the IEC test. addition all I/O pins are tested as per the IEC test specification.
c. The IEC test is carried out while power is applied to the device. The products were tested under the following conditions:
It is possible that the ESD discharge could induce latch-up in the a. Power-On
device under test. This test therefore is more representative of a b. Power-Off
real-world I/O discharge where the equipment is operating nor- There are four levels of compliance defined by IEC1000-4-2.
mally with power applied. For maximum peace of mind, however, The ADM202E/ADM1181A products meet the most stringent
both tests should be performed therefore ensuring maximum compliance level for both contact and for air-gap discharge. This
protection both during handling and later during field service. means that the products are able to withstand contact discharges
in excess of 8 kV and air-gap discharges in excess of 15 kV.
R1 R2
HIGH
VOLTAGE
GENERATOR
DEVICE
C1 UNDER TEST

ESD TEST METHOD R2 C1


H. BODY MIL-STD883B 1.5k 100pF
IEC1000-4-2 330 150pF

Figure 4. ESD Test Standards

REV. B –7–
ADM202E/ADM1181A
Table I. IEC1000-4-2 Compliance Levels A simplified circuit diagram of the actual EFT generator is illus-
trated in Figure 8.
Level Contact Discharge Air Discharge
The transients are coupled onto the signal lines using an EFT
1 2 kV 2 kV coupling clamp. The clamp is 1 m long and it completely sur-
2 4 kV 4 kV rounds the cable providing maximum coupling capacitance
3 6 kV 8 kV (50 pF to 200 pF typ) between the clamp and the cable. High
4 8 kV 15 kV energy transients are capacitively coupled onto the signal lines.
Fast rise times (5 ns) as specified by the standard result in very
effective coupling. This test is very severe since high voltages are
Table II. ADM202E/ADM1181A ESD Test Results coupled onto the signal lines. The repetitive transients can often
cause problems where single pulses do not. Destructive latchup
ESD Test Method I/O Pins
may be induced due to the high energy content of the transients.
MIL-STD-883B ± 15 kV Note that this stress is applied while the interface products are
IEC1000-4-2 powered up and are transmitting data. The EFT test applies
Contact ± 8 kV hundreds of pulses with higher energy than ESD. Worst case
Air ± 15 kV transient current on an I/O line can be as high as 40 A.

FAST TRANSIENT BURST TESTING (IEC1000-4-4) HIGH RC L RM CD


VOLTAGE 50
IEC1000-4-4 (previously 801-4) covers electrical fast-transient/ SOURCE OUTPUT
burst (EFT) immunity. Electrical fast transients occur as a CC ZS
result of arcing contacts in switches and relays. The tests simu-
late the interference generated when for example a power relay
disconnects an inductive load. A spark is generated due to the Figure 8. IEC1000-4-4 Fast Transient Generator
well known back EMF effect. In fact the spark consists of a
burst of sparks as the relay contacts separate. The voltage appear- Test results are classified according to the following:
ing on the line therefore consists of a bust of extremely fast 1. Normal performance within specification limits.
transient impulses. A similar effect occurs when switching on 2. Temporary degradation or loss of performance that is
fluorescent lights. self-recoverable.
The fast transient burst test defined in IEC1000-4-4 simulates 3. Temporary degradation or loss of function or performance
this arcing and its waveform is illustrated in TPC 8. It consists that requires operator intervention or system reset.
of a burst of 2.5 kHz to 5 kHz transients repeating at 300 ms 4. Degradation or loss of function that is not recoverable due
intervals. It is specified for both power and data lines. to damage.
The ADM202E/ADM1181A have been tested under worst-case
V conditions using unshielded cables and meet Classification 2.
Data transmission during the transient condition is corrupted,
but it may be resumed immediately following the EFT event
t without user intervention.
300ms 15ms

5ns
V

50ns

0.2/0.4ms

Figure 7. IEC1000-4-4 Fast Transient Waveform

–8– REV. B
ADM202E/ADM1181A
IEC1000-4-3 RADIATED IMMUNITY ducted emissions. It is, therefore, important that the switches in
IEC1000-4-3 (previously IEC801-3) describes the measurement the charge pump guarantee break-before-make switching under
method and defines the levels of immunity to radiated elec- all conditions so that instantaneous short circuit conditions do
tromagnetic fields. It was originally intended to simulate the not occur.
electromagnetic fields generated by portable radio transceivers The ADM202E has been designed to minimize the switching
or any other device which generates continuous wave radiated transients and ensure break-before-make switching thereby
electromagnetic energy. Its scope has since been broadened to minimizing conducted emissions. This has resulted in the
include spurious EM energy which can be radiated from fluores- level of emissions being well below the limits required by the
cent lights, thyristor drives, inductive loads, etc. specification. No additional filtering/decoupling other than the
Testing for immunity involves irradiating the device with an EM recommended 0.1 µF capacitor is required.
field. There are various methods of achieving this including use Conducted emissions are measured by monitoring the mains
of anechoic chamber, stripline cell, TEM cell, GTEM cell. A line. The equipment used consists of a LISN (Line Impedance
stripline cell consists of two parallel plates with an electric field Stabilizing Network) that essentially presents a fixed impedance
developed between them. The device under test is placed within at RF, and a spectrum analyzer. The spectrum analyzer scans
the cell and exposed to the electric field. There are three severity for emissions up to 30 MHz and a plot for the ADM202E is
levels having field strengths ranging from 1 V to 10 V/m. Results shown in Figure 11.
are classified in a similar fashion to those for IEC1000-4-2.
1. Normal Operation. S1 S3
VCC V+ = 2V C C
2. Temporary Degradation or loss of function that is self- C3
C1
recoverable when the interfering signal is removed. S2 S4
GND VCC
3. Temporary degradation or loss of function that requires
operator intervention or system reset when the interfering
INTERNAL
signal is removed. OSCILLATOR
4. Degradation or loss of function that is not recoverable due
to damage. Figure 9. Charge Pump Voltage Doubler
The ADM202E/ADM1181A products easily meet Classifica-
tion 1 at the most stringent (Level 3) requirement. In fact field
strengths up to 30 V/m showed no performance degradation, and ø1
error-free data transmission continued even during irradiation.

Table III. Test Severity Levels (IEC1000-4-3)


ø2
Level Field Strength V/m
SWITCHING GLITCHES
1 1
2 3
3 10

Figure 10. Switching Glitches


EMISSIONS/INTERFERENCE
EN55 022, CISPR22 defines the permitted limits of radiated
and conducted interference from Information Technology (IT) 80
equipment. The objective of the standard is to minimize the
70
level of emissions both conducted and radiated.
60
For ease of measurement and analysis, conducted emissions are LIMIT

assumed to predominate below 30 MHz and radiated emissions 50


are assumed to predominate above 30 MHz.
dBV

40

CONDUCTED EMISSIONS
30
This is a measure of noise that gets conducted onto the mains
power supply. Switching transients from the charge pump that 20
are 20 V in magnitude and contain significant energy can lead to
10
conducted emissions. Other sources of conducted emissions can
be due to overlap in switch on-times in the charge pump voltage 0
0.3 0.6 1 3 6 10 30
converter. In the voltage doubler shown below, if S2 has not LOG FREQUENCY – MHz
fully turned off before S4 turns on, this results in a transient
Figure 11. ADM202E Conducted Emissions Plot
current glitch between VCC and GND which results in con-

REV. B –9–
ADM202E/ADM1181A
RADIATED EMISSIONS RADIATED NOISE

Radiated emissions are measured at frequencies in excess of


30 MHz. RS-232 outputs designed for operation at high baud
DUT
rates while driving cables can radiate high frequency EM energy.
TO
The reasons already discussed that cause conducted emissions ADJUSTABLE RECEIVER
TURNTABLE
can also be responsible for radiated emissions. Fast RS-232 out- ANTENNA
put transitions can radiate interference, especially when lightly
loaded and driving unshielded cables. Charge pump devices are
also prone to radiating noise due to the high frequency oscillator
and high voltages being switched by the charge pump. The Figure 12. Radiated Emissions Test Setup
move towards smaller capacitors in order to conserve board
space has resulted in higher frequency oscillators being employed
80
in the charge pump design. This has resulted in higher levels of
emission, both conducted and radiated. 70

The RS-232 outputs on the ADM202E products feature a 60


controlled slew rate in order to minimize the level of radiated
emissions, yet are fast enough to support data rates up to 50
230 kBaud.

dBV
40 LIMIT
Figure 13 shows a plot of radiated emissions vs. frequency. This
shows that the levels of emissions are well within specifications 30

without the need for any additional shielding or filtering compo- 20


nents. The ADM202E was operated at maximum baud rates and
configured as in a typical RS-232 interface. 10

Testing for radiated emissions was carried out in a shielded 0


START 30.0MHz STOP 200.0MHz
anechonic chamber.
Figure 13. ADM202E Radiated Emissions Plot

–10– REV. B
ADM202E/ADM1181A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

SOIC (Wide) Package TSSOP Package


(R-16W) (RU-16)

0.4133 (10.50) 0.201 (5.10)

C00066–0–2/01 (rev. B)
0.3977 (10.00) 0.193 (4.90)

16 9 16 9
0.2992 (7.60) 0.177 (4.50)
0.2914 (7.40) 0.169 (4.30)
0.4193 (10.65) 0.256 (6.50)
1 8
0.3937 (10.00) 0.246 (6.25)
1 8

PIN 1 PIN 1
0.050 (1.27) 0.1043 (2.65) 0.0291 (0.74)
BSC 0.0926 (2.35)  45 0.006 (0.15) 0.0433 (1.10)
0.0098 (0.25) MAX
0.002 (0.05)

8 8
0.0118 (0.30) 0.0192 (0.49) SEATING 0 0.0500 (1.27) 0.0256 (0.65) 0.0118 (0.30) 0 0.028 (0.70)
0.0125 (0.32) SEATING 0.0079 (0.20)
0.0040 (0.10) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.020 (0.50)
0.0091 (0.23) 0.0157 (0.40) PLANE 0.0035 (0.090)

SOIC (Narrow) Package DIP Package


(R-16N) (N-16)

0.3937 (10.00) 0.840 (21.34)


0.3859 (9.80) 0.745 (18.92)

16 9 0.280 (7.11)
16 9
0.1574 (4.00) 0.2440 (6.20) 1 8 0.240 (6.10)
0.1497 (3.80) 1 8 0.2284 (5.80) 0.325 (8.25)
PIN 1 0.300 (7.62)
0.060 (1.52)
0.015 (0.38) 0.195 (4.95)
PIN 1 0.0688 (1.75) 0.0196 (0.50) 0.210 (5.33)
x 45° MAX 0.130 0.115 (2.93)
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10) 0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
8° 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
(2.54) PLANE
0.0500 0.0192 (0.49) 0.014 (0.356)
SEATING (1.27) 0.0099 (0.25)
0° 0.0500 (1.27) BSC 0.045 (1.15)
PLANE BSC 0.0138 (0.35)
0.0075 (0.19) 0.0160 (0.41)

ADM202E/ADM1181A–Revision History
Location Page
Data Sheet changed from REV. B to REV. B.
PRINTED IN U.S.A.
Deletion of one ESD Rating in ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Removal of one column in Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

REV. B –11–
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.

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