SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

D Organization . . . 65 536 by 16 Bits J PACKAGE

( TOP VIEW )
D Single 5-V Power Supply
D Operationally Compatible With Existing VPP 1 40 VCC
E 2 39 PGM
Megabit EPROMs
DQ15 3 38 NC
D 40-Pin Dual-In-Line Package and 44-Lead DQ14 4 37 A15
Plastic Leaded Chip Carrier DQ13 5 36 A14
D All Inputs / Outputs Fully TTL Compatible DQ12 6 35 A13
D ±10% VCC Tolerance DQ11 7 34 A12
DQ10 8 33 A11
D Maximum Access / Minimum Cycle Time DQ9 9 32 A10
’27C/PC210A-10 100 ns DQ8 10 31 A9
GND† 11 30 GND†
’27C/ PC210A-12 120 ns
DQ7 12 29 A8
’27C/ PC210A-15 150 ns 13 28
DQ6 A7
’27C/ PC210A-20 200 ns DQ5 14 27 A6
’27C/ PC210A-25 250 ns DQ4 15 26 A5
D 16-Bit Output For Use in DQ3 16 25 A4
DQ2 17 24 A3
Microprocessor-Based Systems
DQ1 18 23 A2
D Very High-Speed SNAP! Pulse DQ0 19 22 A1
Programming G 20 21 A0
D Power-Saving CMOS Technology
D 3-State Output Buffers FN PACKAGE
( TOP VIEW )
D 400-mV Minimum DC Noise Immunity With

DQ13
DQ14
DQ15

PGM
VCC
VPP

A15
A14
Standard TTL Loads

NC

NC
E
D Latchup Immunity of 250 mA on All Input
6 5 4 3 2 1 44 43 42 41 40
and Output Pins 7 A13
DQ12 39
D No Pullup Resistors Required DQ11 8 38 A12
D Low Power Dissipation DQ10 9 37 A11
− Active . . . 275 mW Worst Case DQ9 10 36 A10
DQ8 11 35 A9
− Standby . . . 0.55 mW Worst Case
GND† 12 34 GND†
(CMOS-Input Levels)
NC 13 33 NC
D Temperature Range Options DQ7 14 32 A8
DQ6 15 31 A7
DQ5 16 30 A6
PIN NOMENCLATURE 17 A5
DQ4 29
A0 −A15 Address Inputs 18 19 20 21 22 23 24 25 26 27 28
DQ0 −DQ15 Inputs (programming) / Outputs
A0
A1
A2
A3
A4
DQ3
DQ2
DQ1
DQ0
G
NC

E Chip Enable
G Output Enable
GND Ground
NC No Internal Connection
PGM Program
VCC 5-V Power Supply
VPP 13-V Power Supply‡

† Pins 11 and 30 (J package) and pins 12 and 34 (FN

package) must be connected externally to ground.
‡ Only in program mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


 
!"# $ %&'# "$  (&)*%"# +"#', Copyright  1997, Texas Instruments Incorporated
+&%#$ %! # $('%%"#$ (' #-' #'!$ 
'."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1  "** (""!'#'$,

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

description
The TMS27C210A series are 65 536 by 16-bit (1 048 576-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC210A series are 65 536 by 16-bit (1 048 576-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs ( including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is offered with two choices of
temperature ranges, 0°C to 70°C (JL suffix) and − 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC210A OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing ( FN suffix). The TMS27PC210A is offered with two choices of temperature ranges,
0°C to 70°C ( FNL suffix) and −40°C to 85°C ( FNE suffix). See Table 1.

Table 1. Temperature Range Suffixes

EPROM SUFFIX FOR OPERATING

AND FREE-AIR TEMPERATURE
OTP PROM RANGES
0°C to 70°C − 40°C to 85°C
TMS27C210A-xx JL JE
TMS27PC210A-xx FNL FNE

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), they are ideal for use
in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.

operation
The seven modes of operation for the TMS27C210A and TMS27PC210A are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V), and 12 V on
A9 for signature mode.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

Table 2. Operation Modes

MODE†
FUNCTION OUTPUT PROGRAM
READ STANDBY PROGRAMMING VERIFY SIGNATURE MODE
DISABLE INHIBIT
E VIL VIL VIH VIL VIL VIH VIL
G VIL VIH X VIH VIL X VIL
PGM X X X VIL VIH X X
VPP VCC VCC VCC VPP VPP VPP VCC
VCC VCC VCC VCC VCC VCC VCC VCC
A9 X X X X X X VH‡ VH‡
A0 X X X X X X VIL VIH
CODE
DQ0 −DQ15 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z MFG DEVICE
97 AB
† X can be VIL or VIH.
‡ VH = 12 V ± 0.5 V.

read/output disable
When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins.

latchup immunity
Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/ output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, “Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family”, available through TI Sales Offices.

power down
Active ICC supply current can be reduced from 50 mA to 500 µA by applying a high TTL input on E and to
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.

erasure (TMS27C210A)
Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W•s / cm2. A typical 12-mW/ cm2, filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the
window should be covered with an opaque label.

initializing (TMS27PC210A)
The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed
into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

SNAP! Pulse programming

The TMS27C210A and TMS27PC210A are programmed using the TI SNAP! Pulse programming algorithm
(shown in the flow chart in Figure 1), which can program in a nominal time of seven seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, E = VIL, G = VIH. Data is presented in parallel
(16 bits) on pins DQ0 through DQ15. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
VCC = VPP = 5 V ± 10%.

program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.

program verify
Programmed bits can be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = VIH.

signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. DQ0 −DQ7 contain the
valid codes. All other addresses must be held low. The signature code for these devices is 97AB. A0 low selects
the manufacturer’s code 97 ( Hex), and A0 high selects the device code AB (Hex), as shown in Table 3.

Table 3. Signature Mode

PINS
IDENTIFIER†
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
Manufacturer Code VIL 1 0 0 1 0 1 1 1 97
Device Code VIH 1 0 1 0 1 0 1 1 AB
† E = G = VIL, A9 = VH, A1 −A8 = VIL, A10 −A15 = VIL, VPP = VCC, PGM = VIH or VIL.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

Start

Address = First Location

VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V Program

Mode

Program One Pulse = tw = 100 µs Increment Address

Last No
Address?

Yes
Address = First Location

X=0
Program One Pulse = tw = 100 µs
No

Fail
Increment Verify X=X+1 X = 10?
Address One Byte Interactive
Mode

Pass

No Last
Address?

Yes Yes
VCC = VPP = 5 V ± 0.5 V Device Failed

Compare Fail
All Bytes Final
to Original Verification
Data

Pass

Device Passed

Figure 1. SNAP! Pulse Programming Flowchart

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

logic symbol†
EPROM 65 536 × 16
21
A0 0
22 A∇ 19
A1 DQ0
23 A∇ 18
A2 DQ1
24 A∇ 17
A3 DQ2
25 A∇ 16
A4 DQ3
26 A∇ 15
A5 DQ4
27 A∇ 14
A6 DQ5
28 A∇ 13
A7 0 DQ6
29 A A∇ 12
A8 65 535 DQ7
31 A∇ 10
A9 DQ8
32 A∇ 9
A10 DQ9
33 A∇ 8
A11 DQ10
34 A∇ 7
A12 DQ11
35 A∇ 6
A13 DQ12
36 A∇ 5
A14 DQ13
37 A∇ 4
A15 15 DQ14
A∇ 3
DQ15

2
E [PWR DWN]

&

20
G EN

† This symbol is in accordance with ANSI / IEEE Std 91−1984 and IEC Publication 617−12.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
Operating free-air temperature range (’27C210A-_ _JL, ’27PC210A-_ _FNL) . . . . . . . . . . . . . . 0° C to 70°C
Operating free-air temperature range (’27C210A-_ _JE, ’27PC210A-_ _FNE) . . . . . . . . . . . . − 40° C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

TMS27C/PC210A-10
TMS27C / PC210A-12
TMS27C / PC210A-15
TMS27C / PC210A-20 UNIT
TMS27C / PC210A-25
MIN NOM MAX
Read mode (see Note 2) 4.5 5 5.5
VCC Supply voltage V
SNAP! Pulse programming algorithm 6.25 6.5 6.75
Read mode VCC −0.6 VCC VCC+0.6
VPP Supply voltage V
SNAP! Pulse programming algorithm 12.75 13 13.25
TTL 2 VCC+0.5
VIH High-level dc input voltage V
CMOS VCC − 0.2 VCC+0.5
TTL − 0.5 0.8
VIL Low-level dc input voltage V
CMOS − 0.5 GND+0.2
’27C210A-_ _JL
TA Operating free-air temperature 0 70 °C
’27PC210A-_ _FNL
’27C210A-_ _JE,
TA Operating free-air temperature − 40 85 °C
’27PC210A-_ _FNE
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

electrical characteristics over recommended ranges of operating conditions

PARAMETER TEST CONDITIONS MIN MAX UNIT
IOH = − 20 µA VCC − 0.2
VOH High-level dc output voltage V
IOH = − 2 mA 2.4
IOL = 2.1 mA 0.4
VOL Low-level dc output voltage V
IOL = 20 µA 0.1
II Input current (leakage) VI = 0 V to 5.5 V ±1 µA
IO Output current (leakage) VO = 0 V to VCC ±1 µA
IPP1 VPP supply current VPP = VCC = 5.5 V 10 µA
IPP2 VPP supply current (during program pulse) VPP = 13 V 50 mA
TTL-input level VCC = 5.5 V, E = VIH 500
ICC1 VCC supply current (standby) µA
CMOS-input level VCC = 5.5 V, E = VCC 100
VCC = 5.5 V, E = VIL,
ICC2 VCC supply current (active) tcycle = minimum cycle time, 50 mA
outputs open†
† Minimum cycle time = maximum address access time.

capacitance over recommended ranges of supply voltage and operating free-air

temperature, f = 1 MHz‡
PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT
CI Input capacitance VI = 0 V, f = 1 MHz 8 12 pF
CO Output capacitance VO = 0 V, f = 1 MHz 12 15 pF
‡ Capacitance measurements are made on a sample basis only.
§ Typical values are at TA = 25°C and nominal voltages.

switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
’27C210A-10 ’27C210A-12 ’27C210A-15 ’27C210A-20 ’27C210A-25
TEST ’27PC210A-10 ’27PC210A-12 ’27PC210A-15 ’27PC210A-20 ’27PC210A-25
PARAMETER UNIT
CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Access time from
ta(A) 100 120 150 200 250 ns
address
Access time from
ta(E) 100 120 150 200 250 ns
chip enable
Output enable
ten(G) 55 55 75 75 100 ns
time from G CL = 100 pF,
1 Series 74
Output disable
TTL load,
time from G or E,
tdis Input tr ≤ 20 ns, 0 50 0 50 0 60 0 60 0 60 ns
whichever occurs
Input tf ≤ 20 ns
first¶
Output data valid
time after change
tv(A) of address, E, or 0 0 0 0 0 ns
G, whichever
occurs first¶
¶ Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for tdis except during programming.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER MIN MAX UNIT
tdis(G) Output disable time from G 0 100 ns
ten(G) Output enable time from G 150 ns
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).

timing requirements for programming

MIN NOM MAX UNIT
tw(PGM) Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs
tsu(A) Setup time, address 2 µs
tsu(E) Setup time, E 2 µs
tsu(G) Setup time, G 2 µs
tsu(D) Setup time, data 2 µs
tsu(VPP) Setup time, VPP 2 µs
tsu(VCC) Setup time, VCC 2 µs
th(A) Hold time, address 0 µs
th(D) Hold time, data 2 µs
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

2.08 V

RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)

2.4 V
2V 2V
0.8 V 0.8 V
0.4 V
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.

Figure 2. The ac Testing Output Load Circuit and ac Waveform

VIH
A0 −A15 Addresses Valid
VIL

VIH
E
VIL
ta(E)
VIH
G
VIL
tdis
ten(G)
tv(A)
ta(A)
VOH
DQ0 −DQ15 Hi-Z Output Valid Hi-Z
VOL

Figure 3. Read-Cycle Timing

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

PROGRAMMING INFORMATION
Verify
Program
VIH
Address
A0 −A15 Address Stable
N+1
VIL
tsu(A) th(A)
VIH / VOH
Data-Out
DQ0 −DQ15 Data-In Stable
Valid
VIL / VOL
tsu(D) tdis(G)†
VPP‡
VPP
VCC
tsu(VPP)

VCC‡
VCC
VCC
tsu(VCC)
VIH
E
VIL
th(D)
tsu(E)
VIH
PGM
tsu(G) VIL
tw(PGM) ten(G)†
VIH
G
VIL

† tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
‡ 13-V VPP and 6.5-V VCC for SNAP! Pulse programming.

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane
0.004 (0,10)

0.180 (4,57) MAX

D
0.120 (3,05)
D1 0.090 (2,29)
0.020 (0,51) MIN
3 1 19

0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2

E E1

D2 / E2

8 14

0.050 (1,27) 0.021 (0,53)

9 13 0.013 (0,33)
0.008 (0,20) NOM 0.007 (0,18) M

NO. OF D/E D1 / E1 D2 / E2
PINS
** MIN MAX MIN MAX MIN MAX

20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)

28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)

44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)

52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)

68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005 / B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PIN SHOWN

24 13

1 12
0.065 (1,65) Lens Protrusion
0.010 (0,25) MAX
0.045 (1,14)
0.090 (2,29) 0.175 (4,45)
0.060 (1,53) A
0.140 (3,56)
0.018 (0,46) MIN

Seating Plane

0°−ā 10°

0.125 (3,18) MIN

0.022 (0,56)
0.100 (2,54)
0.014 (0,36) 0.012 (0,30)
0.008 (0,20)

PINS** 24 28 32 40
DIM NARR WIDE NARR WIDE NARR WIDE NARR WIDE
MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
A
MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
B
MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
C
MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)

4040084 / B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

D Organization . . . 65 536 by 16 Bits J PACKAGE

( TOP VIEW )
D Single 5-V Power Supply
D Operationally Compatible With Existing VPP 1 40 VCC
E 2 39 PGM
Megabit EPROMs
DQ15 3 38 NC
D 40-Pin Dual-In-Line Package and 44-Lead DQ14 4 37 A15
Plastic Leaded Chip Carrier DQ13 5 36 A14
D All Inputs / Outputs Fully TTL Compatible DQ12 6 35 A13
D ±10% VCC Tolerance DQ11 7 34 A12
DQ10 8 33 A11
D Maximum Access / Minimum Cycle Time DQ9 9 32 A10
’27C/PC210A-10 100 ns DQ8 10 31 A9
GND† 11 30 GND†
’27C/ PC210A-12 120 ns
DQ7 12 29 A8
’27C/ PC210A-15 150 ns 13 28
DQ6 A7
’27C/ PC210A-20 200 ns DQ5 14 27 A6
’27C/ PC210A-25 250 ns DQ4 15 26 A5
D 16-Bit Output For Use in DQ3 16 25 A4
DQ2 17 24 A3
Microprocessor-Based Systems
DQ1 18 23 A2
D Very High-Speed SNAP! Pulse DQ0 19 22 A1
Programming G 20 21 A0
D Power-Saving CMOS Technology
D 3-State Output Buffers FN PACKAGE
( TOP VIEW )
D 400-mV Minimum DC Noise Immunity With

DQ13
DQ14
DQ15

PGM
VCC
VPP

A15
A14
Standard TTL Loads

NC

NC
E
D Latchup Immunity of 250 mA on All Input
6 5 4 3 2 1 44 43 42 41 40
and Output Pins 7 A13
DQ12 39
D No Pullup Resistors Required DQ11 8 38 A12
D Low Power Dissipation DQ10 9 37 A11
− Active . . . 275 mW Worst Case DQ9 10 36 A10
DQ8 11 35 A9
− Standby . . . 0.55 mW Worst Case
GND† 12 34 GND†
(CMOS-Input Levels)
NC 13 33 NC
D Temperature Range Options DQ7 14 32 A8
DQ6 15 31 A7
DQ5 16 30 A6
PIN NOMENCLATURE 17 A5
DQ4 29
A0 −A15 Address Inputs 18 19 20 21 22 23 24 25 26 27 28
DQ0 −DQ15 Inputs (programming) / Outputs
A0
A1
A2
A3
A4
DQ3
DQ2
DQ1
DQ0
G
NC

E Chip Enable
G Output Enable
GND Ground
NC No Internal Connection
PGM Program
VCC 5-V Power Supply
VPP 13-V Power Supply‡

† Pins 11 and 30 (J package) and pins 12 and 34 (FN

package) must be connected externally to ground.
‡ Only in program mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


 
!"# $ %&'# "$  (&)*%"# +"#', Copyright  1997, Texas Instruments Incorporated
+&%#$ %! # $('%%"#$ (' #-' #'!$ 
'."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1  "** (""!'#'$,

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

description
The TMS27C210A series are 65 536 by 16-bit (1 048 576-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC210A series are 65 536 by 16-bit (1 048 576-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs ( including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is offered with two choices of
temperature ranges, 0°C to 70°C (JL suffix) and − 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC210A OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing ( FN suffix). The TMS27PC210A is offered with two choices of temperature ranges,
0°C to 70°C ( FNL suffix) and −40°C to 85°C ( FNE suffix). See Table 1.

Table 1. Temperature Range Suffixes

EPROM SUFFIX FOR OPERATING

AND FREE-AIR TEMPERATURE
OTP PROM RANGES
0°C to 70°C − 40°C to 85°C
TMS27C210A-xx JL JE
TMS27PC210A-xx FNL FNE

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), they are ideal for use
in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.

operation
The seven modes of operation for the TMS27C210A and TMS27PC210A are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V), and 12 V on
A9 for signature mode.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

Table 2. Operation Modes

MODE†
FUNCTION OUTPUT PROGRAM
READ STANDBY PROGRAMMING VERIFY SIGNATURE MODE
DISABLE INHIBIT
E VIL VIL VIH VIL VIL VIH VIL
G VIL VIH X VIH VIL X VIL
PGM X X X VIL VIH X X
VPP VCC VCC VCC VPP VPP VPP VCC
VCC VCC VCC VCC VCC VCC VCC VCC
A9 X X X X X X VH‡ VH‡
A0 X X X X X X VIL VIH
CODE
DQ0 −DQ15 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z MFG DEVICE
97 AB
† X can be VIL or VIH.
‡ VH = 12 V ± 0.5 V.

read/output disable
When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins.

latchup immunity
Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/ output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, “Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family”, available through TI Sales Offices.

power down
Active ICC supply current can be reduced from 50 mA to 500 µA by applying a high TTL input on E and to
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.

erasure (TMS27C210A)
Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
exposure time) is 15-W•s / cm2. A typical 12-mW/ cm2, filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the
window should be covered with an opaque label.

initializing (TMS27PC210A)
The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed
into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

SNAP! Pulse programming

The TMS27C210A and TMS27PC210A are programmed using the TI SNAP! Pulse programming algorithm
(shown in the flow chart in Figure 1), which can program in a nominal time of seven seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, E = VIL, G = VIH. Data is presented in parallel
(16 bits) on pins DQ0 through DQ15. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
VCC = VPP = 5 V ± 10%.

program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.

program verify
Programmed bits can be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = VIH.

signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. DQ0 −DQ7 contain the
valid codes. All other addresses must be held low. The signature code for these devices is 97AB. A0 low selects
the manufacturer’s code 97 ( Hex), and A0 high selects the device code AB (Hex), as shown in Table 3.

Table 3. Signature Mode

PINS
IDENTIFIER†
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
Manufacturer Code VIL 1 0 0 1 0 1 1 1 97
Device Code VIH 1 0 1 0 1 0 1 1 AB
† E = G = VIL, A9 = VH, A1 −A8 = VIL, A10 −A15 = VIL, VPP = VCC, PGM = VIH or VIL.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

Start

Address = First Location

VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V Program

Mode

Program One Pulse = tw = 100 µs Increment Address

Last No
Address?

Yes
Address = First Location

X=0
Program One Pulse = tw = 100 µs
No

Fail
Increment Verify X=X+1 X = 10?
Address One Byte Interactive
Mode

Pass

No Last
Address?

Yes Yes
VCC = VPP = 5 V ± 0.5 V Device Failed

Compare Fail
All Bytes Final
to Original Verification
Data

Pass

Device Passed

Figure 1. SNAP! Pulse Programming Flowchart

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

logic symbol†
EPROM 65 536 × 16
21
A0 0
22 A∇ 19
A1 DQ0
23 A∇ 18
A2 DQ1
24 A∇ 17
A3 DQ2
25 A∇ 16
A4 DQ3
26 A∇ 15
A5 DQ4
27 A∇ 14
A6 DQ5
28 A∇ 13
A7 0 DQ6
29 A A∇ 12
A8 65 535 DQ7
31 A∇ 10
A9 DQ8
32 A∇ 9
A10 DQ9
33 A∇ 8
A11 DQ10
34 A∇ 7
A12 DQ11
35 A∇ 6
A13 DQ12
36 A∇ 5
A14 DQ13
37 A∇ 4
A15 15 DQ14
A∇ 3
DQ15

2
E [PWR DWN]

&

20
G EN

† This symbol is in accordance with ANSI / IEEE Std 91−1984 and IEC Publication 617−12.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
Operating free-air temperature range (’27C210A-_ _JL, ’27PC210A-_ _FNL) . . . . . . . . . . . . . . 0° C to 70°C
Operating free-air temperature range (’27C210A-_ _JE, ’27PC210A-_ _FNE) . . . . . . . . . . . . − 40° C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

TMS27C/PC210A-10
TMS27C / PC210A-12
TMS27C / PC210A-15
TMS27C / PC210A-20 UNIT
TMS27C / PC210A-25
MIN NOM MAX
Read mode (see Note 2) 4.5 5 5.5
VCC Supply voltage V
SNAP! Pulse programming algorithm 6.25 6.5 6.75
Read mode VCC −0.6 VCC VCC+0.6
VPP Supply voltage V
SNAP! Pulse programming algorithm 12.75 13 13.25
TTL 2 VCC+0.5
VIH High-level dc input voltage V
CMOS VCC − 0.2 VCC+0.5
TTL − 0.5 0.8
VIL Low-level dc input voltage V
CMOS − 0.5 GND+0.2
’27C210A-_ _JL
TA Operating free-air temperature 0 70 °C
’27PC210A-_ _FNL
’27C210A-_ _JE,
TA Operating free-air temperature − 40 85 °C
’27PC210A-_ _FNE
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

electrical characteristics over recommended ranges of operating conditions

PARAMETER TEST CONDITIONS MIN MAX UNIT
IOH = − 20 µA VCC − 0.2
VOH High-level dc output voltage V
IOH = − 2 mA 2.4
IOL = 2.1 mA 0.4
VOL Low-level dc output voltage V
IOL = 20 µA 0.1
II Input current (leakage) VI = 0 V to 5.5 V ±1 µA
IO Output current (leakage) VO = 0 V to VCC ±1 µA
IPP1 VPP supply current VPP = VCC = 5.5 V 10 µA
IPP2 VPP supply current (during program pulse) VPP = 13 V 50 mA
TTL-input level VCC = 5.5 V, E = VIH 500
ICC1 VCC supply current (standby) µA
CMOS-input level VCC = 5.5 V, E = VCC 100
VCC = 5.5 V, E = VIL,
ICC2 VCC supply current (active) tcycle = minimum cycle time, 50 mA
outputs open†
† Minimum cycle time = maximum address access time.

capacitance over recommended ranges of supply voltage and operating free-air

temperature, f = 1 MHz‡
PARAMETER TEST CONDITIONS MIN TYP§ MAX UNIT
CI Input capacitance VI = 0 V, f = 1 MHz 8 12 pF
CO Output capacitance VO = 0 V, f = 1 MHz 12 15 pF
‡ Capacitance measurements are made on a sample basis only.
§ Typical values are at TA = 25°C and nominal voltages.

switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
’27C210A-10 ’27C210A-12 ’27C210A-15 ’27C210A-20 ’27C210A-25
TEST ’27PC210A-10 ’27PC210A-12 ’27PC210A-15 ’27PC210A-20 ’27PC210A-25
PARAMETER UNIT
CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Access time from
ta(A) 100 120 150 200 250 ns
address
Access time from
ta(E) 100 120 150 200 250 ns
chip enable
Output enable
ten(G) 55 55 75 75 100 ns
time from G CL = 100 pF,
1 Series 74
Output disable
TTL load,
time from G or E,
tdis Input tr ≤ 20 ns, 0 50 0 50 0 60 0 60 0 60 ns
whichever occurs
Input tf ≤ 20 ns
first¶
Output data valid
time after change
tv(A) of address, E, or 0 0 0 0 0 ns
G, whichever
occurs first¶
¶ Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for tdis except during programming.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER MIN MAX UNIT
tdis(G) Output disable time from G 0 100 ns
ten(G) Output enable time from G 150 ns
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).

timing requirements for programming

MIN NOM MAX UNIT
tw(PGM) Pulse duration, program SNAP! Pulse programming algorithm 95 100 105 µs
tsu(A) Setup time, address 2 µs
tsu(E) Setup time, E 2 µs
tsu(G) Setup time, G 2 µs
tsu(D) Setup time, data 2 µs
tsu(VPP) Setup time, VPP 2 µs
tsu(VCC) Setup time, VCC 2 µs
th(A) Hold time, address 0 µs
th(D) Hold time, data 2 µs
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

2.08 V

RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)

2.4 V
2V 2V
0.8 V 0.8 V
0.4 V
NOTES: A. CL includes probe and fixture capacitance.
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.

Figure 2. The ac Testing Output Load Circuit and ac Waveform

VIH
A0 −A15 Addresses Valid
VIL

VIH
E
VIL
ta(E)
VIH
G
VIL
tdis
ten(G)
tv(A)
ta(A)
VOH
DQ0 −DQ15 Hi-Z Output Valid Hi-Z
VOL

Figure 3. Read-Cycle Timing

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

PROGRAMMING INFORMATION
Verify
Program
VIH
Address
A0 −A15 Address Stable
N+1
VIL
tsu(A) th(A)
VIH / VOH
Data-Out
DQ0 −DQ15 Data-In Stable
Valid
VIL / VOL
tsu(D) tdis(G)†
VPP‡
VPP
VCC
tsu(VPP)

VCC‡
VCC
VCC
tsu(VCC)
VIH
E
VIL
th(D)
tsu(E)
VIH
PGM
tsu(G) VIL
tw(PGM) ten(G)†
VIH
G
VIL

† tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
‡ 13-V VPP and 6.5-V VCC for SNAP! Pulse programming.

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane
0.004 (0,10)

0.180 (4,57) MAX

D
0.120 (3,05)
D1 0.090 (2,29)
0.020 (0,51) MIN
3 1 19

0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2

E E1

D2 / E2

8 14

0.050 (1,27) 0.021 (0,53)

9 13 0.013 (0,33)
0.008 (0,20) NOM 0.007 (0,18) M

NO. OF D/E D1 / E1 D2 / E2
PINS
** MIN MAX MIN MAX MIN MAX

20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)

28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)

44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)

52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)

68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005 / B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PIN SHOWN

24 13

1 12
0.065 (1,65) Lens Protrusion
0.010 (0,25) MAX
0.045 (1,14)
0.090 (2,29) 0.175 (4,45)
0.060 (1,53) A
0.140 (3,56)
0.018 (0,46) MIN

Seating Plane

0°−ā 10°

0.125 (3,18) MIN

0.022 (0,56)
0.100 (2,54)
0.014 (0,36) 0.012 (0,30)
0.008 (0,20)

PINS** 24 28 32 40
DIM NARR WIDE NARR WIDE NARR WIDE NARR WIDE
MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
A
MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
B
MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
C
MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)

4040084 / B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997

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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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