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Three-dimensional integrated circuits

Article  in  Ibm Journal of Research and Development · August 2006

DOI: 10.1147/rd.504.0491 · Source: IEEE Xplore

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 Three-dimensional A. W. Topol
D. C. La Tulipe, Jr.
integrated circuits L. Shi
D. J. Frank
Three-dimensional (3D) integrated circuits (ICs), which contain K. Bernstein
multiple layers of active devices, have the potential to dramatically S. E. Steen
enhance chip performance, functionality, and device packing density. A. Kumar
They also provide for microchip architecture and may facilitate G. U. Singco
the integration of heterogeneous materials, devices, and signals. A. M. Young
However, before these advantages can be realized, key technology K. W. Guarini
challenges of 3D ICs must be addressed. More specifically, the M. Ieong
processes required to build circuits with multiple layers of
active devices must be compatible with current state-of-the-art
silicon processing technology. These processes must also show
manufacturability, i.e., reliability, good yield, maturity, and
reasonable cost. To meet these requirements, IBM has introduced a
scheme for building 3D ICs based on the layer transfer of functional
circuits, and many process and design innovations have been
implemented. This paper reviews the process steps and design aspects
that were developed at IBM to enable the formation of stacked device
layers. Details regarding an optimized layer transfer process are
presented, including the descriptions of 1) a glass substrate process to
enable through-wafer alignment; 2) oxide fusion bonding and wafer
bow compensation methods for improved alignment tolerance during
bonding; 3) and a single-damascene patterning and metallization
method for the creation of high-aspect-ratio (6:1 , AR , 11:1)
contacts between two stacked device layers. This process provides
the shortest distance between the stacked layers (,2 lm), the
highest interconnection density (.108 vias/cm2), and extremely
aggressive wafer-to-wafer alignment (submicron) capability.

Introduction: Challenges of CMOS technology necessitating the replacement of bulk MOSFETs with
The development of IC technology is driven by the need novel CMOS device structures. Silicon-on-insulator
to increase both performance and functionality while (SOI) technology, which offers higher performance
reducing power and cost. This goal has been achieved by because of junction capacitance reduction and lack of
the use of two solutions: 1) scaling devices and associated body effects, has been developed [4]. Further, scaling
interconnecting wire [1] through the implementation of SOI thickness reduces short-channel effect and
of new materials and processing innovations, and 2)
eliminates most of the leakage paths [5], but it rapidly
introducing architecture enhancements [2] to reconfigure
degrades mobility, thereby limiting the extent of SOI
routing, hierarchy, and placement of critical circuit
building blocks. Challenges associated with process
scaling [6]. Strained Si channels offering mobility
scaling and architectural scaling are discussed in the enhancement have been demonstrated [7], but future
following paragraphs. structures which combine the benefit of SOI and
strained silicon technology may have to be

Front-end-of-line (FEOL) scaling: As accelerated constructed by using device geometry and
gate-length scaling has pushed the gate-dielectric technology developed for double-gate FETs [8]
and junction technology to its physical limits, and FinFETs [9]. A key challenge for these novel
continued conventional bulk-Si CMOS device scaling integration and device options is the increasing
of the oxide thickness, junction depth, and depletion difficulty in their fabrication and the incompatibility
width [3] has become quite difficult, possibly of various designs with planar structures [10].

Copyright 2006 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) each
reproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions,
of this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any
other portion of this paper must be obtained from the Editor. 491
0018-8646/06/$5.00 ª 2006 IBM

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 Benefits of 3D integrated circuits
1–10
One of several promising solutions being explored is the
metal 3D integration and packaging technology (also known as
layers Device layer 2 ⱖ2 layers
Vertical interconnect of active
vertical integration), in which multiple layers of active
devices devices are stacked with vertical interconnections between
the layers (Figure 1) to form 3D integrated circuits (ICs)
Single
device Device layer 1 [16]. Later sections present a detailed description of this
layer Silicon technology. Even in the absence of continued device
scaling, 3D ICs provide potential performance advances,
since each transistor in a 3D IC can access a greater
Figure 1 number of nearest neighbors, and each circuit functional
Schematic diagram of three-dimensional integrated circuit (3D IC) block has higher bandwidth. Other benefits of 3D ICs
showing two stacked device layers with their corresponding include improved packing density, noise immunity,
metallization levels and inter-device-layer connections (vertical improved total power due to reduced wire length/lower
interconnects). Reprinted from [16] with permission; ©2002 IEEE.
capacitance, superior performance, and the ability to
implement added functionality. These features are
described in more detail in the following sections.

Back-end-of-line (BEOL) scaling: CMOS scaling
trends result in a design in which billions of Power
transistors are interconnected by tens of kilometers of Initial analyses of investigated 3D wire-length reduction
wires packed into an area of square centimeters [11]. [11] showed that 3D integration indeed provides a smaller
Wires deliver power to each transistor and provide a wire-length distribution, with the largest effect associated
low-skew synchronizing clock. However, increasing with the longest paths. These shorter wires will decrease
wiring complexity and challenges in improving wire the average load capacitance and resistance and decrease
delay to keep up with intrinsic gate delay are key the number of repeaters needed for long wires. Since
issues for BEOL technology [12]. Although many interconnect wires with their supporting repeaters
new materials and processes have been introduced consume a significant portion of total active power, the
to meet metal conductivity and dielectric permittivity reduced average interconnect length in 3D IC, compared
requirements, it is expected that interconnect with that of 2D counterparts, will improve the wire
metallization of long wires with resulting RC delay, efficiency (;15%) and significantly reduce total active
low yield, and high cost of fabrication will limit the power by more than 10% [17].
performance of ICs beyond the 45-nm-technology
node [13]. Noise

Architecture: The conventional planar IC has limited The shorter interconnects and consequent reduction of
floorplanning choices, and these in turn limit system load capacitance in 3D ICs will reduce the noise due to
architecture performance improvements. This leads simultaneous switching events. The shorter wires will also
to issues related to the interconnect loading in the have lower wire-to-wire capacitance, resulting in less
network of long wires and the need for signal noise coupling between signal lines. The shorter global
repeaters used for clock distribution. However, wires with reduced numbers of repeaters should also have
repeaters are responsible for a significant fraction of less noise and less jitter, providing better signal integrity.
the total power consumption on a chip. Also, existing
two-dimensional (2D) IC designs may not be suitable Logical span
for the integration of disparate signals (digital, Because MOSFET fan-out is limited to a fixed amount of
analog, or rf) or technologies (SOI, SiGe, capacitive gain per cycle, the increasing intrinsic gate load
heterojunction bipolar transistors or HBTs, GaAs, is significantly constrained by extrinsic load capacitance
etc.) [14]. In addition, because of IC scaling trends, (wires). Since 3D IC provides a lower wiring load, it
traditional computer-aided-design (CAD) practices makes it possible to drive a greater number of logic gates
and tools have required an increased number of (fan-out) [18].
design cycles, raising time to market and cost per chip
function [15]. Therefore, a solution is required that Density
both alleviates the interconnect bottleneck and In three dimensions, active devices can be stacked and the
provides new avenues for the advanced device and size of a chip footprint can be reduced. This added
492 architectural innovation. dimension to the conventional two-dimensional device

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006
layout improves the transistor packing density, since
p p
circuit components can be stacked on top of each other,
as in Figure 2, where an n-FET is placed over a p-FET.
When the total layout area (the sum of the device area
and the metal routing area) is compared for 2D and 3D 2D inverter
standard cells with different inverter designs, a 30% areal 3D inverter
benefit for the 3D cells can be achieved [18]. The ability to
stack circuit elements, thus shrinking the footprint and
potentially reducing the volume and/or weight of a chip, n

is of great interest for wireless, portable electronics, and

military applications. n
Higher-density and hence higher-speed SRAM circuits
can also be created. For example, the pull-up p-MOS Interlevel contacts
devices could be stacked over the n-MOS in a 3D
approach to save device area. However, since metal
routing occupies a large portion of the total layout area,
the total cell area reduction will depend strongly on the
chip architecture and the metal routing design. Successful
Figure 2
stacked CMOS SRAM cell technology has been reported
[19], but its extendibility is limited by extremely tight Layout designs of the 2D and 3D inverters with fan-in equal to 1,
showing large (30%) areal gain for the 3D case. Reprinted from
alignment tolerance requirements for interlayer contacts.
[18] with permission; ©2003 IEEE.

Performance
3D technology enables the memory arrays to be placed
above or under logic circuitry, resulting in an increased
bandwidth and thus a significant performance gain in 1.6
communication between memory and microprocessor. In
particular, as the amount of on-chip memory increases Four layers
1.5
Relative performance

(i.e., the majority of the chip will soon be occupied by

memory), the latency of the path from logic to memory 1.4 Three layers
becomes a limiting factor in the logic-memory system.
The ability to stack logic and memory has been 1.3
Two layers
demonstrated [20].
1.2
In addition, one can determine maximum system
performance as a function of the number of device layers.
1.1
Maximum performance depends on power dissipation 0.0001 0.001 0.01 0.1 1
constraints. In the presence of power constraints, there Total power in process core (W)
are global technology scaling optima that yield maximum
computation (for example, if devices are scaled too far, Figure 3
leakage consumes too much of the power). Simple models Relative performance for different numbers of stacked layers vs.
of device and system dependencies have been developed, the pre-set total power in the process core, showing performance
and optimizations have been performed. These layering increase as the square root of the number of layers stacked.
models ignore the impact of blockage due to signals Reprinted from [16] with permission; ©2002 IEEE.
passing through a device layer. As depicted in Figure 3,
the results show significant potential advantage for 3D
integration, with performance increasing roughly as the
square root of the number of circuit layers that are Functionality
stacked. For these data points, device characteristics 3D integration will allow the incorporation of new
(such as Vdd, VT, tox, gate length, mean FET width, wire elements that are currently prohibited by conventional
half-pitch, and repeater spacing) have all been optimized planar technology; it will enable the implementation
for maximum performance [21], where performance is of related design flexibility, including new system
calculated as Performance ¼ total number of logic architectures. Its primary application is the combination
switching events per second in a processor core. of dissimilar technologies (memory, logic with extension 493

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 accuracy requirements when compared with 3D ICs.
Interlayer via density (no. of vias per mm2) Hence, a key process technology element being optimized
100,000
for 3D IC is a methodology for higher-density, smaller-
dimension interlayer connections. Chip-to-chip and chip-
10,000 to-wafer methods have been utilized to accomplish this
goal and are discussed in sections that follow.
1,000
Wafer-scale fabrication
A wafer-level stacking of 3D ICs potentially enables
100 a more cost-effective solution than the chip-stacking
techniques. 3D IC wafer-scale technology (currently a
200-mm and soon a 300-mm option) has the advantage
Transistor Macro Unit Core
level level level level of potentially offering increased design flexibility, since
0.25-␮m via 0.75-␮m via 2.0-␮m via 4.0-␮m via
3D design partitioning level

Figure 4
Schematic diagrams of applications for 3D integration based on
3D partitioning level and the required interlayer via density.
(Personal communication with R. Puri, IBM Research Division,
2005.)

to rf, analog, optical, and microelectromechanical (a)

systems) to create hybrid circuits [22].

3D IC fabrication technology
3D IC fabrication technology can be accomplished by the
implementation of diverse processing sequences. The
simplest way to distinguish among various methods
is by differentiating between chip-level and wafer-level
processing during the layering of key circuit components.
Then the process can be further differentiated by
(b)
determining whether the layer stacking was done using
a face-to-face or face-to-back approach. A detailed
description of some of the most promising 3D assembly
methods is presented in next few subsections.

Chip stacking
3D stacking technology was established for packaging
[17] and focused mainly on chip-stacking methods. Today
many 3D packaging systems are manufactured, but high-
density memory modules are a key application [23]. (c)
Typically a 3D package stacks bare dies or multichip
modules (MCMs), securing the full chips by using epoxy
or glues and creating electrical connections by wire- Figure 5
bonding techniques. Novel 3D packages utilize peripheral Schematic diagrams of assembled 3D IC structures; dashed line
interconnections that are several millimeters long [24], but indicates bonded interface: (a) SOI-based face-to-back process
higher interconnect density with shorter links (hundreds with closely coupled layers; (b) face-to-face bonding (avoids need
for glass substrate and achieves high-density connections between
of microns) between stacked layers has also been ICs); (c) face-to-back process with some Si remaining and deep
demonstrated by incorporating conducting vertical vias formed between the device layers. Reprinted from [29] with
through-hole vias across the chip [23]. 3D packaging has permission; ©2004 IEEE.
494 relaxed interconnect pattern geometry and alignment

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006
Table 1 Technology features associated with assembled 3D IC structures from Figure 5.

Process feature (a) SOI-based face-to-back process (b) Face-to-face process (c) Face-to-back process

Bonding medium Fusion or adhesive Cu–Cu Cu–Cu

Distance between device layers Smallest Middle Largest
Glass substrate needed Yes No Yes
Alignment required Aggressive (sub-lm) Few lm More relaxed
Minimum via pitch Very tight (;0.4 lm) ;10 lm 20–50 lm
8 2 6 2
Interlayer via density Very high (;10 /cm ) High (;10 /cm ) Lower
Suitability for SOI vs. bulk wafer SOI Either Either
Chip vs. wafer bonding Wafer/wafer only Either Either
Directly extendable to .2 layers Yes No Yes
Connection to package Standard Deep via Standard

many key processing steps have not been developed at the alignment tolerances, the integrity of contacts between
die level. There are two primary schemes for wafer-scale device layers, and high process reliability [16].
integration of 3D circuits: ‘‘bottom-up’’ and ‘‘top-down’’
fabrication. 3D IC stacking
As shown in Figure 4, 3D IC structures may also be
Bottom-up wafer-scale fabrication characterized according to the parts of the circuit design
In the bottom-up approach, the layering process is that are layered. More specifically, the 3D integration
sequential and may not require wafer stacking. More can be application-specific, and conceptually it can be
specifically, the bottom-most layer is first created using partitioned as stacking layers of devices, circuits, macros,
standard CMOS technology, followed by the formation circuit functional units, or chips. As depicted in Figure 4,
of a second Si layer, and device fabrication on the second depending on 3D application or partition level, a specific
layer. Additional layers can be added on the top in a input/output (I/O) or interlayer via density is achievable.
similar fashion. The subsequent Si layers are fabricated Further, depending on the position of the top of the
without additional wafer stacking using solid-phase second layer with respect to the top of the first layer after
crystallization [20], the implementation of seeding agents stacking, the process can be described as ‘‘face-to-face’’ if
such as germanium or nickel [25], lateral overgrowth [26], the two tops are facing each other, or ‘‘face-to-back’’ if
or the implementation of wafer-bonding techniques [27] they are not. The most promising methods for creating
to provide a new Si substrate. The latter methods provide 3D ICs using face-to-face and face-to-back options are
single-crystal silicon and result in improved device quality depicted in Figure 5, and their assembly technology
in comparison with the first method [28]. However, features are listed in Table 1. In general, these options can
thermal budget constraints, facilitated to maintain good be used to build chip-to-chip, wafer-to-wafer, and chip-
performance in the underlying IC layers, are a concern to-wafer 3D ICs, but a specific process flow may be easier
for all of these technologies. for a particular chip- or wafer-level technology, and
it is often driven by a specific application.
Top-down wafer-scale fabrication Figure 5(a) shows a structure in which the distance
In the top-down method, multiple 2D IC circuits can between device layers is minimized by removing the entire
be fabricated in parallel and then ‘‘assembled’’ to form Si substrate between the layers. Bonding between the
3D IC [16]. Such an approach enables the performance device layers is achieved through blanket dielectric fusion
optimization of each layer and its functional verification bonding or the use of an adhesive interlayer, after
prior to stacking, and results in acceptable yield and which interlayer electrical connections are formed [29].
lower manufacturing cost. It is particularly attractive for Figure 5(b) shows the face-to-face bonding option, which
applications in which layers of disparate technologies are is effective for creating high-density Cu–Cu bonded links
closely stacked. Key process challenges of the top-down between layers but requires deep vias for bringing signals
3D IC technology include high-quality, low-temperature out to the package [30]. The structure in Figure 5(c)
bonding (,4008C), as back-end materials (metals and typically has the largest interlayer via dimensions and the
low-k) may already be a part of the structure, tight lowest via density, along with the most relaxed alignment 495

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 Key 3D IC technology challenges
Glass Independent of the final 3D IC structure, the assembly
method always involves the integration of four key
technology areas: thinning of the wafers, interdevice-
layer alignment, bonding, and interlayer contact
Circuit patterning. An additional challenge in achieving high-
layer 1 density I/O signal through the stack layers arises from
• Attach circuit to glass substrate thermal mismatch between the bonded layers, affecting
• Remove original substrate alignment tolerance. Also, thermal dissipation of high-
performance CMOS devices is already a concern in 2D
ICs; for 3D circuits, heat spreading and self heating
G la ss
become critical issues. All of these 3D IC integration
challenges require new material and process innovations
[29]; the following sections of this paper discuss related
IBM solutions.

Wafer thinning
Techniques based on mechanical grinding and polishing
Circuit layer 2 and plasma or wet etching have been demonstrated
to reliably thin 200-mm silicon wafers to ;20-lm
• Align and bond top circuit to bottom circuit
thicknesses. To facilitate the removal of bulk Si, the
prominent feature of most IBM 3D IC work is the use of
SOI and glass substrates. The buried oxide layer (BOX)
serves as an etch stop for substrate thinning, enabling the
use of high-performance state-of-the-art IC technology.
More specifically, the BOX in SOI wafers provides a
selective etch stop for the uniform removal of the Si
3D IC
substrate; combined with the use of a glass substrate, it
• Remove glass substrate and adhesives
enables improved alignment capabilities (Figure 6). Both
• Form vertical interconnects features greatly simplify the layer-transfer process,
providing a means of obtaining the shortest distance
between devices. The final ‘‘decal’’ structure on a glass
Figure 6 carrier has all of the bulk Si removed; only the device
Schematic diagrams of IBM assembly process, which uses layer layer with its metallization levels remains, making the
transfer methodology to fabricate 3D ICs. Reprinted from [16] stack transparent and hence enabling the ‘‘through-
with permission; ©2002 IEEE. wafer’’ alignment process.

Alignment
Standard alignment methodology allows both front-side
tolerances [31]. The choice of structure and fabrication (through-wafer) and back-side alignment strategies. A
method depends on the specific goal and application of primary challenge for future high-density 3D ICs is the
the 3D IC technology. requirement for high (submicron) alignment tolerances
The IBM 3D assembled structure [Table 1, column (a)] to facilitate higher-level circuit designs. As tested using
is described as having the shortest distance between current available commercial alignment tools, 3 sigma
stacked device layers, the highest interconnection density, value (3r) of ;1.0 lm is the best alignment accuracy
achieved at present using the through-wafer alignment
and extremely aggressive wafer-to-wafer alignment
strategy (glass substrate); it is ;1.0 lm lower than the
requirements. By using IBM methodology, unique n-FET
best results from nontransparent alignment methods
and p-FET layers can be stacked to derive full benefit
(back-side alignment strategies). In addition, for
from the 3D IC process. The process flow to fabricate multiple stacked fully thinned IC device layers, signal
such structures is depicted in Figure 6. With stringent degradation caused by alignment through glass is not
design requirements, the key process optimization expected, and good alignment can easily be achieved. If a
focused on development of state-of-the-art interdevice nontransparent carrier is used, the wavelength-dependent
496 layer connections. signal attenuation through Si may degrade alignment

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006
Table 2 Technology features of various bonding methods.

Critical aspects Oxide fusion bonding Thermo-compression bonding Bonding with adhesive layers

Minimum bonding temperature Room temperature Depends on metal; for Cu 300–4008C Mostly 200–3008C
State of material during bonding Solid May temporarily be viscous Viscous
if metals are alloyed
Special requirements None Good temperature control Good temperature control
Ability to preserve alignment High Low Low
during bonding

accuracy (especially for layers in which remaining Si is chemical–mechanical polishing (CMP) and wet chemical
thicker than 40 lm) [32]. Therefore, the tradeoff between surface treatment is often used prior to bonding to ensure
resolution and transparency in Si poses a real challenge clean and reactive bonding surfaces. Cleaning procedures
for nontransparent wafers which is circumvented by and a post-deposition annealing sequence control bond
the use of a glass for which the CTE is matched to that strength in that they reduce the formation of voids at the
of silicon. bonding interface and must be optimized for every set of
Alignment error due to the difference in the CTE of the bonded materials. More specifically for the oxide-fusion
two layers was minimized in the SOI-based face-to-back bonding process, reduction of the bulk concentration of
process by utilizing oxide-fusion bonding at room –OH groups in oxide (post-deposition) before bonding
temperature. When compared with other bonding enhances the ability of the oxide to absorb byproducts
methods, oxide-fusion bonding shows clear superiority released during the bonding anneal and is critical
(Table 2) because it allows wafer to be tacked in place in obtaining defect-free bonded interfaces [34].
at room temperature during alignment. We have shown Figure 7 shows a cross-sectional TEM image of two
that increased temperature during the post-bonding SOI CMOS device layers bonded by oxide fusion.
anneal strengthens the bond but does not change the Since surface root mean square (RMS) roughness
alignment accuracy [32]. In comparison, since Cu requirements for fusion-bonded surfaces are very
bonding occurs at higher temperatures, extremely good stringent (,1.0 nm) and not easily achieved, many
temperature control must be maintained. Accuracy researchers turn to metal-to-metal bonding options
using bonding with adhesive layers may be degraded, because their RMS roughness specifications can be higher
as adhesives may become viscous during the bonding (,20 nm). However, the drawback of the metal-to-metal
process (temperature and compression cycle), thus low-temperature bonding process is that high pattern
causing alignment patterns to shift. It is important to
density is required to provide high bond strength and
notice that the placement error of state-of-the-art
interface stability during further processing steps.
lithography tools is ,0.02 lm and as such does not
Bonding using polymeric or dielectric glue layers has the
limit alignment precision [33].
least stringent surface planarity requirements, but the use
Large alignment errors may be induced by bowing of
of viscous glue may lead to shifts of these layers during
the wafers. Every processing step changes the bow of a
bonding, thereby limiting alignment tolerance (Table 2).
wafer, sometimes by hundreds of microns [32]. To achieve
optimal alignment results, the bow should be less than Temperatures for all of these bonding approaches must
20 lm for 200-mm wafers during alignment. To maintain be compatible with the thermal constraints of each
this bow target, compensation methods, such as the functional layer, typically ;4508C for post-CMOS FEOL
deposition of counter-pre-stressed films, have been processes. The quality of the bonded interface (bond
implemented prior to the bonding step. Similarly, surface strength, void content, and cleanliness) is critical in
smoothness and local planarity are critical for high- ensuring high yields in the fabrication of interlevel vias,
accuracy alignments, as they affect the ability of the and may be a key factor in bonded device reliability
optics of an alignment tool to focus on alignment mark characteristics.
structures.
Inter-device-layer via fabrication
Bonding For all three structures depicted in Figure 5, the 3D IC
For all types of bonding methods, the quality of the technology requires the formation of high-aspect-ratio
bonded interface depends strongly on surface roughness (AR) vias. The patterning and metallization process for
and cleanliness. In particular, a fusion bonding requires the creation of such vias (e.g., plasma etch, metal fill, and
atomically smooth surfaces. The combination of CMP) must be compatible with other BEOL process 497

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 strategies. All metallization techniques place specific
limitations on the maximum aspect ratio of vias, and may
er thus lead to design limitations with respect to the layout
v ice lay
Top de of active and passive devices on each layer. As stated
earlier, the BOX layer in a SOI substrate is used to
control the transferred device layer thickness to very tight
tolerances. This in turn minimizes the effective aspect
icated
ter fa ce ind ratio of the interwafer via by enabling vertical stacking
o nded in
on of b of the layers spaced only a few microns apart. To utilize
Locati d li ne
e
by dott the full potential of 3D IC, vias of submicron diameter
dimensions are required to be compatible with state-of-
the-art FEOL technology. Hence, the performance and
eventual viability of the 3D ICs built by stacking high-
performance CMOS devices depends critically on
bonding alignment tolerances and on the structural and
electrical integrity of the submicron high-aspect-ratio vias
connecting device layers.
Figure 8 shows our capability to fabricate small
(submicron) interconnecting 3D IC copper-filled vias with
layer
device high aspect ratios (6:1 , AR , 11:1) using a single-
Bottom
damascene process [34]. The via profile, metal liner, and
Cu plating processes were modified only slightly from a
standard back-end-of-line via formation sequence to
achieve proper fill of these high-aspect-ratio structures.
The smallest vias, with a bottom diameter of ;0.14 lm,
Figure 7 height .1.6 lm, and sidewall angle of approximately
Cross-sectional TEM image of two metallized, stacked, and 86 degrees, can be formed on a 0.4-lm pitch, equivalent
oxide-fusion-bonded SOI CMOS device layers. to an extremely high via density of .108 vias per cm2.
Vias with bottom critical dimensions (CDs) of
;0.14 lm 3 0.14 lm correspond to a 0.13-lm CMOS
BEOL technology, but owing to the higher aspect ratio of
the interlevel vias in 3D ICs, their resistance is expected to
(b)
be two to three times higher than that of a typical back-
end via. Measurements of resistance per link of 3D via
chains connecting the first metal level of top and bottom
wafers indicate resistance values of ;2–4 X per link and
good yield for via chains with 100–10,000 vias [32]. This
confirms a successful metallization process through the
bonded interface. Further process optimization is required
to achieve acceptable yields for the longer chain lengths.
One should notice, however, that vias with such high
density would rarely be used because of the space that
would be taken up by active circuitry on the upper device
layer and because of alignment challenges. Nevertheless,
this process illustrates a technique for building ultrahigh-
(c)
density, low-parasitic links between layers using materials
(a) and processes compatible with pre-fabricated circuitry.
The alignment accuracy required to reliably interconnect
the various device circuits fabricated ranges from 0.5 to
Figure 8
2.5 lm and has been successfully achieved.
(a) Polished cross-sectional SEM images of Cu-filled vias with a
6:1 aspect ratio and height ~1.6 ␮m; (b) cleaved SEM image of
isolated via; (c) cleaved SEM image of via structure with diameter
Thermal dissipation
~175 nm and high aspect ratio. Device temperature increase is already a major concern
498 in 2D SOI technology. Because of the poor heat

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006
 Figure 9
3D via-chain diagram for resistance characterization testing 128 interlevel vias (left) and four-via structure (right), providing reliability and
yield learning about high-aspect-ratio 3D interlayer vias. Reprinted from [34] with permission; ©2005 IEEE.

conductivity of the BOX layer, temperature increases

Thinned TEM film
of 80–1208C/mW/lm of width in transistors have been
reported [35]. In addition, a rise in temperature causes
device performance variation and can be very critical for
matching in analog circuits. Also, the performance of the
clock buffer is affected by device temperature increases.
Calculations show that for SOI and bulk devices, every
Bonded interface 0.1 ␮m
108C increase in junction temperature degrades clock
buffer performance by 1.2% and 1.32%, respectively.
Various tests, including pulsed I–V, body-contact diode, Figure 10
polySi resistance, and subthreshold slope methods, have
Cross-sectional TEM image: Oxide-to-oxide fusion-bonded
been used to measure temperature in 2D SOI transistors1 interface showing 2% aerial void density indicating non-optimized
[35–37] and may be utilized to test 3D ICs. The reduced annealing cycle (outgassing of dielectric layers). Insert: transmis-
surface-area-to-volume ratio of 3D structures will sion IR image of bonded 200-mm wafers during bond strength
inevitably lead to increases in power density and measurement shows good bond strength as good surface prepara-
may potentially affect the intrinsic heating of high- tion (cleaning) steps are implemented. Reprinted from [32] with
permission; ©2005 IEEE.
performance chips. Therefore, for some applications the
use of heat-dissipating structures to minimize thermal
gradients and local heating may be required, but it could
affect the interlevel interconnect layout and the design of between bonded layers using materials and processes
the 3D chip [38]. To address all of these 3D IC critical compatible with prefabricated circuitry. As indicated in
issues, a reliable set of verification test structures
Figure 8, a single-damascene process can be used to
(described below) is required.
fabricate such submicron, Cu-filled vias, reliably
connecting top and bottom wafers.
3D IC technology verification test vehicles
Bonding verification test structures
Inter-device-layer via formation verification
test structures Bond strength measurement is a good first-pass method
Figure 9 shows an example of a 3D via-chain structure for of evaluating the quality of the bonded interface, but it
resistance measurements. Via chains go back and forth is not sufficient from a device reliability point of view.
between the first metal levels of the top and bottom For example, TEM-based measurement of the oxide-
wafers. All test pads are at the top wafer. There are two fusion-bonded interface in Figure 10 exhibits a 2%
pads for each end of a via chain to enable four-point aerial void density, but it yields a high bond strength
resistance measurement. These simple test structures can of ;2.2 J/m2 (wedge test depicted in the Figure 10 insert).
show whether low parasitic connections have been made To better evaluate the oxide-fusion-bonded interface,
1
IBM utilizes via-chain test structures with submicron
Edward Nowak, IBM Systems and Technology Group, personal communication,
2003. vias, which are sensitive to leakage induced by a poor 499

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 Another example of an optical alignment test structure,
a Vernier-type structure, is shown in Figure 12(b), where
24
High spec alignment between metal levels in the bottom and top
21
Resistance per link (⍀)

Mean wafers is measured. In this design, Vernier patterns are

18 Maximum placed in both the x and y directions, creating a structure
15 Minimum
for resolving misalignment at 0.18-lm granularity. We
12
have shown nearly perfect ,0.18-lm alignment in both
9 Target spec
Low spec the x and y directions at one particular spot on the wafer
6
[32]. This is a significantly better result than the best
3
reported alignment precision for a 200-mm-diameter
0
wafer to date. One must consider, however, that
Bonded

Bonded

Bonded

Bonded

Bonded

Bonded
Nonbonded

Nonbonded

Nonbonded

Nonbonded

Nonbonded

Nonbonded
alignment across the whole wafer degraded, and by
optical measurements only 65% of the area is within
the required ,2.5-lm alignment precision.
40 80 240 800 2,000 4,000 In addition to optical test structures, we have also
vias vias vias vias vias vias
designed a resistor chain structure to electrically measure
Via-chain length and medium
bonding alignment for 3D stacked circuits [39]. The chain
is fabricated in the bottom wafer, having polySi resistors
Figure 11 along the metal chain. Using an interlevel via, the center
Resistance for interlevel vias through areas with and without terminal from the bottom chain taps into a metal leg in
bonded interface for chains with various via numbers, showing the top wafer track, creating a voltage divider circuit.
that the quality of the bonded interface is good and does not Such a measurement across the wafer generates electrical
degrade the electrical performance of the device-connecting vias maps of layer-to-layer registration. If there is a bonding
for all via-chain lengths tested (resistance within the expected
misalignment, the interlayer via will miss the targeted
value <4 ⍀ per link). Reprinted from [32] with permission; ©2005
IEEE. metal leg in the bottom wafer and land on a different one.
In this design, the mismatch in voltage reading depends
on the misalignment, sizes of metal chain pitch, and
interwafer via dimension. The same approach can also be
interface. Comparisons such as the one shown in used for patterns without added polySi resistance along
Figure 11 measure the resistance of interlevel via chains the metal chain (metal chain method). Figure 13 shows
of various lengths, patterned-through oxide with and typical test results of alignment measurements for testing
without the bonded interface, indicating that the with via sizes of 140 nm, 180 nm, and 250 nm bottom
resistance of the interlevel vias, patterned through critical dimension. The results are very promising, since
the bonded interface, is within the expected value all of the chains tested across the wafer fit within the
required (0.5–2.5 lm) alignment tolerance, and most of
(,4 X per link) for Cu vias having this aspect ratio.
them are ,1 lm. Many other test structures using via-
chain elements can be designed to evaluate alignment.
Verification test structures for bonding alignment
accuracy
Verification test structures for circuit power/thermal
We have developed several techniques to optically and
management
electrically align 3D layers and at the same time be able to
Thermal issues in 3D ICs become severe with increased
measure the resultant overlay error. Two of the optical
power density and thermal resistance from stacking
alignment test structures are shown in Figures 12(a) multiple layers. To evaluate the thermal aspects of the 3D
and 12(b). These structures can be used for automated or vs. 2D ICs, subthreshold slope and polySi resistance
manual bonding alignment and for measurement of the methods are used in 3D macros for self- and spread-
resultant overlay [39]. Figure 12(a) shows an image of a heating measurements. Tests include quantifying self-
standard box-in-box structure. For 3D IC applications, heating in a single transistor and spread-heating through
however, here the outer box comes from the upper device shared Si islands in two-finger transistors (Figure 14).
layer and the inner box from the lower device layer. By While most studies focus on device self-heating, in our
design, the center of the smaller box should be 13.0 lm work we also consider spread-heating, defined as the
away from the edge of the bigger box. Therefore, simply temperature rise of a transistor due to the power
by measuring the difference in distance between the two dissipation of its neighbors in horizontal and vertical
boxes, the alignment accuracy in both the x and y directions. Figure 14(a) shows a 28-finger n-FET
500 directions can be determined. with its center finger connected for four-point resistance

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006
 Structure on the
upper device layer

Structure on the
lower device layer

(a) (b)

Figure 12
(a) 3D box-in-box bonding alignment structure showing nearly perfect alignment (<0.2 ␮ m); (b) top-down optical image of fabricated Vernier
grids. The minimum achievable resolution with a Vernier structure is 0.18 ␮m. Reprinted from [32] with permission; ©2005 IEEE.

Horizontal displacements Vertical displacements

40 40

35 35

30 30
y-axis ( ␮m)

y-axis ( ␮m)

25 Rotational error 25 Magnification error

20 20

15 15

10 10

5 5
5 10 15 20 25 30 35 40 5 10 15 20 25 30 35 40
x-axis ( ␮m) x-axis ( ␮m)
(a) (b)

Figure 13
Electrical maps of layer-to-layer registration for 140-, 180-, and 250-nm vias. Every box is 5 ␮m wide, and green bars signify the size of the
alignment error within this particular chip location. All measurements show less than 2.5-␮m misalignment and indicate potential rotational
and magnification errors. Translation, rotation, magnification, and orthogonality errors can be detected using these maps, and corrections can
be included in the alignment procedure. Center chip indicated in green.

measurement. The rest of the fingers are connected to 0.2 lm, 0.5 lm, 1 lm, and 2.98 lm from one another
drive the transistor with one gate terminal. The transistor on each wafer in a two-wafer 3D chip, as shown in
is laid out in 3D for self-heating measurements in the top Figure 14(b), with the goal of characterizing spread-
and/or bottom wafer. This cell is connected such that the heating effects through STI and 3D BOX with
temperature rise can be measured in both ac and dc interconnect layer. Transistors from top and bottom
operating modes. These test structures have been wafers are connected in such a way that each transistor
fabricated successfully, but the final analysis has not has its own source terminal and all transistors share a
yet been completed. common shorted drain and gate terminal. While the
ANSYS** simulation work suggests that the experiments are being conducted, the common drain and
temperature drops very rapidly in shallow-trench gate terminal must be tied to Vdd. Then, applying Vdd to a
isolation (STI) around an isolated electrically ON source terminal of a transistor turns the transistor OFF,
transistor: 80% within 0.5 lm in 0.13-lm SOI CMOS while applying GND to a source terminal turns it ON.
technology. Therefore, five transistors are separated Thus, one can selectively control the ON/OFF state of 501

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 benefit, the alignment and interconnect dimensions
Force Sense Drain must be of the order of that in the critical layers, and the
gate gate #1
layer transfer process cannot degrade the performance
of the 3D structures. The IBM performance-integrity test
structures include ring oscillators (ROs), single transistors
(FETs), and inverter circuits. We performed a systematic
study of the electrical integrity of high-performance SOI
FETs (of various geometries, down to length L ¼ 55 nm)
and ring oscillator (RO) circuits that were subjected to
the processes required for layer transfer.
In the first testing stage each wafer was put through
Source Sense gate #2
several stages of the layer-transfer process, and electrical
(a)
tests were performed on 25 chips per wafer after each
Sense gates stage for the top device layer transferred onto another
#1 #2 #3 #4 device layer without the interconnection process. Among
other measurements [16], we examined median data for a
particular wafer at three stages: a) after standard CMOS
fabrication; b) after an additional ‘‘simulated’’ lamination
process in which the pressure and temperature required to
adhere the processed wafer to glass are applied without
actually completing the adhesion; c) after full attachment
to glass, an anneal to simulate the thermal processing
required for the second bonding step, and elimination
of the glass plus adhesive removal. Linear drain current,
Idlin, and linear threshold voltage, Vtlin, of long-channel
Source (5-lm) n-FETs were not appreciably altered, indicating
(b)
that these processes do not influence the channel mobility.
The short-channel (65-nm) devices show a slight (,10%)
Figure 14 degradation in Idlin and Vtlin, which we attribute to an
(a) Top-down optical image of a fabricated 28-finger n-FET for
increase in line resistance, since small devices are more
self-heating measurement in 3D ICs; (b) schematic diagram of sensitive to resistance changes [16].
five FETs on each wafer in a 3D chip for measuring temperature Once the process was optimized to preserve the
rise due to spread-heating. Reprinted from [39] with permission. resistance characteristics of the top circuits, special masks
were designed in order to be able to build 3D IC circuits
with functional top and bottom device layers after the
layer transfer process. First, Vtlin and saturation voltage,
a transistor. The ON transistors are used to generate Vtsat, were measured for various FETs on the bottom
heat, while the OFF transistors are used to measure layer of two-layer stacked ICs. Figure 15 shows the Vt
the temperature rise due to spread-heating from the plots for the same six locations on the wafers from
subthreshold slope. The analysis of the measurements the same lot before and after the layer transfer and
from these structures is expected to be complete by the interconnection process. Data indicates that, within the
end of 2006. statistical margins, no degradation due to the 3D IC layer
transfer process has been detected.
Verification test structures for circuit ROs with 59 or 41 ring stages, a 13-stage divider, and
a five-stage output buffer were designed and fabricated.
performance integrity
There are seven macros with 3D ROs and inverters. The
The electrical integrity of devices and circuits must
variation in 3D RO layout is related to the placement of
be preserved during the 3D IC fabrication process.
n-MOS or p-MOS transistors on the top or bottom wafer.
One critical issue is the effect of thermal cycling and The 41-stage RO allows a bonding misalignment of 2 lm
mechanical stresses brought on by the layer transfer with the use of a large landing zone for interwafer vias.
processes during 3D IC fabrication. Another issue relates The 59-stage RO requires strict bonding alignment
to the precise alignment and low parasitic connection (;0.5 lm). In addition, process conditions during the
requirements for stacking and interconnecting the patterning of the gates were tuned to enable the creation
502 multiple device layers. To obtain the optimal circuit of RO devices of various lengths. As depicted in

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006
Figure 16, the lithographic exposure dose affects the
0.7
length of the gate and therefore changes RO delay.
Trends show that a higher dose yields more process
variation, while a lower dose gives better process control. 0.6 Heat n-FET
Overall, the performance of the RO on the bottom layer (mean, standard deviation)
Pre-bond
appears to be unaffected by the layer-transfer process
Vtlin (0.580 ⫾ 0.047)

Vt (V)
[32]. 0.5 Vtsat (0.387 ⫾ 0.024)
Post-bond
Summary and conclusions Vtlin (0.620 ⫾ 0.053)
This paper reviews various 3D integration technologies, Vtsat (0.383 ⫾ 0.035)
0.4
addresses key integration challenges of the 3D ICs, and
describes several optical and electrical test structures
fabricated to verify 3D IC process readiness. A critical 0.3
need exists for a reliable layer-to-layer alignment Pre-bonded Post-bonded
accuracy; several techniques for alignment and overlay
measurements have been presented. The most aggressive
Figure 15
alignment tolerance (0.18 lm) for 3D ICs can be achieved
by implementing a transparent substrate, high-quality Linear threshold and saturation voltage evaluation for various
FETs on the bottom layer pre- and post-layer transfer.
oxide fusion bonding, and bow compensation methods.
Further process improvement of alignment across the
wafer is needed.
We have described issues related to the fabrication
of small, high-aspect-ratio vias suitable for high-density
connections between layers in a 3D IC. Using 0.13-lm 50.00

MOSFET and ring oscillator circuits, it was shown that Average before bonding
BEOL CMOS process techniques can be used to fabricate 40.00 Average after bonding
copper-filled, high-aspect-ratio (.8:1) trenches, providing Process average
the capability to create the smallest (sub-lm-size) vias
Delay (ps)

30.00
as wafer-to-wafer connections. Electrical structures for
testing the reliability of the connecting vias and bonding 20.00
interface have been reviewed. Test structures for
characterizing both self- and spread-heating effects in 3D
10.00
ICs have also been described. This work is a major step
toward the realization of true wafer-level 3D integration
0.00
of high-performance CMOS devices. 5 10 15 20 25 30
Gate exposure dose change (%)
Acknowledgments
The authors are indebted to their many collaborators at Figure 16
IBM for the results described in this paper. In particular,
Delay of RO circuits with different device lengths (variations in
we thank W. Haensch, J. Patel, J. Vichiconti, S. Goma,
exposure conditions during gate lithography) showing device
D. Dimilia, D. Posillico, M. Cobb, S. Medd, M. T. characteristics preserved during the 3D IC process. Reprinted
Robson, E. Duch, M. Farinelli, D. Boyd, D. Neumayer, from [32] with permission; ©2005 IEEE.
C. Wang, R. A. Conti, D. M. Canaperi, L. Deligianni,
K. T. Kwietniak, C. D’Emic, J. Ott, K. Jenkins, R. Joshi,
N. Zamdmer, and Prof. J. Lu from RPI for their
collaborations and useful discussions. Many colleagues Contract Nos. N66001-00-C-8003 and N66001-04-C-
kindly provided data and information for this paper, and 8032.
these are cited individually in the references. The devices
and circuits were fabricated at the IBM Advanced **Trademark, service mark, or registered trademark of ANSYS,
Semiconductor Technology Center, the Materials Inc. in the United States, other countries, or both.
Research Laboratory, and Central Scientific Services;
and we thank the facility management team for strong References
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M. I. Flik, ‘‘Measurement and Modeling of Self-Heating in Member and worked in the area of layer transfer of back-end-of-
SOI NMOSFETS,’’ IEEE Trans. Electron Devices 41, 69 line (BEOL) structures, a novel enabling technology for future low-
(1994). k and/or air-gap-containing interconnect levels. Dr. Topol later
38. A. Rahman and R. Reif, ‘‘Thermal Analysis of Three- joined the Advanced Device group, where she participated in and
Dimensional (3-D) Integrated Circuits (ICs),’’ Proceedings of led a number of semiconductor fabrication technology programs.
the IEEE International Interconnect Conference, 2001, p. 157. She was a project leader for a $4.3M government-funded contract
39. A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, A. M. on three-dimensional integrated circuits and a technical leader for
Young, D. J. Frank, S. E. Steen, J. Vichiconti, D. Posillico, R&D efforts related to the fabrication of middle-of-the-line (MOL)
D. M. Canaperi, S. Medd, R. A. Conti, S. Goma, D. Dimilia, integrated circuits. Her work focused on developing new materials
C. Wang, L. Deligianni, M. A. Cobb, K. Jenkins, A. Kumar, and processes for MOL circuits and their integration in emerging
K. T. Kwietniak, M. Robson, G. W. Gibson, C. D’Emic, E. microelectronic device manufacturing, for which she received an
Nowak, R. Joshi, K. W. Guarini, and M. Ieong, ‘‘Assembly IBM Research Outstanding Technical Contribution Achievement
Technology for Three Dimensional Integrated Circuits,’’ Award in 2004. In February 2002 Dr. Topol joined the IBM STG
Proceedings of the VLSI/ULSI Multilevel Interconnection Alliance strategy group as a Technical Assistant to Dr. Bernard
Conference, 2005, p. III-D. Meyerson (VP, Strategic Alliances and Chief Technologist, STG).
Dr. Topol participated in the 2002 Corporate Technology
Received September 22, 2005; accepted for publication Communication Advisory Council and in 2005 became a member
April 26, 2006; Internet publication August 8, 2006 of the Material Research Community Council.

Douglas C. La Tulipe, Jr. IBM Research Division, Thomas J.

Watson Research Center, P.O. Box 218, Yorktown Heights, New
York 10598 (dlip@us.ibm.com). Mr. La Tulipe is an Advisory
Engineer. Since joining IBM in 1984, he has worked on various
projects including exploratory III–V device fabrication, advanced
lithographic thin-film imaging, and BEOL low-k reactive ion etch
processing. Mr. La Tulipe joined the Silicon Technology group in
2004 and began work on 3D integration technology. He is the
author of several patents and technical papers.

Leathen Shi IBM Research Division, Thomas J. Watson

Research Center, P.O. Box 218, Yorktown Heights, New York
10598 (leashi@us.ibm.com). Dr. Shi received his M.S. degree
in aeronautics and astronautics and his Sc.D. degree in the
field of material engineering from the Massachusetts Institute
of Technology in 1978 and 1981, respectively. Since joining the
IBM Thomas J. Watson Research Center in 1985, he has worked
in a variety of technical areas, including electronic packaging,
interconnects, LCD projection monitors, BEOL, CMOS device
fabrication and integration, and wafer bonding. Currently, Dr.
Shi’s major interests are wafer-level 3D device integration and
wafer (or substrate) engineering for high-performance electronic
devices. He is a member of the IEEE.

David J. Frank IBM Research Division, Thomas J. Watson

Research Center, P.O. Box 218, Yorktown Heights, New York
10598 (djf@us.ibm.com). Dr. Frank received a B.S. degree from the
California Institute of Technology in 1977 and a Ph.D. degree in
physics from Harvard University in 1983. Since graduation, he has
worked at the IBM Thomas J. Watson Research Center, where
he is a Research Staff Member. His studies have included non-
equilibrium superconductivity, III–V devices, and exploring the
limits of scaling of silicon technology. His recent work includes the
modeling of innovative Si devices, analysis of CMOS scaling issues
such as power consumption, discrete dopant effects and short-
channel effects associated with high-k gate insulators, exploring
various nanotechnologies, investigating the usefulness of energy-
recovering CMOS logic and reversible computing concepts, and
low-power circuit design. Dr. Frank is an IEEE Fellow; he has 505

IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006 A. W. TOPOL ET AL.
 served as chairman of the Si Nanoelectronics Workshop and is an 45-nm front-end process integration for the Silicon Technology
associate editor of IEEE Transactions on Nanotechnology. He has Department at the Thomas J. Watson Research Center and
authored or co-authored more than 90 technical publications and program management in Emerging Products at the IBM
holds nine U.S. patents. Semiconductor Research and Development Center. He previously
worked for several years in the Solid State Division at MIT Lincoln
Laboratory.

Kerry Bernstein IBM Research Division, Thomas J. Watson

Research Center, P.O. Box 218, Yorktown Heights, New York
10598 (kbernste@us.ibm.com). Mr. Bernstein is a Senior Technical Kathryn W. Guarini IBM Corporate Division, 294 Route 100,
Staff Member at the IBM Thomas J. Watson Research Center. He Somers, New York 10598 (kwg@us.ibm.com). Dr. Guarini is
is currently responsible for future product technology definition, currently on assignment in IBM Corporate Technology, working
performance, and application. He received his B.S. degree in on technical assessments for the IBM Technology Team. Before
electrical engineering from Washington University in St. Louis, that, she was a Research Staff Member and Manager of the
joining IBM in 1978. He holds 50 U.S. patents and is a coauthor of 45-nm Front End Integration group in the Silicon Technology
three college textbooks and multiple papers on high-speed and low- Department at the IBM Thomas J. Watson Research Center. Her
power CMOS. Mr. Bernstein is currently interested in the area of research included CMOS device fabrication, three-dimensional
high-performance, low-power advanced circuit technologies. He is integrated circuits, and novel nanofabrication techniques and
a Senior Member of the IEEE, and is a staff instructor at RUNN/ applications. Dr. Guarini joined the IBM Research Division in
Marine Biological Laboratories, Woods Hole, Massachusetts. 1999 after completing her Ph.D. degree in applied physics at
Stanford University.

Steven E. Steen IBM Research Division, Thomas J. Watson

Research Center, P.O. Box 218, Yorktown Heights, New York Meikei Ieong IBM Research Division, 2070 Route 52, Hopewell
10598 (ssteen@us.ibm.com). Mr. Steen is the team leader for Junction, New York 12533 (mkieong@us.ibm.com). Dr. Ieong
optical patterning and line integrators in the microelectronics received the B.S. degree in electrical engineering from the National
research line at the Thomas J. Watson Research Center. He joined Taiwan University, Taiwan, R.O.C., and the M.S. and Ph.D.
IBM in 1997 to help develop Picosecond Imaging Circuit Analysis degrees in electrical and computer engineering from the University
(PICA) for VLSI characterization and design debug. After the of Massachusetts, Amherst, in 1993 and 1996, respectively. Since
successful commercialization of PICA, he moved on to the joining IBM in 1995, he has held numerous management and
challenges of lithography in 2001 and has been leading the imaging engineering positions in both the research and development
efforts in the microelectronics research line. His focus is on organizations. He is currently Senior Manager of the FEOL
developing special lithographic applications to further research integration group at the IBM Thomas J. Watson Research Center,
into novel devices and structures. Mr. Steen is the author of more Yorktown Heights, New York. His departments are responsible
than two dozen technical papers; he has several patents pending. for the 32-nm FEOL integration and metal-gate high-k projects.
He is also project leader for the AMD/IBM Research Alliance and
the Sony/Toshiba/IBM Research Alliance. Dr. Ieong has published
more than one hundred papers in journals and conference
Arvind Kumar IBM Research Division, Thomas J. Watson proceedings. He has more than fifty patents related to
Research Center, P.O. Box 218, Yorktown Heights, New York semiconductor technology issued or pending. He was elected a
10598 (arvkumar@us.ibm.com). Dr. Kumar received the B.S., Master Inventor in the IBM Research Division in 2006. In 2001,
M.S., and Ph.D. degrees in electrical engineering and computer Dr. Ieong held the position of Adjunct Associate Professor in the
science from the Massachusetts Institute of Technology. After Department of Electrical Engineering at Columbia University. He
graduation, he pursued postdoctoral studies in mesoscopic shot is a committee member of the VLSI Technology Symposium and
noise at CEA Saclay, France. In 1996, he joined the IBM Thomas is also on the executive committee of the IEDM. Dr. Ieong has
J. Watson Research Center, where his primary interests have been received an IBM Outstanding Technical Achievement Award, a
in semiconductor device physics, modeling, and design. Research Division Award, a Corporate Award, and two
Supplemental Patent Awards.

Gilbert U. Singco IBM Research Division, Thomas J. Watson

Research Center, P.O. Box 218, Yorktown Heights, New York
10598 (gilbt@us.ibm.com). Mr. Singco is a development engineer
at the IBM Thomas J. Watson Research Center. He worked for
several years in nuclear core design and safety analysis before
coming to IBM in 1985. Mr. Singco received M.S. degrees in
physics and nuclear engineering from the University of Illinois,
and an M.S. degree in electrical engineering from the Rensselaer
Polytechnic Institute. He writes programming tools and utilities for
data analysis of semiconductor measurements.

Albert M. Young IBM Research Division, Thomas J. Watson

Research Center, P.O. Box 218, Yorktown Heights, New York
10598 (yalbert@us.ibm.com). Dr. Young received his Ph.D. degree
in electrical engineering and computer science in 1994 from the
Massachusetts Institute of Technology. He is Program Manager
for 3D integration at IBM and is involved in fabrication and
infrastructure development activities related to the vertical stacking
506 of silicon integrated circuits. His prior work experience includes

A. W. TOPOL ET AL. IBM J. RES. & DEV. VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006

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