CACHE COHERENCE :

SNOOPY PROTOCOLS

Dr M Rajasekhara Babu

Vellore-632014, Tamil Nadu, India

 Outline
Session objectives

Write Invalid and Write update policies

Cache Events and Actions

Example

Summary

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 2

 Objectives
To explore Policies, used for
maintaining cache consistency

To acquaint with snoopy

protocols

To apprise with Cache Events

and Actions

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 3

 Write-invalidate, write-update
Snooping
• Every cache Line is accompanied by the
sharing status of that block
• All cache controllers monitor the shared
bus
• Policies used for maintaining cache
consistency
– Write-invalidate
• a processor gains exclusive access of a block
before writing by invalidating all other copies
– Write-update
• when a processor writes, it updates other shared
copies of that block
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 4
 Write-invalidate, write-update
 Example
Snoopy protocols
• P0: Rd X
• P1: Rd X
• Caches of P0 and P1 as well as Shared
memory have consistent copies
Processor Processor Processor
P0 P1 Pn

X X

X
Shared Memory
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 5
 Write-invalidate, write-update
 Example
Snoopy protocols
• P0: Rd X
• P1: Rd X
– Caches of P0 and P1 as well as Shared memory have
consistent copies
• P0: Wr X
Processor Processor Processor
P0 P1 Pn

X X I

X
Shared Memory
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 6
 Write-invalidate, write-update
 Example,
Cache Events and Actions
 Cache Events and Actions • Read-hit
– Read Hit
– Is always performed in local cache memory
– Example: P0 Rd X

Processor Processor
P0 P1

HIT
X
Cache Cache

Shared Memory

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 7

 Write-invalidate, write-update
 Example,
Cache Events and Actions: Read-miss
 Cache Events and Actions • No copy exists with other caches
– Read Hit, Read Miss
– Main Memory supplies a copy
– Set that cache copy in Valid state
• Example: P1 Rd y
Processor Processor
P0 P1

MISS
Cache Cache

y
Shared Memory
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 8
 Write-invalidate, write-update
 Example,
Cache Events and Actions: Read-miss
 Cache Events and Actions • If a copy exists in a remote cache
– Read Hit, Read Miss
– Send a copy to the requesting cache from
remote cache
• Example: P1 Rd x

Processor Processor
P0 P1

x
MISS
Cache Cache

Shared Memory
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 9
 Write-invalidate, write-update
 Example,
Cache Events and Actions: Write-hit
 Cache Events and Actions • If the copy is available in multiple caches
– Read Hit, Read Miss
– Write Hit
– invalidate to all other caches copies
– Modify locally and set to dirty state
• Example: P1 WR x

Processor Processor
P0 P1

XX x I
HIT Cache Cache

Shared Memory
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 10
 Write-invalidate, write-update
 Example,
Cache Events and Actions: Write-miss
 Cache Events and Actions • Write-miss
– Read Hit, Read Miss
– If a processor fails to write in the local cache memory,
– Write Hit, Write Miss
• the copy must come either from the main memory or from a
remote cache memory with a dirty block.
• This is done by sending a read-invalidate command, which
will invalidate all cache copies.
• Then the local copy is updated with dirty state.

Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 11

 Write-invalidate, write-update, Eg.
 Cache Events and Actions
SMP Example
– Read Hit, Read Miss A: Rd X
– Write Hit, Write Miss B: Rd X
 SMP Example
C: Rd X
Processor Processor Processor Processor
A: Wr X
A: Wr X
Cache Cache Cache Cache
C: Wr X A B C D
B: Rd X
A: Rd X
A: Rd Y
B: Wr X Main Memory I/O System

B: Rd Y
B: Wr X
B: Wr Y
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 12
 Write-invalidate, write-update, Eg.
 Cache Events and Actions
SMP Example
– Read Hit, Read Miss Step Instruction A B C Remarks
– Write Hit, Write Miss 1 A: Rd X S(X)
 SMP Example 2 B: Rd X S(X) S(X)
3 C: Rd X S(X) S(X) S(X)
4 A: Wr X E(X) I(X) I(X)
5 A: Wr X E(X) I(X) I(X)
6 C: Wr X I(X) I(X) E(X)
7 B: Rd X I(X) S(X) S(X)
8 A: Rd X S(X) S(X) S(X)
9 A: Rd Y S(X),S (Y) S (X) S (X)
10 B: Wr X I(X),S (Y) E (X) I(X)
11 B: Rd Y I(X), S (Y) E(X), S (Y) I(X)
12 B: Wr X I(X),S (Y) E (X) , S (Y) I(X)
13 B: Wr Y I(X),I(Y) E(X), E (Y) I(X)
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 13
 Summary
• Write-invalidate • Example
• Write-update
• Cache Events and
Actions
– Read-hit
– Read-miss
• If no copy exists with
other caches
• If a copy exists in a
remote cache
– Write-hit
• If the copy is available in
multiple caches
– Write-miss
Dr M Rajasekhara Babu, Vellore Institute of Technology (VIT)-Vellore Slide.# 14
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