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HDL LAB MANUAL

As Per VTU CBCS Syllabus
5TH SEM ELECTONICS AND COMMUNICATION

VISHVAKIRAN R C

2 0 2 0

ELECTRONICS AND COMMUNICATION ENGG DEPT.

 CONTENTS

PART A:
PROGRAMMING (Verilog Using Xilinx Tool)
Write a Verilog program for the following combinational designs ............................................ 1-12
1. 2 to 4 decoder using only NAND gates ........................................................................................... 1
2. 8 to 3 encoder without priority ........................................................................................................ 3
3. 8 to 3 encoder with priority ............................................................................................................. 5
4. 8 to 1 multiplexer using case and if statements .............................................................................. 7
5. 4 bit binary to gray converter using 1 bit adder, 1 bit subractor, 1 bit gray to binary ................... 10
6. a. Write a Verilog code to describe the functions of a Full Adder Using 3 modeling styles . 13-18
i. Full Adder Data Flow Description ......................................................................................... 13
ii. Logic Gates AND, OR, XOR, XNOR using Full Adder ........................................................ 15
iii. Full Adder Behavioral Description ........................................................................................ 15
iv. Full Adder Structural Description .......................................................................................... 17
7. Verilog 32-bit ALU shown in figure below and verify the functionality of ALU by selecting
appropriate test patterns. The functionality of the ALU is presented in Table 1. .................... 19-21
a. Write test bench to verify the functionality of the ALU considering all possible input
patterns
b. The enable signal will set the output to required functions if enabled, if disabled all the
outputs are set to tri-state
c. The acknowledge signal is set high after every operation is Completed Write a Verilog
code to model 32 bit ALU using the schematic diagram shown below
OPCODE ALU OPERATION Bin [31:0] Ain [31:0]

32
0. A+B 32

Ack
1. A–B 3

Opcode[2:0] 32
32-bit ALU
2. A OR B Result[31:0]
Enable
3. A AND B ALU top level block diagram
4. A Complement
5. A+1
6. A–1
7. A True
Develop the Verilog code for the following flip-flops, SR, D, JK and T......................................... 22-29
8. SR Flip Flop ................................................................................................................................. 22
9. JK Flip Flop .................................................................................................................................. 24
10. D Flip Flop ................................................................................................................................... 26
11. T Flip Flop .................................................................................................................................... 28
Note: Clock divider Concept
Design a 4 bit binary, BCD counters Synchronous reset counters, using Verilog code ................ 31-34
12. BCD Synchronous Reset 4bit Counter ......................................................................................... 31
13. Binary Synchronous Reset 4bit Counter considering the frequency divider ................................ 33

i
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
1. 2 to 4 decoder realization using NAND gates only (structural
model)
2
d_in

inputs 4
Decoder 2 to 4 d_op
outputs
en

Figure 1: Block Diagram of Decoder 2 to 4

Inputs Outputs
en d_in(1) d_in(0) d_op(3) d_op(2) d_op(1) d_op(0)
0 X X Z Z Z Z
1 0 0 1 1 1 0
1 0 1 1 1 0 1
1 1 0 1 0 1 1
1 1 1 0 1 1 1
Truth Table 1: Decoder 2 to 4

𝑑_𝑜𝑝[0] = ̅̅̅̅̅̅̅̅̅̅
𝑑_𝑖𝑛[1] ∙ ̅̅̅̅̅̅̅̅̅̅
𝑑_𝑖𝑛[0] ∙ 𝑒𝑛
𝑑_𝑜𝑝[1] = ̅̅̅̅̅̅̅̅̅̅
𝑑_𝑖𝑛[1] ∙ 𝑑_𝑖𝑛[0] ∙ 𝑒𝑛
𝑑_𝑜𝑝[2] = 𝑑_𝑖𝑛[1] ∙ ̅̅̅̅̅̅̅̅̅̅
𝑑_𝑖𝑛[0] ∙ 𝑒𝑛
𝑑_𝑜𝑝[3] = 𝑑_𝑖𝑛[1] ∙ 𝑑_𝑖𝑛[0] ∙ 𝑒𝑛

Verilog File Name: decoder2to4.v

// decoder2to4
module decoder2to4(en,d_in, d_op );
input [1:0] d_in;
input en;
output [3:0] d_op;
nand n0(d_op[0],!d_in[1],!d_in[0], en);
nand n1(d_op[1],!d_in[1], d_in[0], en);
nand n2(d_op[2], d_in[1],!d_in[0], en);
nand n3(d_op[3], d_in[1], d_in[0], en);

endmodule

Verilog Testbench File Name:decoder_test.v

module dec_tb;
reg [1:0] din;
reg en;
wire [3:0] dout;

decoder2to4 uut ( .d_in(din), .en(en), .d_op(dout) );

initial
begin // Initialize Inputs
en = 0;
#10 en = 1; din = 2’b00;
#10 din = 2’b01;

PART-A: NON-INTERFACING 1 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
#10 din = 2’b10;
#10 din = 2’b11;
#10 en = 0; din = 2’b10;
end

initial #60 $finish;

initial $monitor ($time,” %b %b %b “,en,din, dout);

endmodule

Waveform 1: Decoder 2 to 4

0 0 xx zzzz
10 1 00 1110
20 1 01 1101
30 1 10 1011
40 1 11 0111
50 0 10 zzzz
Stopped at time : 60 ns
Transcript1: Decoder 2 to 4

PART-A: NON-INTERFACING 2 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
2. 8 to 3 encoder without priority (behavioral model)
8
a_in

inputs Encoder 3
y_op
Without Priority
outputs
en

Figure 2: Block Diagram of Encoder Without Priority

Inputs Outputs
y_op y_op y_op
en a_in(7) a_in(6) a_in(5) a_in(4) a_in(3) a_in(2) a_in(1) a_in(0)
(2) (1) (0)

1 X X X X X X X X Z Z Z

0 0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 1 0 0 0 0 1 1

0 0 0 0 1 0 0 0 0 1 0 0

0 0 0 1 0 0 0 0 0 1 0 1

0 0 1 0 0 0 0 0 0 1 1 0

0 1 0 0 0 0 0 0 0 1 1 1
Truth Table 2: Encoder Without Priority
Verilog File Name: encd_wo_prior.v
// encoder without priority
module encd_wo_prior( en, a_in, y_op );
input en;
input [7:0] a_in;
output [2:0] y_op;
wire en;
wire [7:0] a_in;
reg [2:0] y_op;

always @ (a_in, en)

begin
if(en) //Active Low Enabled
y_op = 3'bZZZ;
else
begin
case (a_in)
8'b00000001 : y_op = 3'b000;

PART-A: NON-INTERFACING 3 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
8'b00000010 : y_op = 3'b001;
8'b00000100 : y_op = 3'b010;
8'b00001000 : y_op = 3'b011;
8'b00010000 : y_op = 3'b100;
8'b00100000 : y_op = 3'b101;
8'b01000000 : y_op = 3'b110;
8'b10000000 : y_op = 3'b111;
default : y_op = 3'bZZZ;
endcase
end
end
endmodule

Verilog Testbench File Name:encd_wo_ptest.v

module encd_wop_tb;
reg [7:0] ain;
reg en;
wire [2:0] yout;
encd_wo_prior uut (.a_in(ain),.en(en),.y_op(yout));
initial
begin
en = 1;
#10 en = 0;
#10 ain =8'b10000000 ;
#10 ain =8'b01000000 ;
#10 ain =8'b00100000 ;
#10 ain =8'b00010000 ;
#10 ain =8'b00001000 ;
#10 ain =8'b00000100 ;
#10 ain =8'b00000010 ;
#10 ain =8'b00000001 ;
#10 ain =8'b10000001 ;
#10 ain =8'b00011101 ;
end
initial #120 $finish;
initial $monitor ($time," %b %b %b ",en, ain, yout);
endmodule

Waveform 2: Encoder Without Priority

0 1 xxxxxxxx zzz
10 0 xxxxxxxx zzz
20 0 10000000 111
30 0 01000000 110
40 0 00100000 101
50 0 00010000 100
60 0 00001000 011
70 0 00000100 010
80 0 00000010 001
90 0 00000001 000
100 0 10000001 zzz
110 0 00011101 zzz
Stopped at time : 120 ns
Transcript 2: Encoder Without Priority

PART-A: NON-INTERFACING 4 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
3. 8 to 3 encoder with priority (behavioral model)
8
a_in

inputs Encoder 3
y_op
With Priority
outputs
en

Figure 3: Block Diagram of Encoder With Priority

Inputs Outputs
y_op y_op y_op
en a_in(7) a_in(6) a_in(5) a_in(4) a_in(3) a_in(2) a_in(1) a_in(0)
(2) (1) (0)
1 X X X X X X X X Z Z Z
0 1 X X X X X X X 1 1 1
0 0 1 X X X X X X 1 1 0
0 0 0 1 X X X X X 1 0 1
0 0 0 0 1 X X X X 1 0 0
0 0 0 0 0 1 X X X 0 1 1
0 0 0 0 0 0 1 X X 0 1 0
0 0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 0 0 0 1 0 0 0
Truth Table 3: Encoder With Priority
Verilog File Name: encd_w_prior.v
// encoder with priority
module encd_w_prior( en, a_in, y_op );
input en;
input [7:0] a_in;
output [2:0] y_op;
wire en;
wire [7:0] a_in;
reg [2:0] y_op;

always @ (a_in, en)

begin
if (en == 1'b1) // Active Low Enabled
y_op = 3'bZZZ;
else
begin
if(a_in[7] == 1'b1) y_op = 3'b111;
else if(a_in[6] == 1'b1) y_op = 3'b110;
else if(a_in[5] == 1'b1) y_op = 3'b101;
else if(a_in[4] == 1'b1) y_op = 3'b100;
else if(a_in[3] == 1'b1) y_op = 3'b011;
else if(a_in[2] == 1'b1) y_op = 3'b010;
else if(a_in[1] == 1'b1) y_op = 3'b001;

PART-A: NON-INTERFACING 5 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
else if(a_in[0] == 1'b1) y_op = 3'b000;
else y_op = 3'bZZZ;
end
end
endmodule

Verilog Testbench File Name:encd_w_ptest.v

module encd_wp_tb;
reg [7:0] ain;
reg en;
wire [2:0] yout;
encd_w_prior uut (.a_in(ain),.en(en),.y_op(yout));
initial
begin
en = 1;
#10 en = 0;
#10 ain =8'b10000000 ;
#10 ain =8'b01000000 ;
#10 ain =8'b00100000 ;
#10 ain =8'b00010000 ;
#10 ain =8'b00001000 ;
#10 ain =8'b00000100 ;
#10 ain =8'b00000010 ;
#10 ain =8'b00000001 ;
#10 ain =8'b10000001 ;
#10 ain =8'b00011101 ;
end
initial #120 $finish;
initial $monitor ($time," %b %b %b ",en, ain, yout);
endmodule

Waveform 3: Encoder With Priority

0 1 xxxxxxxx zzz
10 0 xxxxxxxx zzz
20 0 10000000 111
30 0 01000000 110
40 0 00100000 101
50 0 00010000 100
60 0 00001000 011
70 0 00000100 010
80 0 00000010 001
90 0 00000001 000
100 0 10000001 111
110 0 00011101 100
Stopped at time : 120 ns
Transcript3: Encoder WithPriority

PART-A: NON-INTERFACING 6 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
4. 8 to 1 multiplexer using case statement and if statements
8
i_in

inputs y_out
Multiplexer 8 to 1
output
en

3
sel
Figure 4: Block Diagram of Multiplexer 8 to 1

Inputs Output
sel sel sel i_in i_in i_in i_in i_in i_in i_in i_in
en y_out
(2) (1) (0) (7) (6) (5) (4) (3) (2) (1) (0)
1 X X X X X X X X X X X Z
0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 0 0 1
0 0 1 1 0 0 0 0 1 0 0 0 1
0 1 0 0 0 0 0 1 0 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 1 0 0 1 0 0 0 0 0 0 1
0 1 1 1 1 0 0 0 0 0 0 0 1
Truth Table 4: Mux 8 to 1
Verilog File Name: mux8to1c.v
// Multiplexer 8 to 1 using case statement
module mux8to1(en,i_in,sel,y_out);
input en;
input [2:0] sel;
input [7:0] i_in;
output y_out;
wire en;
wire [7:0] i_in;
wire [2:0] sel;
reg y_out;

always@(en,sel,i_in)
begin
if(en != 0) // Active Low Enabled
y_out = 1'bZ;
else
begin
case(sel)
3'b000: y_out = i_in[0];
3'b001: y_out = i_in[1];
3'b010: y_out = i_in[2];
3'b011: y_out = i_in[3];
3'b100: y_out = i_in[4];
PART-A: NON-INTERFACING 7 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
3'b101: y_out = i_in[5];
3'b110: y_out = i_in[6];
3'b111: y_out = i_in[7];
default: y_out = 1'bZ;
endcase
end
end
endmodule

Verilog File Name: mux8to1if.v

// Multiplexer 8 to 1 using if statement
module mux8to1(en,i_in,sel,y_out);
input en;
input [2:0] sel;
input [7:0] i_in;
output y_out;
wire en;
wire [7:0] i_in;
wire [2:0] sel;
reg y_out;
always@(en,sel,i_in)
begin
if(en != 0) // Active Low Enabled
y_out = 1'bZ;
else
begin
if ( sel==3'b111 ) y_out =i_in[7];
else if (sel==3'b110) y_out = i_in[6];
else if ( sel==3'b101) y_out = i_in[5];
else if ( sel==3'b100) y_out = i_in[4];
else if ( sel==3'b011) y_out = i_in[3];
else if ( sel==3'b010) y_out = i_in[2];
else if ( sel==3'b001) y_out = i_in[1];
else if ( sel==3'b000) y_out = i_in[0];
else y=1’bZ;

end
end
endmodule

Verilog Testbench File Name: mux81_test.v

module mux81_tb;
reg en;
reg [7:0] i_in;
reg [2:0] sel;
wire yout;
mux8to1 uut (.en(en),.i_in(i_in),.sel(sel),.y_out(yout));
initial
begin
en = 1;
#10 en = 0;
#10 i_in = 8'b01000010; sel = 3'b001;
#10 i_in = 8'b00000100; sel = 3'b010;
#10 i_in = 8'b00001000; sel = 3'b011;

PART-A: NON-INTERFACING 8 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
#10 i_in = 8'b00010000; sel = 3'b100;
#10 i_in = 8'b00100000; sel = 3'b101;
#10 i_in = 8'b01000000; sel = 3'b001;

end
initial #80 $finish;
initial $monitor ($time," %b %b %b %b ",en, i_in, sel, yout);
endmodule

Waveform 4: Mux 8 to 1

0 1 xxxxxxxx xxx z
10 0 xxxxxxxx xxx z
20 0 01000010 001 1
30 0 00000100 010 1
40 0 00001000 011 1
50 0 00010000 100 1
60 0 00100000 101 1
70 0 01000000 001 0
Stopped at time : 80 ns
Transcript4: Multiplexer 8 to 1

PART-A: NON-INTERFACING 9 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
5. 4-bit binary to gray converter using 1-bit gray to binary
converter 1-bit adder and subtractor

Binary
inputs 4
to g_op
4
b_in Gray
outputs
Converter

Figure 5: Block Diagram of Binary to Gray Converter

b_in(0)
b_in(1)
g_op(0) Boolean Expressions
𝑔_𝑜𝑝(3) = 𝑏_𝑖𝑛(3)
b_in(2)
g_op(1) 𝑔_𝑜𝑝(2) = 𝑏_𝑖𝑛(3)⨁ 𝑏_𝑖𝑛(2)
𝑔_𝑜𝑝(1) = 𝑏_𝑖𝑛(2)⨁ 𝑏_𝑖𝑛(1)
b_in(3)
g_op(2) 𝑔_𝑜𝑝(0) = 𝑏_𝑖𝑛(1)⨁ 𝑏_𝑖𝑛(0)
g_op(3)

Logic Diagram of 4bits Binary to Gray

Converter

Inputs Outputs
Binary Gray
Decimal
b_in(3) b_in(2) b_in(1) b_in(0) g_op(3) g_op(2) g_op(1) g_op(0)
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Truth Table 5: Binary to Gray
Verilog File Name: bin_to_gray_4bit.v
// Binary to Gray 4bit Converter
module bin_to_gray_4bit( b_in, g_op );
input [3:0] b_in;
output [3:0] g_op;
assign g_op[3]= b_in[3];
halfadder ha1(g_op[2],,b_in[3], b_in[2]);
halfsubtractor hs1(g_op[1],,b_in[2], b_in[1]);

PART-A: NON-INTERFACING 10 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
xor x1(g_op[0], b_in[1], b_in[0]);
endmodule

module halfadder(sum,carry,ain,bin);
output sum, carry;
input ain, bin;
assign sum=ain ^bin;
assign carry=ain &bin;
endmodule

module halfsubtractor(difference, borrow,ain,bin);

output difference, borrow;
input ain,bin;
assign difference =ain ^bin;
assign borrow =~ain &bin ;
endmodule

Verilog Testbench File Name:b2g_4bit_test.v

module bitogr_tb;
reg [3:0] bin;
wire [3:0] gout;
bin_to_gray_4bit uut (.b_in(bin), .g_op(gout) );
initial
begin
bin=0;
#10 bin=1;
#10 bin=2;
#10 bin=3;
#10 bin=4;
#10 bin=5;
#10 bin=6;
#10 bin=7;
#10 bin=8;
#10 bin=9;
#10 bin=10;
#10 bin=11;
#10 bin=12;
#10 bin=13;
#10 bin=14;
#10 bin=15;
end
initial #160 $finish;
initial $monitor ($time," %b %b ",bin, gout);
endmodule

Waveform 5: 4Bit Binary to Gray Converter

PART-A: NON-INTERFACING 11 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

0 0000 0000
10 0001 0001
20 0010 0011
30 0011 0010
40 0100 0110
50 0101 0111
60 0110 0101
70 0111 0100
80 1000 1100
90 1001 1101
100 1010 1111
110 1011 1110
120 1100 1010
130 1101 1011
140 1110 1001
150 1111 1000
Stopped at time : 160 ns
Transcript5: 4Bit Binary to Gray Converter

PART-A: NON-INTERFACING 12 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
6. Full Adder – a. Verilog Module

a_in sum
b_in Full Adder outputs
inputs
c_in carry

Figure 6a: Block Diagram of Full Adder

a_in S1
b_in x1 sum
x2

a2
S3
carry
o1
a1
S2
c_in

Logic Diagram of Full Adder

Inputs Outputs
a_in b_in c_in sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Truth Table 6a: Full Adder
Logical expression:
Halfadder sum ->S1
𝑆1 = 𝑎 ⊕ 𝑏 ; 𝑠𝑢𝑚 = 𝑆1 ⊕ 𝑐_𝑖𝑛 ;
𝑐𝑎𝑟𝑟𝑦 = 𝑎 ∗ 𝑏 + 𝑆1 ∗ 𝑐_𝑖𝑛;

Conditions to Verify AND, OR, XOR and XNOR:

Condition 1: When c_in = 0,
𝑠𝑢𝑚 = 𝑆1 ⊕ 0 = 𝑆1 = 𝑎 ⊕ 𝑏= XOR gate
𝑐𝑎𝑟𝑟𝑦 = 𝑎 ∗ 𝑏 + 𝑆1 ∗ 0 = 𝑎 ∗ 𝑏 = 𝑎 & 𝑏 = AND gate
Condition 2: When c_in =1,
𝑠𝑢𝑚 = 𝑆1 ⊕ 1 = 𝑆1 ∙ 1̅ + ̅̅̅ 𝑆1 = 𝑎̅𝑏̅ + 𝑎 𝑏 = XNOR gate
𝑆1 ∙ 1 = ̅̅̅
𝑐𝑜𝑢𝑡 = 𝑎 ∗ 𝑏 + 𝑆1 ∗ 1 = 𝑎𝑏 + 𝑎𝑏̅ + 𝑎̅𝑏 = 𝑎 (𝑏 + 𝑏̅) + 𝑎̅𝑏 = 𝑎 + 𝑎̅𝑏 = (𝑎 + 𝑎̅)(𝑎 + 𝑏) = OR gate

PART-A: NON-INTERFACING 13 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
Inputs Outputs
a b aandb aorb axorb axnorb
0 0 0 0 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 1 0 1
Truth Table 6b: Full Adder
Full Adder Data Flow Description

Verilog File Name: FullAdder_DF.v

// FullAdder - Data Flow Model
module fulladder_df( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;

assign sum = a_in ^ b_in ^ c_in;

assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in);
endmodule

Verilog Testbench File Name: full_adder_test.v

module fulladd_tb;
reg ain, bin, cin;
wire sum, carry;

fulladder_df uut (.a_in(ain), .b_in(bin), .c_in(cin),

.sum(sum),.carry(carry));
initial
begin

ain = 0; bin = 0; cin = 0; #100;

ain = 0; bin = 0; cin = 1; #100;
ain = 0; bin = 1; cin = 0; #100;
ain = 0; bin = 1; cin = 1; #100;
ain = 1; bin = 0; cin = 0; #100;
ain = 1; bin = 0; cin = 1; #100;
ain = 1; bin = 1; cin = 0; #100;
ain = 1; bin = 1; cin = 1; #100;
ain = 0; bin = 0; cin = 0; #100;
#100;

end
endmodule

PART-A: NON-INTERFACING 14 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

a_in S1 HA2
b_in x1 sum
x2

HA1 a2
S3
carry
o1
a1
S2
c_in

Logic Diagram of Full Adder using two Half Adder

Basic gates using Full Adder

Verilog File Name: FullAdder_HalfAdder.v

module fulladder(a_in,b_in,c_in,sum,carry);
input a_in,b_in,c_in;
output sum, carry;
wire S1;
assign S1 = a_in^b_in;
assign sum = S1^c_in;
assign carry= (a_in&b_in) | (S1&c_in);
endmodule

Verilog File Name:Basicgates_FullAdder.v

module basicgate_fa(a,b,aandb, aorb, axorb, axnorb);
input a,b;
output aandb, aorb, axorb, axnorb;
fulladder i1(a,b,1'b0, axorb,aandb);
fulladder i2(a,b,1'b1, axnorb,aorb);
endmodule

Verilog Testbench File Name:Basicgate_test.v

module basicg_test;
reg a,b;
wire aandb,aorb,axorb,axnorb;
basicgate_fa uut(.a(a), .b(b), .aandb(aandb), .aorb(aorb),
.axorb(axorb), .axnorb(axnorb));

initial begin
a = 0; b = 0;
#10 a = 0; b = 1;
#10 a = 1; b = 0;
#10 a = 1; b = 1;
#10;
end
endmodule

Full Adder Behavioral Description

Verilog File Name: FullAdder_Behav.v

//FullAdder - Behavioral Model
module fulladder_behav( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;

PART-A: NON-INTERFACING 15 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
wire a_in, b_in, c_in;
reg sum, carry;

always @ ( a_in, b_in, c_in)

begin
if(a_in==0 & b_in==0 & c_in==0)
begin
sum = 0;
carry = 0;
end
else if (( a_in==0 & b_in==0 & c_in == 1)
| (a_in==0 & b_in==1 & c_in == 0)
| (a_in==1 & b_in==0 & c_in == 0))
begin
sum = 1;
carry = 0;
end

else if (( a_in==0 & b_in==1 & c_in == 1)

| (a_in==1 & b_in==0 & c_in == 1)
| (a_in==1 & b_in==1 & c_in == 0))
begin
sum = 0;
carry = 1;
end
else if(a_in==1 & b_in==1 & c_in == 1)
begin
sum = 1;
carry = 1;
end
end
endmodule

Verilog Testbench File Name: full_adder_test.v

module fulladd_tb;
reg ain, bin, cin;
wire sum, carry;

fulladder_behav uut (.a_in(ain), .b_in(bin), .c_in(cin),

.sum(sum),.carry(carry));
initial
begin

ain = 0; bin = 0; cin = 0; #100;

ain = 0; bin = 0; cin = 1; #100;
ain = 0; bin = 1; cin = 0; #100;
ain = 0; bin = 1; cin = 1; #100;
ain = 1; bin = 0; cin = 0; #100;
ain = 1; bin = 0; cin = 1; #100;
ain = 1; bin = 1; cin = 0; #100;
ain = 1; bin = 1; cin = 1; #100;
ain = 0; bin = 0; cin = 0; #100;
#100;
end
endmodule

PART-A: NON-INTERFACING 16 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

Full Adder Structural Description

Verilog File Name: full_adder_struct.v

//Full Adder - Structural
module full_adder( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
wire s1,s2,s3;

//syntax: gate_operator lable (ouput, input, input, , , );

half_adder HA1 (s1, s2, a_in, b_in);
half_adder HA2 (sum, s3, s1, c_in);
or O1 (carry, s2, s3);
endmodule
Verilog File Name: half_adder_dataflow.v
//Half Adder - Dataflow
module half_adder( sum, carry, a_in, b_in );
input a_in, b_in;
output sum, carry;

assign sum = a_in ^ b_in;

assign carry = a_in & b_in;

endmodule

Verilog Testbench File Name: full_adder_test.v

module fulladd_tb;
reg ain, bin, cin;
wire sum, carry;

full_adder uut (.a_in(ain), .b_in(bin), .c_in(cin),

.sum(sum),.carry(carry));
initial
begin

ain = 0; bin = 0; cin = 0; #100;

ain = 0; bin = 0; cin = 1; #100;
ain = 0; bin = 1; cin = 0; #100;
ain = 0; bin = 1; cin = 1; #100;
ain = 1; bin = 0; cin = 0; #100;
ain = 1; bin = 0; cin = 1; #100;
ain = 1; bin = 1; cin = 0; #100;
ain = 1; bin = 1; cin = 1; #100;
ain = 0; bin = 0; cin = 0; #100;
#100;

end
endmodule

PART-A: NON-INTERFACING 17 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

Waveform 6: Full Adder

Waveform7: Basic Gates AND, OR, XOR, XNOR

Figure 6B: RTL Schematic of Basic Gates using FullAdder

PART-A: NON-INTERFACING 18 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
7. ALU 32 Bits

a_in [31:0] b_in [31:0]

32 32

ack
3

opcode[2:0] 32
32-bit ALU
zout[31:0]
en
Figure 10: Block diagram of ALU 32 bits

Inputs Outputs
Actions
opc a_in b_in zout ack
XXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXX
XXX ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ 0 No Change
XXXXX XXXXX
000 000000000000000000010111 000000000000000000101101 00000000000000000000000001000100 1 a_in + b_in
001 000000000000000000010111 000000000000000000101101 11111111111111111111111111101010 1 a_in - b_in
010 000000000000000000010111 000000000000000000101101 00000000000000000000000000111111 1 a_in or b_in
011 000000000000000000010111 000000000000000000101101 00000000000000000000000000000101 1 a_in and b_in
100 000000000000000000010111 11111111111111111111111111101000 1 not a_in
101 000000000000000000010111 000000000000000000011000 1 a_in + 1
110 000000000000000000010111 000000000000000000010110 1 a_in - 1
111 000000000000000000010111 000000000000000000010111 1 a_in

Truth Table 7: ALU 32bits

Verilog File Name: alu32bit.v
// ALU 32bit
`timescale 1ns / 1ps

module alu32bit(a_in,b_in,opcode,zout,ack);
input [23:0] a_in,b_in;
input [2:0] opcode;
output [31:0] zout;
output ack;
reg [31:0] zout;
reg ack;
wire [31:0] a, b;

assign a = {8'b0,a_in};
assign b = {8'b0,b_in};

always@ *
begin
case (opcode)
3'b000 : begin zout = a+b; ack = 1; end
3'b001 : begin zout = a-b;ack = 1; end
3'b010 : begin zout = a | b; ack = 1; end
3'b011 : begin zout = a & b; ack = 1; end
3'b100 : begin zout = ~ a;ack = 1; end
3'b101 : begin zout = a*b;ack = 1; end
3'b110 : begin zout = a + 1;ack = 1; end
PART-A: NON-INTERFACING 19 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
3'b111 : begin zout = a;ack = 1; end
default : begin zout = 32'd0; ack = 0; end
endcase
end

endmodule
Verilog Testbench File Name: alu32bit_test.v

`timescale 1ns / 1ps

module alu32bit_test;

// Inputs
reg [23:0] a_in;
reg [23:0] b_in;
reg [2:0] opcode;

// Outputs
wire [31:0] zout;

// Instantiate the Unit Under Test (UUT)

alu32bit uut (.a_in(a_in),.b_in(b_in),.opcode(opcode),.zout(zout));

initial begin
// Initialize Inputs
a_in = 23; b_in = 45;
opcode = 0;
#1 opcode = 1;
#1 opcode = 2;
#1 opcode = 3;
#1 opcode = 4;
#1 opcode = 5;
#1 opcode = 6;
#1 opcode = 7;
#1 a_in = 53; b_in = 56;
#1 opcode = 0;
#1 opcode = 1;
#1 opcode = 2;
#1 opcode = 3;
#1 opcode = 4;
#1 opcode = 5;
#1 opcode = 6;
#1 opcode = 7;
end

initial #20 $finish;

initial $monitor ($time," %b %b %b ====> %b " , a_in,b_in,opcode,zout);

endmodule

PART-A: NON-INTERFACING 20 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

Finished circuit initialization process.

0 000000000000000000010111 000000000000000000101101 000 ====> 00000000000000000000000001000100 1
1 000000000000000000010111 000000000000000000101101 001 ====> 11111111111111111111111111101010 1
2 000000000000000000010111 000000000000000000101101 010 ====> 00000000000000000000000000111111 1
3 000000000000000000010111 000000000000000000101101 011 ====> 00000000000000000000000000000101 1
4 000000000000000000010111 000000000000000000101101 100 ====> 11111111111111111111111111101000 1
5 000000000000000000010111 000000000000000000101101 101 ====> 00000000000000000000010000001011 1
6 000000000000000000010111 000000000000000000101101 110 ====> 00000000000000000000000000011000 1
7 000000000000000000010111 000000000000000000101101 111 ====> 00000000000000000000000000010111 1
8 000000000000000000110101 000000000000000000111000 111 ====> 00000000000000000000000000110101 1
9 000000000000000000110101 000000000000000000111000 000 ====> 00000000000000000000000001101101 1
10 000000000000000000110101 000000000000000000111000 001 ====> 11111111111111111111111111111101 1
11 000000000000000000110101 000000000000000000111000 010 ====> 00000000000000000000000000111101 1
12 000000000000000000110101 000000000000000000111000 011 ====> 00000000000000000000000000110000 1
13 000000000000000000110101 000000000000000000111000 100 ====> 11111111111111111111111111001010 1
14 000000000000000000110101 000000000000000000111000 101 ====> 00000000000000000000101110011000 1
15 000000000000000000110101 000000000000000000111000 110 ====> 00000000000000000000000000110110 1
16 000000000000000000110101 000000000000000000111000 111 ====> 00000000000000000000000000110101 1
Stoppedattime : 20ns
Transcript Output6: ALU 32 Bits

PART-A: NON-INTERFACING 21 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
8. S R Flip Flop
s
q
r
SR Flip Flop outputs
inputs
qb
rst

clk
Figure 8: Block Diagram of SR Flip Flop

Inputs Outputs
rst clk s r q qb Action
1 ↑ X X q qb No Change
0 ↑ 0 0 q qb No Change
0 ↑ 0 1 0 1 Reset
0 ↑ 1 0 1 0 Set
0 ↑ 1 1 - - Illegal
Truth Table 8: S R Flip Flop
Verilog File Name: sr_ff.v
//Async SR Flip Flop
module sr_ff( sr , clk , reset , q ,qb );
input [1:0] sr;
input clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (sr)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = 1'bX;
endcase
qb = ~q;
end
endmodule

PART-A: NON-INTERFACING 22 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
Verilog Testbench File Name: sr_ff_test.v
`timescale 1ns/1ps
module srflip_tb;
reg clk, rst;
reg [1:0] sr;
wire q, qb;

sr_ff uut ( .clk(clk), .reset(rst), . sr(sr), .q(q), .qb(qb));

initial
begin
clk = 0; rst=1; sr=2'b00;
end
always
#5 clk=~clk;
initial
begin
#10 rst=0;
#10 sr = 2'b10;
#10 sr = 2'b00;
#10 sr = 2'b01;
#10 sr = 2'b11;
#20 sr = 2'b10;
#10 sr = 2'b00;
#10;
end
initial #100 $finish;
initial $monitor ($time," %b %b %b ---> %b ",clk , rst , sr, q
,qb);
endmodule

Waveform 8: S R Flip Flop

0 0 1 00 ---> 0 1
5 1 1 00 ---> 0 1
10 0 0 00 ---> 0 1
15 1 0 00 ---> 0 1
20 0 0 10 ---> 0 1
25 1 0 10 ---> 1 0
30 0 0 00 ---> 1 0
35 1 0 00 ---> 1 0
40 0 0 01 ---> 1 0
45 1 0 01 ---> 0 1
50 0 0 11 ---> 0 1
55 1 0 11 ---> x x
60 0 0 11 ---> x x
65 1 0 11 ---> x x
70 0 0 10 ---> x x
75 1 0 10 ---> 1 0
80 0 0 00 ---> 1 0
85 1 0 00 ---> 1 0
Stopped at time : 100.000 ns
Transcript 7: S R Flip Flop
PART-A: NON-INTERFACING 23 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

9. J K Flip Flop
j
q
k
JK Flip Flop outputs
inputs
qb
rst

clk
Figure 9: Block Diagram of JK Flip Flop

Inputs Outputs
rst clk j k q qb Action
1 ↑ X X q qb No Change
0 ↑ 0 0 q qb No Change
0 ↑ 0 1 0 1 Reset
0 ↑ 1 0 1 0 Set
0 ↑ 1 1 q' q' Toggle
Truth Table 9: J K Flip Flop
Verilog File Name: jk_ff.v
//Async JK Flip Flop
module jk_ff( jk , clk , reset , q ,qb );
input [1:0] jk;
input clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (jk)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = ~q;
endcase
qb = ~q;
end
endmodule

PART-A: NON-INTERFACING 24 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
Verilog Testbench File Name: jk_ff_test.v
`timescale 1ns/1ps
module jkflip_tb;
reg clk, rst;
reg [1:0] jk;
wire q, qb;

jk_ff uut ( .clk(clk), .reset(rst), . jk(jk), .q(q), .qb(qb));

initial
begin
clk = 0; rst=1; jk=2'b00;
end
always
#5 clk=~clk;
initial
begin
#10; rst=0;
#10 jk = 2'b10;
#10 jk = 2'b00;
#10 jk = 2'b01;
#10 jk = 2'b11;
#40 jk = 2'b10;
#10 jk = 2'b00;
#10;
end
initial #120 $finish;
initial $monitor ($time," %b %b %b ---> %b ",clk , rst , jk, q
,qb);
endmodule

Waveform 9: J K Flip Flop

0 0 1 00 ---> 0 1
5 1 1 00 ---> 0 1
10 0 0 00 ---> 0 1
15 1 0 00 ---> 0 1
20 0 0 10 ---> 0 1
25 1 0 10 ---> 1 0
30 0 0 00 ---> 1 0
35 1 0 00 ---> 1 0
40 0 0 01 ---> 1 0
45 1 0 01 ---> 0 1
50 0 0 11 ---> 0 1
55 1 0 11 ---> 1 0
60 0 0 11 ---> 1 0
65 1 0 11 ---> 0 1
70 0 0 11 ---> 0 1
75 1 0 11 ---> 1 0
80 0 0 11 ---> 1 0
85 1 0 11 ---> 0 1
90 0 0 10 ---> 0 1
95 1 0 10 ---> 1 0
100 0 0 00 ---> 1 0
105 1 0 00 ---> 1 0
110 0 0 00 ---> 1 0
115 1 0 00 ---> 1 0
Stopped at time : 120.000 ns
PART-A: NON-INTERFACING 25 VK
Transcript 8: JK Flip Flop
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
10. D Flip Flop

d q

D Flip Flop outputs

inputs
qb
rst

clk
Figure 10: Block Diagram of D Flip Flop

Inputs Outputs
rst clk d q qb Action
1 ↑ X q qb No Change
0 ↑ 0 0 1 Reset
0 ↑ 1 1 0 Set
Truth Table 10: D Flip Flop

Verilog File Name: d_ff.v

//Async D Flip Flop
module d_ff( d , clk , reset , q ,qb );
input d, clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb=~q;
end
else
begin
q = d;
qb=~q;
end
endmodule

PART-A: NON-INTERFACING 26 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

Verilog Testbench File Name: d_ff_test.v

module dflip_tb;
reg clk, rst, d;
wire q, qb;
d_ff uut ( .clk(clk), .reset(rst), . d(d), .q(q), .qb(qb));
initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

initial
begin
#10; rst=0;
#10 d = 0;
#10 d = 1;
#10
#10 d = 0;
#10 d = 1;
#40;
end
initial #100 $finish;
initial $monitor ($time," %b %b %b ---> %b ",clk , rst , d, q ,qb);
endmodule

Waveform 10: D Flip Flop

0 0 1 x ---> 0 1
5 1 1 x ---> 0 1
10 0 0 x ---> 0 1
15 1 0 x ---> x x
20 0 0 0 ---> x x
25 1 0 0 ---> 0 1
30 0 0 1 ---> 0 1
35 1 0 1 ---> 1 0
40 0 0 1 ---> 1 0
45 1 0 1 ---> 1 0
50 0 0 0 ---> 1 0
55 1 0 0 ---> 0 1
60 0 0 1 ---> 0 1
65 1 0 1 ---> 1 0
70 0 0 1 ---> 1 0
75 1 0 1 ---> 1 0
80 0 0 1 ---> 1 0
85 1 0 1 ---> 1 0
90 0 0 1 ---> 1 0
95 1 0 1 ---> 1 0
Stopped at time : 100.000 ns
Transcript 9: D Flip Flop
PART-A: NON-INTERFACING 27 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
11. T Flip Flop

t q

T Flip Flop outputs

inputs
qb
rst

clk
Figure 11: Block Diagram of T Flip Flop

Inputs Outputs
rst clk t q qb Action
1 ↑ X q qb No Change
0 ↑ 0 q qb No Change
0 ↑ 1 q' q' Toggle
Truth Table 11: T Flip Flop
Verilog File Name: t_ff.v
//Async T Flip Flop
module t_ff( t, clk, reset, q, qb );
input t, clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb=~q;
end
else
if (t)
begin
q = ~q;
qb = ~q;
end
endmodule

PART-A: NON-INTERFACING 28 VK
 5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

Verilog Testbench File Name:t_ff_test.v

module tflip_tb;
reg clk, rst, t;
wire q, qb;
t_ff uut ( .clk(clk), .reset(rst), . t(t), .q(q), .qb(qb));
initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

initial
begin
#10; rst=0;
#10 t = 0;
#10 t = 1;
#20
#10 t = 0;
#10 t = 1;
#40;
end
initial #100 $finish;
initial $monitor ($time," %b %b %b ---> %b ",clk , rst , t, q ,qb);
endmodule

Waveform 11: T Flip Flop

0 0 1 x ---> 0 1
5 1 1 x ---> 0 1
10 0 0 x ---> 0 1
15 1 0 x ---> 0 1
20 0 0 0 ---> 0 1
25 1 0 0 ---> 0 1
30 0 0 1 ---> 0 1
35 1 0 1 ---> 1 0
40 0 0 1 ---> 1 0
45 1 0 1 ---> 0 1
50 0 0 1 ---> 0 1
55 1 0 1 ---> 1 0
60 0 0 0 ---> 1 0
65 1 0 0 ---> 1 0
70 0 0 1 ---> 1 0
75 1 0 1 ---> 0 1
80 0 0 1 ---> 0 1
85 1 0 1 ---> 1 0
90 0 0 1 ---> 1 0
95 1 0 1 ---> 0 1
Stopped at time : 100.000 ns
Transcript 10: T Flip Flop

PART-A: NON-INTERFACING 29 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
CLOCK DIVIDER CONCEPT

Note:

FPGA frequency f=4MHz

𝑓
Clock division = = 1 Hz i.e. T=1 sec
222
// initialization and declaration of input and output variables
input clk;
reg [31:0]counter;
wire clk_div;
always@(posedge clk)
begin
counter = counter +1;
end
assign clk_div=counter[21];
// clock pulse of count1[21] to specify the delay of 1 Sec.
always@(posedge clk_div, posedge clr/rst)
// body of the Program

PART-A: NON-INTERFACING 30 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru
12. BCD Synchronous Reset 4bit Counter

BCD Synchronous Reset 4

rst bcd_out
4bit Counter outputs
inputs

clk
Figure 12: Block Diagram of BCD Synchronous Reset 4bit Counter

Verilog File Name: bcd_counter_sync_4bit.v

// BCD synchronous reset 4bit counter
module bcd_sync ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end
always @(posedge clk)
if(rst)
count = 4'd0;
else if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule

Verilog Testbench File Name: bcd_counter_sync_4bit_test.v

module count4bit_tb;
reg rst, clk;
wire [3:0] count;

bcd_sync uut ( .rst(rst), .clk(clk), .count(count));

initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

PART-A: NON-INTERFACING 31 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

initial
begin
#5; rst=0;
#105;
#10; rst=1;
#15; rst=0;
#30;
#2; rst=1;
#10;
end

endmodule

Waveform 12: BCD Synchronous Reset 4bit Counter

PART-A: NON-INTERFACING 32 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

13. Binary Synchronous Reset 4bit Counter

4
clk1 q0
4
clk2 q1
Binary Synchronous Reset 4
clk3 q2
4bit Counter 4
clk4 q3
inputs outputs

rst
Figure 13: Block Diagram of Binary Synchronous Reset 4bit Counter

Verilog File Name: bin_counter_sync_4bit.v

// Binary synchronous reset 4bit counter
module bin_cnt(clk1,clk2,clk3,clk4,rst, q1,q2,q3,q4);

input clk1,clk2,clk3,clk4,rst;
output reg [3:0]q1=4'd0;
output reg [3:0]q2=4'd0;
output reg [3:0]q3=4'd0;
output reg [3:0]q4=4'd0;

always@(posedge clk1)
begin
if(rst==1)
q1=4'd0;
else
q1=q1+1'b1;
end

always@(posedge clk2)
begin
if(rst==1)
q2=4'd0;
else
q2=q2+1'b1;
end

always@(posedge clk3)
begin
if(rst==1)
q3=4'd0;
else
q3=q3+1'b1;
end

always@(posedge clk4)
begin
if(rst==1)
q4=4'd0;
else
q4=q4+1'b1;
end
endmodule

PART-A: NON-INTERFACING 33 VK
5TH SEM, HDL Lab, 18ECL58 2020-21 DEPT. E&C, CEC, Bengaluru

Verilog Testbench File Name: bin_counter_sync_4bit_test.v

module bin_tb;
reg clk1,clk2,clk3,clk4;
reg rst;
wire [3:0]q1,q2,q3,q4;
bin_cnt uut (.clk1(clk1), .clk2(clk2), .clk3(clk3), .clk4(clk4),
.rst(rst), .q1(q1), .q2(q2), .q3(q3), .q4(q4));

initial
begin
rst=1; #10;
clk1 = 0;
clk2 = 0;
clk3 = 0;
clk4 = 0;
rst = 0;
end

always #10 clk1=~clk1;

always #20 clk2=~clk2;
always #40 clk3=~clk3;
always #80 clk4=~clk4;

endmodule

Waveform 13: Binary Synchronous Reset 4bit Counter

PART-A: NON-INTERFACING 34 VK