Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.1 SOP and POS

AIM: To reduce SOP and POS expression and implement using universal gates.

Expressions: f(x, y, z) = ∑ m(0, 3, 4, 7)

F(x, y, z) = ∏ M(0, 1, 3, 5)

APPARATUS: IC 7400, IC 7402, power supply, breadboard, wires, LED’S.

All the experiments are performed using Logisim online simulator.

THEORY: K-map is a graphical method to reduce the logical expression. Two variable k-
map requires 2^2 = 4 cells to represent the logic function.

Three variable k-map requires 2^3 = 8 cells to represent the logic function.
Four variable k-map requires 2^4 = 16 cells to represent the logic function.

In the standard representation of logic functions we use SOP and POS forms. 1) SOP (Sum Of
Product): Sum Of Product is realized by AND-OR configuration, in which first level is AND and
second level is OR. This AND-OR configuration is equivalent to NAND-NAND configuration
and can be implemented using only one type of gates i.e. NAND. Each individual term of standard
SOP is called as minterm.

2) POS (Product Of Sum): Product Of Sum is realized by OR-AND configuration,

in which first level is OR and second level is AND. This OR-AND configuration is
equivalent to NOR-NOR configuration and can be implemented using only one
type of gates i.e. NOR. Each individual term of standard POS is called as maxterm.

PROCEDURE:

a. As per the logic diagram, implement the circuit.

b. Apply power supply to the respective terminals
c. Give the input in various combinations of 1’s and 0’s.
d. Observe the output in each case
CONCLUSION: K-map minimization gives optimum solution. SOP expression
can be implemented using only NAND gates and POS expression can be
implemented using only NOR gates.

SOP :
POS :
Name : JHA PRAMNAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.2
Full Adder
AIM:To design and implement full adder using logic gates.

APPARATUS: IC 7486, IC 7432, IC7408, power supply, breadboard, wires, LED’S. All
the experiments are performed using Logisim online simulator.

THEORY: Half-Adder: A combinational logic circuit that performs the addition of two data bits,
A and B, is called a half-adder. Addition will result in two output bits; one of which is the sum
bit,S, and the other is the carry bit, C. The Boolean functions describing the half-adder are:

Sum = A ⊕ B Carry = A B
Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This
carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two
data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing
the full-adder are:
Sum= A ⊕ B ⊕C
Carry=A B + B Cin + A Cin
The difference between a half-adder and a full-adder is that the full-adder has three inputs and
two outputs, whereas half adder has only two inputs and two outputs. The first two inputs are A
and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string
eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the
next.

FULL ADDER TRUTH TABLE:

 Input Output

A B Cin Sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

BOOLEAN EXPRESSIONS:

Sum= A B CCarry=A B + B Cin + A Cin

PROCEDURE:

As per the circuit diagram, implement the given function

a. Apply power supply to the respective terminals

b. Give the select input in various combinations of 1’s and 0’s.
c. Observe the output in each case
CONCLUSION: Two binary bits and the carry from previous addition is added using full adder.
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.3
Implement the given function using Multiplexer.
AIM: - To implement the function using Multiplexer.

APPARATUS: IC74151(8: 1 Multiplexer), IC7404 (NOT Gate), power supply, breadboard,

wires, LED’S.

All the experiments are performed using Logisim online simulator

PROBLEM STATEMENT: F(W,X,Y,Z)=∑m(0,1,2,4,9,15)+D(6,14) Implement the

function using 8:1 Multiplexer.

THEORY: A Multiplexer or data selector is a logic circuit that accepts several data inputs and
allow only one of them at a time to get through the output. The routing of the desired data input
to the output is controlled by select inputs.
S0 S1 S2 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
 Internal diagram of 4 :1 Multiplexer.

Y=S 1 S 0D0+S 1S 0D 0+S 1S 0D 0+S 1S 0D 0

Above fig shows 4 input multiplexer with data inputs D0,D1,D2,D3 , and data select input s
S0,S1.The logic levels applied to S0,S1 inputs, determine which and gate is enabled ,so that its
data input passes through the OR gate to the output .

Applications of Multiplexer.
● Logic function generator.
 ● Parallel to Serial Data converter.
● Multiplexing seven segment Display

PROCEDURE:

e. As per the circuit diagram, implement the given function.

f. Apply power supply to the respective terminals
g. Give the select input in various combinations of 1’s and 0’s.
h. Observe the output in each case
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.4
Binary to Gray code Conversion
AIM:The purpose of this experiment is to design a 4-bit Binary to Gray code converter using
exclusive-OR gates

APPARATUS: IC 7486, power supply, breadboard, wires, LED’S. Experiment performed using
Logisim Software.

THEORY:

The input to the 4-bit binary-to-Gray-code converter circuit is a 4-bit binary and the output is a
4bit Gray code. There are 16 possible combinations of 4-bit binary input and all of them are valid.
Hence no don’t care. The 4-bit binary and the corresponding Gray code are shown in the
conversion table. From the conversion table, we observe that the expression for the outputs G4,
G3, G2, and G1 are as follows:

The minimal expressions for the outputs obtained from the K -map are:
PROCEDURE:

1. Choose the IC to use in the experiment – place the component on the breadboard.

2. Connect the inputs of the IC to the logic sources (A, B) and its output to the logic indicators (S,
C) – make the wire connections between the various components.
3. Apply various input combinations and observe output for each one – use the DIP switches to
apply various input combinations and note the LED indicators.

4. Verify the truth table for each input/output combination.

5. Exit the experiment when done – use the “Close” button to exit.

RESULT:

Students are able to choose the components in a realistic way with the possibility of choosing the
wrong components for a given experiment and also with the possibility of making wrong wire
connections. The simulator will check the connections and report with a pop-up, in case any error
in the connection exists, before running the simulation.

Students will learn the concepts of the Digital Electronics Lab by performing hands on experiments
in this virtual lab and understanding the basic concepts of the topic without having to worry about
damaging the components and learning via experimentation.
CONCLUSION: Code conversion is implemented using Logisim and the truth table is verified.
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.5
Implementation of Mod- 6 counter
AIM: To Design & implement Mod- 6 (Asynchronous) counter using JK Flip-flop.

APPRATUS: IC 7476, IC 7400, bread board, connecting wires, power supply, LED.

All the experiments are performed using Logisim online simulator

THEORY: Asynchronous Counter-

A binary ripple/ asynchronous counter consists of a series connection of

complementing flip-flops, with the output of each flip-flop connected to the clock input of the
next higher-order flip-flop. In asynchronous counter all flip-flops are not clocked
simultaneously. Logic circuits used in these counters are simple even for a greater number of
states. Main drawback of these counters is their low speed as the clock is propagated through
number of flip-flops before it reaches last flip-flop.

Synchronous counter-
When counter is clocked such that each flip-flop in the counter is triggered at the same time,
the counter is called Synchronous counter. In this type there is no connection between output
of first flip-flop and clock input of the next flip-flop. In this counter all the flip-flops are
clocked simultaneously. Its design involves complex logic circuit as number of states
increases. As clock is simultaneously given to all flip-flops there is no problem of propagation
delay. Hence, they are preferred when number of flip-flops increases in the given design.

Mod counters-
Fig. shows basic 3-bit ripple counter. In its basic form it is a Mod-8 binary counter which
count in sequence from 000 to 111. However, the presence of NAND gate will alter this
sequence as follows:
1. The NAND gate output is connected to the asynchronous RESET inputs of each flip-
flop. As long as the NAND output is HIGH, it will have no effect on the counter. When it
goes LOW, it will reset all flip-flops so that counter immediately goes to the 000 state.

2. The inputs for the NAND gate are the outputs of the B & C flip-flops, and so the
NAND output will go LOW whenever QB=QC = 1. This condition will occur when the
counter goes from the 101 state to the 111 state. The LOW at the NAND output will
immediately reset the counter to the 000 state. Once the flip-flops have been reset, the NAND
output goes back HIGH, since the QB=QC=1 condition no longer exists.

3. The counting sequence is 000 through 110 therefore, though the counter does go to
the 110 state, it remains there for only a few nanoseconds before it recycles to 000. Thus, we
can essentially say that the counter counts from 000 to 101 and then recycles to 000. Due to
this counter skips 110,111 states and it goes through only six different states, thus it is a MOD-
6 counter.

MOD-6 COUNTER
Truth Table:
Clock Q0 Q1 Q2
Pulse
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
Procedure:

a. Implement circuit as shown in figure on bread-board.

b. Connect +5v supply.

c. Observe output on LED’s.

Conclusion: Mod -6 counter output is observed on LED’s. Design of truncated counter is studied.
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.6
Implementation of Ring Counter
AIM: To design and implement Ring Counter (Synchronous) using D Flip-flop.

APPRATUS: IC7474, bread board, connecting wires, power supply, LED.

All the experiments are performed using Logisim online simulator.

THEORY: Ring Counter-

Fig. shows the logic diagram for 4-bit ring counter. As shown in the fig, the Q output of
each stage is connected to the D input of the next stage and the output of last stage is fed
back to the input of first stage. The CLR followed by PRE makes the output of first stage
to ‘1’ and remaining outputs are zero, i.e Q0 is one and Q1, Q2, Q3 are zero.

RING COUNTER-
The first clock pulse produces Q1=1 and remaining outputs are zero. According to the clock
pulses applied at clock input CLK, a sequence of four states is produced. These states are listed
in table-
Clock Q0 Q1 Q2 Q3
Pulse
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0

As shown in table, 1 is always retained in the counter and simply shifted around the ring
advancing one stage for each clock pulse. In this case 4 stages of flip-flops are used. So
a sequence of four states is produced and repeated.

The ring counter can be used for counting the number of pulses. The number of pulses
counted is read by noting which flip-flop is in state 1. No decoding circuitry id\s required.
Since there is one pulse at the output for each of the N clock pulses, this circuit is also
referred to as a divide-by-N counter or an N:1 scalar. Ring counters can be instructed for
any desired MOD number, that is MOD N ring counter requires N flip-flops.

Johnson / Twisted Ring / Switch Tail Counter-

In a Johnson counter, the Q output of each stage of flip-flop is connected to the D input
of the next stage. The single exception is that the complement output of the last flip-
flop is connected back to the D input of the first flip-flop as fig.
Truth Table-

Clock QA QB QC QD
Pulse
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

PROCEDURE:

a. Implement circuit as shown in figure on bread-board.

b. Connect +5v supply.

c. Observe output on LED’s.

CONCLUSION: Ring counter is implemented using D flipflop. The persetted one follows
circular path and makes the ring.
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.7

Implementation Half Subtractor using Verilog

AIM:To simulate half subtractor using Verilog.

APPRATUS: EDA Playground online Verilog Simulator.

THEORY: A Half Subtractor is a combinational circuit that subtracts two bits and

produces two bits as output i.e. Difference and Borrow. Here is a Verilog module for a

half-subtractor:

Code for Half Subtractor

module

halfsubtractor(a,b,diff,borrow

);

input a,b;

output diff,borrow;

wire diff,borrow;

assign diff = a^b; // diff bit

assign borrow = (~a&b); //borrow bit

endmodule

The module half subtractor declares four ports, of which two are input and two are output
ones. Each port is a signal path that is only one bit wide. The module is implemented by
a pair of logic gates, an exclusive-or gate (xor) that determines the sum, and an and gate
that determines the borrow.

Non-blocking assignment & Blocking assignment: A simple explanation would be that a

nonblocking assignment (<=) actually is used when the order of assignment does not
matter (or rather not defined) and the statements need to be concurrent in execution.
These assignments are also useful in specifying the `TICK delay for flops with ease
without blocking concurrent statements hence named non-blocking. The blocking
assignment (=) is used when we need the operations to follow one after the other within
a block (from begin to end).

Wire and reg: The basic difference between wire and register is that a wire needs to be
‘driven’ at all times (driven can be either from a register or through a Boolean assign
statement that continuously keeps assigning values) and a reg stores the values when
changed. For example, in the Dflipflop code we need q to be a reg because it is not being
‘driven’ continuously and needs to store values between clock edges (positive) i.e. in the
period between the edges the value needs to be stored. On the other hand, in the code of
halfsubtractor, the difference being the output of a combinatorial circuit is continuously
driven. Hence it is a wire.

Testbench for Half Subtractor

// Code your testbench here

// or browse Examples

module main;

reg a,b;

wire diff, borrow;

halfsubtractor sub(a,b,diff,borrow);

initial

begin

$monitor($time,"a=%b,b=%b,diff=%b,borrow=%b",a,b,diff,borrow);
 #5 a=0;b=0;

#5 a=0;b=1;

#5 a=1;b=0;

#5 a=1;b=0;

#5 $finish;

end

initial

begin

$dumpvars(0,main);

$dumpfile("my.vcd");

end

endmodule

The $monitor(), $finish() Verilog Tasks and Time Progression Verilog is a discrete-event
simulation language, and the progression of time determines when events may occur in
the system being simulated. The $monitor argument $time outputs the current simulation
time. In Verilog, time is modeled in discrete time steps with respect to a given unit of
time. $time is an integer variable. The $monitor string argument says to output the values
of the four variables in binary.

The initial begin keywords, designate what Verilog should do at simulation $time = 0.
We specify all initializations in the initial blocks. Here the first executable statement is
$monitor, which generates printed output, in a fashion similar to a printf statement in C).
Unlike C, however, the output from $monitor is generated whenever any of the input
variables changes value. The next statement initializes the two 1-bit registers a and b to
zero. This will occur at simulation time zero. The next line begins with a delay prefix
“#10.” This requires that the interpreter has to “wait” ten simulation time steps before
executing the rest of the statement. That is, after delaying until simulation time 10,
register b will be set to one. Finally, the last statement “$finish,” terminates the simulation
and halts Verilog.
OUTOUT IN EDA PLAYGROUND :
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.8
Implementation of Decoder using Verilog
AIM: To simulate 2:4 Decoder using Verilog.

APPRATUS: EDA Playground online Verilog Simulator.

THEORY: Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 noutput
lines. One of these outputs will be active High based on the combination of inputs present. The
outputs of the decoder are nothing but the min terms of ‘n’ input variables lines. Here is a Verilog
module for a 2:4 Decoder:

module decoder2to4(x,y);

input [1:0]x;

output [3:0]y;

reg[3:0] y;

always @(x)

case(x) //case statement. Check all the 4 combinations.

2'b00: y=4'b0001;

2'b01: y=4'b0010;

2'b10: y=4'b0100;

2'b11: y=4'b1000;

endcase

endmodule
Testbench for 2:4 Decoder

module main;

reg [1:0]x;

wire [3:0]y;

decoder2to4 test(x,y);

initial

begin

$monitor($time,"x=%b,y=%b",x,y);

#5 x=2'b00;

#5 x=2'b01;

#5 x=2'b10;

#5 x=2'b11;

#5 $finish;

end

initial

begin

$dumpvars(0,main);

$dumpfile("my.vcd");

end

endmodule

Numeric Constants in Verilog:

In Verilog constants are specified in the traditional form of a series of digits with or without a
sign, but also in the following form
<size><base format><number>

Where <size> contains decimal digits that specify the size of the constant in the number of bits.
The <size> is optional. The <base format> is the single character “’ ” followed by one of the
following characters b, d, o and h, which stand for binary, decimal, octal and hexadecimal,
respectively. The <number> part contains digits which are legal for the <base format>.

Some examples:

549 // decimal number

’h08FF // 16-bit hexadecimal number

4’b11 // 4-bit binary number 11 (0011)

3’b10x // 3-bit binary number with least significant bit unknown/don’t care

12’o1345 // 12-bit octal number

5’d3 // 5-bit decimal number 3 (00011)

-4’b11 // 4-bit two’s complement negation of binary number 11 (1101)

-4’d3 // 4-bit value decimal number -3 in two’s complement (1101)

always and initial Verilog Threads:

There are two types of threads: the initial threads and the always ones. An initial thread is specified
as an initial begin . . . end block and it is executed once at $time = 0 (at the beginning of simulation).
We use initial threads to initialize system variables and to drive the simulation procedure from the
top-level module. initial threads complete as soon as the last (behavioral) statement in their body
is executed. initial statements are not synthesizable by the backend of an integrated design
automation system. This means that no actual hardware can be synthesized out of statements which
are preceded by initial. The always keyword, as in always begin . . . end, introduces an “always”
thread which continuously repeats its body in an infinite loop. As before the begin and end
keywords define the thread’s body. always specifies that the thread loops
forever. When the last statement in the body is reached, thread execution starts over at the top of
the body. always can (and in most cases should) be controlled by simulation time delays. These
delays can be specified either as an explicit number of clock units the thread must wait or as
events which will cause the thread to resume execution as soon as they take place.

CONCLUSION: The Verilog code for decoder is written and output is verified. Numeric
constant and always Verilog thread is studied.

OUTPUT IN EDA PLAY GROUND :

Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO.9

Implementation of D Flipflop using Verilog

AIM: To simulate D Flipflop using Verilog.

APPRATUS: EDA Playground online Verilog Simulator.

THEORY: Flipflop is used to store one bit of information. In case of D flipflop output is equal

to input with some delay at every active edge of the clock. Here is a Verilog module for D flipflop.

Code for D Flipflop :

DESIGN CODE:-

module dff(clk,reset,d,q,qb);

input clk;

input reset;

input d;

output q;

output qb;

reg q;

assign qb=~q;

always @(posedge clk or posedge reset)

 begin

if(reset)begin

q<=1'b0;

end else begin

q<=d;

end

end

endmodule

Test Bench for D flipflop

module test;

reg clk;

reg reset;

reg d;

wire q;

wire qb;

dff DFF(clk,reset,d,q,qb);

initial clk=1'b0;

always#1 clk=~clk;

initial

begin

reset=1'b1;

d=1'bx;

#2 reset=1'b0;

#3 d=1'b1;
 #10$finish;

end

initial

begin

$dumpfile("dff.vcd");

$dumpvars(0,test);

$monitor($time,"d=%b,reset=%b,q=%b,qb=%b",d,reset,q,qb);

end

endmodule

Event Lists in Verilog:

In Verilog we can precede any behavioral statement by an event specification list as follows:
always @(A or B or C or negedge CLK or posedge Reset ) begin ... #5 D = B; /* Time delay for
5 units */ ... end The expression @( ... ) above is called a sensitivity list and it is an event specifier.
Statements preceded by a sensitivity list suspend execution until the event specifier’s condition
is satisfied. In @( A or B or C ... ) of the example above, the event is “any change in the value of
variables A or B or C.” This is called a “level-sensitive” specification and it will resume the
execution of the always block as soon as any of the listed variables change signal value. In the
@( ... ) line of the example above the sub-expression “negedge CLK or posedge Reset ” specifies
the event “the value of the CLK signal takes the high-to-low transition (falling edge) or the value
of the Reset signal takes the low-to-high transition (rising edge)”. This is called an “edge-
triggered” specification and it is most useful in synchronous sequential circuits, where a clock
signal triggers the modification of storage elements, such as, Flip-Flop circuits.

CONCLUSION: The Verilog code for D flipflop is written and output is verified. Event lists in
Verilog is studied.
OUTPUT IN EDA PLAYGROUND :
Name : JHA PRANAV PRAMOD

Roll No : 17

Subject: Digital Electronics

EXPT.NO. 10
Implementation of 4-Bit counter using Verilog
AIM:To simulate 4-Bit counter using Verilog.

APPRATUS: EDA Playground online Verilog Simulator.

THEORY: Counter is used to count the number of clock pulses. 4-Bit counter counts 16 states

from 0 to 15. Here is a Verilog module for 4-Bit counter.

Code for 4-Bit Counter

module counter(clear,clock,count);

input clear,clock;

output reg[3:0] count;

always@(negedge clock)

if(clear)

count<=0;

else

count<=count+1;

endmodule
Test Bench for Counter
module test_counter;

reg clk,clr;

wire[3:0]out;

counter CNT (clr,clk,out);

initial clk=1'b0;

always #5 clk=~clk;

initial

begin

clr=1'b1;

#15 clr=1'b0;

#200 clr=1'b1;

#10 $finish;

end

initial

begin

$dumpfile("counter.vcd");

$dumpvars(0,test_counter);
 $monitor($time,"count:%d",out);

end

endmodule

CONCLUSION: The Verilog code for D flipflop is written and output is verified. Event lists in
Verilog is studied.

OUTPUT IN EDA PLAYGROUND :