Von Neumann Model and ISA

ABV-IIITM, Gwalior
Odd Semester 2022-23
The Stored Program Computer
 1943: ENIAC (Electronic Numerical Integrator and Computer)
 Presper Eckert and John Mauchly -- first general electronic computer.
(or was it John V. Atanasoff in 1939?)
 Hard-wired program -- settings of dials and switches.
 1944: Beginnings of EDVAC (Electronic Discrete Variable Automatic Computer)
 among other improvements, includes program stored in memory
 1945: John von Neumann
 wrote a report on the stored program concept,
known as the First Draft of a Report on EDVAC
 The basic structure proposed in the draft became known
as the “von Neumann machine” (or model).
 a memory, containing instructions and data
 a processing unit, for performing arithmetic and logical operations
 a control unit, for interpreting instructions

For more history, see http://www.maxmon.com/history.htm

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Basic Elements of a Computer
 Pre-requisites:
 Combinational circuits
 Sequential circuits
 With them, we can build
 Decision elements
 Storage elements
 Basic elements of a computer

 To get a task done by a computer we need

 Computer
 Data
 Program: A set of instructions
 Instruction: the smallest piece of work in a computer
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The Von Neumann Model
 Let’s start building the computer

 In order to build a computer we need a model

 John von Neumann proposed a fundamental model that consists

of the following five parts:

 Memory
 Processing unit
 Input
 Output
 Control unit

 We will consider two examples of the von Neumann model

 LC-3
 MIPS (Microprocessor without Interlocked Pipeline Stages)

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The Von Neumann Model
MEMORY
Mem Addr Reg
Mem Data Reg

INPUT PROCESSING UNIT OUTPUT

Keyboard, Monitor,
Mouse, ALU TEMP Printer,
Disk… Disk…

CONTROL UNIT

PC or IP Inst Register

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The Von Neumann Model
MEMORY
Mem Addr Reg
Mem Data Reg

INPUT PROCESSING UNIT OUTPUT

Keyboard, Monitor,
Mouse, ALU TEMP Printer,
Disk… Disk…

CONTROL UNIT

PC or IP Inst Register

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Memory
 The memory stores
 Data
 Programs

 The memory contains bits

 Bits are grouped into bytes (8 bits) and words (e.g., 8, 16, 32 bits)

 How the bits are accessed determines the addressability

 E.g., word-addressable
 E.g., 8-bit addressable (or byte-addressable)

 The total number of addresses is the address space

 In LC-3, the address space is 216
 16-bit addresses
 In MIPS, the address space is 232
 32-bit addresses
 In x86-64, the address space is (up to) 248
 48-bit addresses

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Word-Addressable Memory
 Each data word has a unique address
 In MIPS, a unique address for each 32-bit data word
 In LC-3, a unique address for each 16-bit data word

Word Address Data MIPS memory

. . .

. . .

. . .
00000003 D1617A1C Word 3
00000002 13C81755 Word 2

00000001 F2F1F0F7 Word 1

00000000 89ABCDEF Word 0

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Byte-Addressable Memory
 Each byte has a unique address
 Actually, MIPS is byte-addressable
 LC-3b (updated version of LC-3) is byte-addressable, too

Byte Address Data MIPS memory

. . .
of the Word

. . .

. . .
0000000C D 1 61 7A 1 C Word 3
00000008 1 3 C8 17 5 5 Word 2

00000004 F 2 F1 F0 F 7 Word 1
How are these four bytes
00000000 8 9 addressed?
AB CD EF Word 0
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Big Endian vs Little Endian

 Little Endians broke their eggs on the little end of the egg

 Big Endians broke their eggs on the big end of the egg

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Big Endian vs Little Endian
Big Endian Little Endian
Byte Address Byte
Address of the Address

. . .
. . .
Word

. . .
C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
(Most Significant Byte) (Least Significant Byte)
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Big Endian vs Little Endian
Big Endian Little Endian
Byte Word Byte
Does
Address thisAddress
really matter?
Address

. . .
. . .

. . .
Answer: No, it is a convention
C D E F C F E D C

8 9 A B 8 B A 9 8
Qualified answer: No, except when one big-
endian
4 5system
6 and
7 one 4little-endian
7 6system
5 4
have
0 to
1 share
2 data
3 0 3 2 1 0
MSB LSB MSB LSB
(Most Significant Byte) (Least Significant Byte)
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Accessing Memory: MAR and MDR
 There are two ways of accessing memory
 Reading or loading
 Writing or storing

 Two registers are necessary to access memory

 Memory Address Register (MAR)
 Memory Data Register (MDR)

 To read
 Step 1: Load the MAR with the address
 Step 2: Data is placed in MDR

 To write
 Step 1: Load the MAR with the address and the MDR with the data
 Step 2: Activate Write Enable signal

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The Von Neumann Model
MEMORY
Mem Addr Reg
Mem Data Reg

INPUT PROCESSING UNIT OUTPUT

Keyboard, Monitor,
Mouse, ALU TEMP Printer,
Disk… Disk…

CONTROL UNIT

PC or IP Inst Register

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Processing Unit
 The processing unit can consist of many functional units

 We start with a simple Arithmetic and Logic Unit (ALU),

which executes computations
 LC-3: ADD, AND, NOT (XOR in LC-3b)
 MIPS: add, sub, mult, and, nor, sll, slr, slt…

 The ALU processes quantities that are referred to as words

 Word length in LC-3 is 16 bits
 In MIPS it is 32 bits

 Temporary storage: Registers

 E.g., to calculate (A+B)*C, the intermediate result of A+B is
stored in a register

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Registers
 Memory is big but slow

 Registers
 Ensure fast access to operands
 Typically one register contains one word

 Register set or file

 LC-3 has 8 general purpose registers (GPR)
 R0 to R7: 3-bit register number
 Register size = Word length = 16 bits
 MIPS has 32 registers
 Register size = Word length = 32 bits

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MIPS Register File
Name Register Number Usage
$0 0 the constant value 0
$at 1 assembler temporary
$v0-$v1 2-3 function return value
$a0-$a3 4-7 function arguments
$t0-$t7 8-15 temporary variables
$s0-$s7 16-23 saved variables
$t8-$t9 24-25 temporary variables
$k0-$k1 26-27 OS temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 function return address

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The Von Neumann Model
MEMORY
Mem Addr Reg
Mem Data Reg

INPUT PROCESSING UNIT OUTPUT

Keyboard, Monitor,
Mouse, ALU TEMP Printer,
Disk… Disk…

CONTROL UNIT

PC or IP Inst Register

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Input and Output
 Many devices can be used for input and output

 They are called peripherals

 Input
 Keyboard
 Mouse
 Scanner
 Disks
 Etc.
 Output
 Monitor
 Printer
 Disks
 Etc.

 In LC-3, we consider keyboard and monitor

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The Von Neumann Model
MEMORY
Mem Addr Reg
Mem Data Reg

INPUT PROCESSING UNIT OUTPUT

Keyboard, Monitor,
Mouse, ALU TEMP Printer,
Disk… Disk…

CONTROL UNIT

PC or IP Inst Register

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Control Unit
 The control unit is similar to the conductor of an orchestra

 It conducts the step-by-step process of executing (every

instruction in) a program

 It keeps track of the instruction being executed with an

instruction register (IR), which contains the instruction

 Another register contains the address of the next

instruction to execute. It is called program counter (PC) or
instruction pointer (IP)

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 Programmer Visible (Architectural) State

M[0]
M[1]
M[2]
M[3] Registers
M[4] - given special names in the ISA
(as opposed to addresses)
- general vs. special purpose

M[N-1]
Memory Program Counter
array of storage locations memory address
indexed by an address of the current instruction

Instructions (and programs) specify how to transform

the values of programmer visible state
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The Von Neumann Model
MEMORY
Mem Addr Reg
Mem Data Reg

INPUT PROCESSING UNIT OUTPUT

Keyboard, Monitor,
Mouse, ALU TEMP Printer,
Disk… Disk…

CONTROL UNIT

PC or IP Inst Register

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Von Neumann Model: Two Key Properties
 Von Neumann model is also called stored program computer
(instructions in memory). It has two key properties:

 Stored program
 Instructions stored in a linear memory array
 Memory is unified between instructions and data
 The interpretation of a stored value depends on the control signals

 Sequential instruction processing

 One instruction processed (fetched, executed, completed) at a time
 Program counter (instruction pointer) identifies the current instruction
 Program counter is advanced sequentially except for control transfer
instructions

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LC-3: A Von Neumann Machine
Program
Counter

Control signals 8 General Purpose

Registers (GPR)
Data

Finite State Machine

(for Generating Control Signals)

Instruction
Register ALU: 2 inputs, 1 output

ALU operation

GateALU

Memory Data Keyboard

Register KBDR (data), KBSR (status)

Monitor
Memory Address 16-bit DDR (data), DSR (status)
Register addressable
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