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8086 Architecture

The document describes the architecture of the 8086 microprocessor. It has two main units: the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handles interfacing with external devices and memory, address generation, and instruction fetching. The EU decodes and executes instructions. The 8086 uses memory segmentation to divide the 1MB address space into multiple 64KB segments to extend addressing capabilities beyond 16-bits. Segmentation allows for code, data, and stacks to be placed in different segments of memory.

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0% found this document useful (0 votes)
122 views7 pages

8086 Architecture

The document describes the architecture of the 8086 microprocessor. It has two main units: the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU handles interfacing with external devices and memory, address generation, and instruction fetching. The EU decodes and executes instructions. The 8086 uses memory segmentation to divide the 1MB address space into multiple 64KB segments to extend addressing capabilities beyond 16-bits. Segmentation allows for code, data, and stacks to be placed in different segments of memory.

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shahid ali
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© © All Rights Reserved
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Eplain with suitable diagram architecture of 8086

microprocessor.

The architecture is divided into two units:

1. Bus Interface Unit (BIU) 2. Execution Unit (EU)

BUS INTERFACE UNIT (BIU)

 It provides the interface of 8086 to other devices.


 It operates w.r.t. Bus cycles. This means it performs various machine cycles
such as Memory Read, IO Write etc to transfer data with Memory and I/O
devices.
 It also generates the 20-bit physical address for memory access, fetches
instruction from memory, transfers data to and from the memory and IO.
 It supports Pipelining using the 6-byte instruction queue.
The main components of the BIU are as follows:
SEGMENT REGISTERS:

 CS Register: CS holds the base (Segment) address for the Code Segment.
All programs are stored in the Code Segment. It is multiplied by 10H (16d),
to give the 20-bit physical address of the Code Segment. CS register cannot
be modified by executing any instruction except branch instructions.

 DS Register: DS holds the base (Segment) address for the Data Segment. It
is multiplied by 10H (16d), to give the 20-bit physical address of the Data
Segment. Eg: If DS = 4321H then DS × 10H = 43210H è Starting address of
Data Segment.

 SS Register: SS holds the base (Segment) address for the Stack Segment. It
is multiplied by 10H (16d), to give the 20-bit physical address of the Stack
Segment.

 ES Register: ES holds the base (Segment) address for the Extra Segment. It
is multiplied by 10H (16d), to give the 20-bit physical address of the Extra
Segment.

Instruction Pointer (IP register): It is a 16-bit register. It holds offset of the next
instruction in the Code Segment. Address of the next instruction is calculated as CS x 10H
+ IP. IP is incremented after every instruction byte is fetched. IP gets a new value whenever
a branch occurs.

Address Generation Circuit: The BIU has a Physical Address Generation Circuit. It


generates the 20-bit physical address using Segment and Offset addresses using the
formula: Physical Address (20 bit) = Segment Address (16 bit) X 10H + Offset Address (16
bit)

Pipelining: It is a 6-byte FIFO RAM used to implement Pipelining. Fetching the next
instruction while executing the current instruction is called Pipelining. BIU fetches the
next “six instruction-bytes” from the Code Segment and stores it into the queue.
Execution Unit (EU) removes instructions from the queue and executes them.

Execution Unit (EU)

 It fetches instructions from the Queue in BIU, decodes and executes them.

 It performs arithmetic, logic and internal data transfer operations. It sends request
signals to the BIU to access the external module. It operates in synchronization
with T-States (clock cycles).

The main components of the EU are as follows:


a) General Purpose Registers: 8086 has four 16-bit general-purpose registers AX, BX, CX
and DX. These are available to the programmer, for storing values during programs. Each
of these can be divided into two 8-bit registers such as AH, AL; BH, BL; CL, CH and DL, DH.
Beside their general use, these registers also have some specific functions.

 AX Register (16-Bits): It holds operands and results during multiplication and


division operations. All IO data transfers using IN and OUT instructions use A
register (AL/AH or AX). It functions as accumulator during string operations.
 BX Register (16-Bits): It holds the memory address (offset address), in Indirect
Addressing modes.
 CX Register (16-Bits): It holds count for instructions like: Loop, Rotate, Shift
and String Operations.
 DX Register (16-Bits): It is used with AX to hold 32 bit values during
Multiplication and Division. It is used to hold the address of the IO Port in
indirect IO addressing mode.

b) Special Purpose Registers

 Stack Pointer (SP 16-Bits): It is holds offset address of the top of the Stack.
Stack is a set of memory locations operating in LIFO manner. SP is used with the
SS Register to calculate physical address for the Stack Segment. It used during
instructions like PUSH, POP, CALL, RET etc. During PUSH instruction, SP is
decremented by 2 and during POP it is incremented by 2.

 Base Pointer (BP 16-Bits): It holds the offset address of any location in the
stack segment. It is used to access random locations of the stack.

 Source Index (SI 16-Bits): It is normally used to hold the offset address for
Data segment but can also be used for other segments using Segment Overriding.
It holds offset address of source data in Data Segment, during String Operations.

 Destination Index (DI 16-Bits): It is normally used to hold the offset


address for Extra segment but can also be used for other segments using
Segment Overriding. It holds offset address of destination in Extra Segment,
during String Operations.

c) ALU (16-Bits): It has a 16-bit ALU. It performs 8 and 16-bit arithmetic and logic
operations.

d) Instruction Register and Instruction Decoder (Present inside the Control Unit): The
EU fetches an opcode from the queue into the Instruction Register. The Instruction
Decoder decodes it and sends the information to the control circuit for execution.
What are the advantages of memory segmentation of
8086.

1. It allows the memory addressing capacity to be 1 Mbyte even though the address
associated with individual instruction is only 16-bit.
2. It allows instruction code, data, stack, and portion of program to be more than 64
KB long by using more than one code, data, stack segment, and extra segment.
3. It facilitates use of separate memory areas for program, data and stack.
4. It permits a program or its data to be put in different areas of memory, each time
the program is executed i.e. program can be relocated which is very useful in
multiprogramming.

Memory Segmentation in 8086


Microprocessor
Segmentation is the process in which the main memory of the computer is
logically divided into different segments and each segment has its own base
address. It is basically used to enhance the speed of execution of the computer
system, so that the processor is able to fetch and execute the data from the memory
easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers
(mentioned below) called as Segment Registers.

 Code segment register (CS): is used for addressing memory location in the
code segment of the memory, where the executable program is stored.
 Data segment register (DS): points to the data segment of the memory
where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory
which is another data segment in the memory.
 Stack Segment Register (SS): is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to
store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as
to access one of the 1MB memory locations. The four segment registers actually
contain the upper 16 bits of the starting addresses of the four memory segments of
64 KB each with which the 8086 is working at that instant of time. A segment is a
logical unit of memory that may be up to 64 kilobytes long. Each segment is made
up of contiguous memory locations. It is an independent, separately addressable
unit. Starting address will always be changing. It will not be fixed.

Note that the 8086 does not work the whole 1MB memory at any given time.
However, it works only with four 64KB segments within the whole 1MB memory.

Below is the one way of positioning four 64 kilobyte segments within the 1M byte
memory space of an 8086.
Types Of Segmentation –

1. Overlapping Segment – A segment starts at a particular address and its


maximum size can go up to 64kilobytes. But if another segment starts along
with this 64kilobytes location of the first segment, then the two are said to
be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its
maximum size can go up to 64kilobytes. But if another segment starts before
this 64kilobytes location of the first segment, then the two segments are said
to be Non-Overlapped Segment.

Rules of Segmentation Segmentation process follows some rules as follows:

 The starting address of a segment should be such that it can be evenly


divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64
kB.
Advantages of the Segmentation The main advantages of segmentation are
as follows:

o It provides a powerful memory management mechanism.


o Data related or stack related operations can be performed in different
segments.
o Code related operation can be done in separate code segments.
o It allows to processes to easily share data.
o It allows to extend the address ability of the processor, i.e.
segmentation allows the use of 16 bit registers to give an addressing
capability of 1 Megabytes. Without segmentation, it would require 20
bit registers.
o It is possible to enhance the memory size of code data or stack
segments beyond 64 KB by allotting more than one segment for each
area.

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