18EI/BM/ML56

Model Question Paper -1 with effect from 2020-21(CBCS Scheme)

USN

Fifth Semester B.E. Degree Examination

VLSI Design
TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each MODULE.
02.
03.

Module – 1
(a) How moor’s law can be related to evolution of microelectronics? 4
(b) With neat diagram explain the fabrication of nMOS transistor. 10
Q.1
(c) Distinguish between CMOS and Bipolar technologies. 6
OR
Derive an expression for an nMOS inverter in non-saturation and saturation region. Draw the
(a) 10
relevant sketches.
What is body effect in MOS transistors and how it affects the MOS transistor threshold
Q.2 (b) 5
voltage?
(c) Derive the expression for transconductance of MOS transistor. 5
Module – 2
(a) Derive the pull up to pull down ratio for an nMOS inverter, driven through, one or more pass
10
Q.3 transistors.
(b) With relevant sketches analyze the different operating regions of CMOS inverter. 10
OR
(a) Define the sheet resistance. How the sheet resistance can be calculated for the MOS
10
Q.4 transistor and inverter?
(b) What are the problems associated with MOS transistor to drive large capacitive load?
What are the different techniques available to drive large capacitive loads? Obtain the 10
expression for the overall delay Td for cascaded inverters.
Module – 3
(a) Illustrate the stick diagram of one-bit shift register cell using CMOS design style with
10
Q.5 step by step procedure.
(b) What is the lambda-based design rules for the wires and transistors in nMOS and
CMOS technology? 10
 18EI/BM/ML56

OR
(a) Derive the following scaling factors:
(i) Gate Area Ag (ii) Gate Delay Td (iii) Maximum operating frequency f0 10
Q.6 (iv) Switching energy per gate Eg (v) Gate capacitance Cg
(b) What are the limitations of scaling in VLSI technology? Discuss the effect of any two
10
limitations of scaling.
Module – 4
(a) Draw the circuit diagram and stick diagram for 2 i/p NAND gate using NMOS and CMOS. 10
Q.7
(b) Design a general logic function block to generate any function of two variables (A,B)
10
using four way multiplexer.
OR
(a) Explain the general arrangement of a 4-bit arithmetic processor and basic bus architectures.
10
Q.8 (b) Illustrate the generation of two-phase clock signals using D flip flops along with its
waveforms. 6

(c) Describe the operation of active bus and passive bus arrangements for bus lines.
4
Module – 5
(a) Define regularity 2
Q.9 Write the expressions for a carry look ahead adders. Draw and explain the structure. 10
(b)
(c) Explain the serial parallel multiplier with D-flip-tlop and full adder.
8
OR
(a) Describe the operation of three transistor dynamic RAM cell and also write its stick
8
diagram
Q.10 (b) What are to be considered in the designer 's tool box for the chip design in CAD tools and explain
12
simulation?
 18EI/BM/ML56

Table showing the Bloom’s Taxonomy Level, Course Outcome and Programme
Outcome

Question Bloom’s Taxonomy Level Course Programme Outcome

attached Outcome
Q.1 (a) L1 CO1 PO1
(b) L2 CO1 PO1
(c) L2 CO1 PO1
Q.2 (a) L2 CO2 PO1, PO2
(b) L2 CO2 PO1, PO2
(c) L2 CO2 PO1, PO2
Q.3 (a) L3 CO2 PO1, PO2, PO3
(b) L3 CO2 PO1, PO2, PO3
Q.4 (a) L3 CO2 PO1, PO2, PO3
(b) L3 CO2 PO1, PO2, PO3
Q.5 (a) L3 CO3 PO1, PO2, PO3
(b) L1 CO2 PO1, PO2
Q.6 (a) L2 CO2 PO1, PO2
(b) L2 CO2 PO1, PO2
Q.7 (a) L2 CO3 PO1, PO2, PO3
(b) L3 CO3 PO1, PO2, PO3
Q.8 (a) L2 CO3 PO1, PO2, PO3
(b) L2 CO3 PO1, PO2
(c) L2 CO3 PO1, PO2
Q.9 (a) L1 CO4 PO1
(b) L2 CO4 PO1, PO2
(c) L2 CO4 PO1, PO2
Q.10 (a) L2 CO4 PO1, PO2
(b) L1 CO5 PO1, PO2, PO3

Lower order thinking skills

Bloom’s Remembering( Understanding Applying (Application):
Taxonomy knowledge):‫ܮ‬1 Comprehension): ‫ܮ‬2 ‫ܮ‬3
Levels Higher order thinking skills
Analyzing (Analysis): ‫ܮ‬4 Valuating (Evaluation): ‫ܮ‬5 Creating (Synthesis): ‫ܮ‬6
 18EI/BM/ML56
Model Question Paper -2 with effect from 2020-21(CBCS Scheme)
USN

Fifth Semester B.E. Degree Examination

VLSI Design
TIME: 03 Hours Max. Marks: 100

Note: 01. Answer any FIVE full questions, choosing at least ONE question from each MODULE.
02.
03.

Module – 1
(a) Identify a suitable VLSI technology for optimum speed and power performance. 4
(b) Describe with neat sketches, the fabrication of P – well CMOS inverter. 10
Q.1
(c) With neat sketches describe the working of enhancement mode transistor. 6
OR
(a) What are the aspects of MOS transistor threshold voltage? 8

Q.2 (b) Derive the expression for transconductance and output conductance of MOS transistor. 8
Draw the MOS transistor characteristics curve in enhancement mode and depletion
(c) 4
mode.
Module – 2
(a) Derive the pull up to pull down ratio for an nMOS inverter driven through another
8
nMOS inverter.
(b) Analyze the latch up in CMOS Circuits with relevant sketches and mention the 8
Q.3 remedies to overcome latch up.
(c) List the alternate forms of pull ups along with its characteristic graph. 4
OR
(a) Estimate the rise time and fall time of a CMOS inverter.
8

(b) Justify that BiCMOS inverters can drive large capacitive loads with lesser delay than
Q.4 compared to CMOS inverter with relevant sketches and graphs. 8

Explain the working of inverting super buffers? 4

(c)
Module – 3
(a) Draw the stick diagram of n-well based BiCMOS inverter. 6
Q.5 (b) Using nMOS design style draw the stick diagram of the Boolean equation X` A + BC
8
(c) What is the lambda-based design rules for the transistors in nMOS, pMOS and CMOS
6
technology?
 18EI/BM/ML56

OR
(a) Derive the following scaling factors:
(i) Gate capacitance per unit area Co
Q.6 (ii) Carrier density in channel Qon
10
(iii) Saturation current Idss
(iv) Switching energy per gate Eg
(v) Current density J
(b) Discuss the limitations of scaling with respect to following parameters.
(i) Substrate doping scaling factor 10
(ii) Limits of miniaturization
Module – 4
(a) Draw the circuit diagram and stick diagram for 2-i/p nor gate in nMOS and CMOS
Q.7 10
family
(b) Explain bus arbitration logic for n-line bus moving from unstructured design to
10
structured design.
OR
(a) Draw and describe the working of NMOS version of dynamic shift register. 6
Q.8
(b) Discuss the working of 4 x 4-barrel shifter with the neat circuit diagram and stick diagram. 8
(c) What are the general considerations in VLSI design methodology 6
Module – 5
(a) Implement a 4 bit ALU using a 4 bit adder 10
Q.9
Explain the 2's compliment multiplication using the Baugh-Wooley method.
(b) 10
OR
(a) Describe the read and write operations in static RAM with neat diagram. 10
(b) With the help of circuit diagram explain the operation of the following
Q.10 (i) JK Flipflop 10
(ii) D Flipflop
 18EI/BM/ML56

Table showing the Bloom’s Taxonomy Level, Course Outcome and Programme
Outcome

Question Bloom’s Taxonomy Level Course Programme Outcome

attached Outcome
Q.1 (a) L1 CO1 PO1
(b) L2 CO1 PO1
(c) L2 CO1 PO1
Q.2 (a) L2 CO2 PO1, PO2
(b) L2 CO2 PO1, PO2
(c) L2 CO2 PO1, PO2
Q.3 (a) L3 CO2 PO1, PO2, PO3
(b) L3 CO2 PO1, PO2, PO3
(c) L1 CO2 PO1
Q.4 (a) L3 CO2 PO1, PO2, PO3
(b) L3 CO2 PO1, PO2, PO3
(c) L2 CO2 PO1, PO2
Q.5 (a) L2 CO3 PO1, PO2, PO3
(b) L2 CO2 PO1, PO2
(c) L1 CO2 PO1, PO2
Q.6 (a) L2 CO2 PO1, PO2
(b) L2 CO2 PO1, PO2
Q.7 (a) L2 CO3 PO1, PO2, PO3
(b) L3 CO3 PO1, PO2, PO3
Q.8 (a) L2 CO3 PO1, PO2, PO3
(b) L2 CO3 PO1, PO2, PO3
(c) L1 CO3 PO1
Q.9 (a) L3 CO4 PO1, PO2, PO3
(b) L2 CO4 PO1, PO2
Q.10 (a) L2 CO4 PO1, PO2
(b) L2 CO5 PO1, PO2, PO3

Lower order thinking skills

Bloom’s Remembering( Understanding Applying (Application):
Taxonomy knowledge):‫ܮ‬1 Comprehension): ‫ܮ‬2 ‫ܮ‬3
Levels Higher order thinking skills
Analyzing (Analysis): ‫ܮ‬4 Valuating (Evaluation): ‫ܮ‬5 Creating (Synthesis): ‫ܮ‬6