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Mil Sil Pil Hil

- MIL, SIL, PIL, and HIL are stages of verification for model-based design approaches where a controller model is tested against a plant model before deployment to hardware - MIL uses controller and plant models in simulation to verify controller logic - SIL replaces the controller model with generated code while keeping the plant a model to test code implementability - PIL replaces the plant model with an embedded processor running the controller code to identify processor capability issues - HIL finally replaces the plant model with actual hardware to test the full system

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538 views6 pages

Mil Sil Pil Hil

- MIL, SIL, PIL, and HIL are stages of verification for model-based design approaches where a controller model is tested against a plant model before deployment to hardware - MIL uses controller and plant models in simulation to verify controller logic - SIL replaces the controller model with generated code while keeping the plant a model to test code implementability - PIL replaces the plant model with an embedded processor running the controller code to identify processor capability issues - HIL finally replaces the plant model with actual hardware to test the full system

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MIL, SIL, PIL, and HIL

MIL, SIL, PIL, and HIL


MIL, SIL, PIL, and HIL testing come in the verification part of the Model-Based Design
approach after you have recognized the requirement of the component/system you are
developing and they have been modeled at the simulation level (e.g. Simulink platform).
Before the model is deployed to the hardware for production, a few verification steps take
place which are listed below. Here, I am taking an example of designing a controller for a
DC motor and putting the code generated from the model of the Controller in a supported
System-on-Chip.
Model-in-the-Loop (MIL) simulation or Model-Based
Testing
First, you have to develop a model of the actual plant (hardware) in a simulation
environment such as Simulink, which captures most of the important features of the
hardware system. After the plant model is created, develop the controller model and verify
if the controller can control the plant (which is the model of the motor in this case) as per
the requirement. This step is called Model-in-Loop (MIL) and you are testing the controller
logic on the simulated model of the plant. If your controller works as desired, you should
record the input and output of the controller which will be used in the later stage of
verification.

https://www.mathworks.com/discovery/model-based-testing.html
Software-in-the-Loop (SIL) simulation
Once your model has been verified in MIL simulation, the next stage is Software-in-Loop(SIL),
where you generate code only from the controller model and replace the controller block with
this code. Then run the simulation with the Controller block (which contains the C code) and
the Plant, which is still the software model (similar to the first step). This step will give you an
idea of whether your control logic i.e., the Controller model can be converted to code and if it
is hardware implementable. You should log the input-output here and match it with what
you have achieved in the previous step. If you experience a huge difference in them, you may
have to go back to MIL and make necessary changes and then repeat steps 1 and 2. If you
have a model which has been tested for SIL and the performance is acceptable you can move
forward to the next step.

https://www.mathworks.com/help/ecoder/software-in-the-loop-sil-simulation.html
Processor-in-the-Loop (PIL) or FPGA-in-the-Loop
(FIL) simulation
The next step is Processor-in-the-Loop (PIL) testing. In this step, we will put the Controller
model onto an embedded processor and run a closed-loop simulation with the simulated
Plant. So, we will replace the Controller Subsystem with a PIL block which will have the
Controller code running on the hardware. This step will help you identify if the processor is
capable of running the developed Control logic. If there are glitches, then go back to your
code, SIL or MIL, and rectify them.
https://www.mathworks.com/help/ecoder/processor-in-the-loop.html

In the case of running the simulation on an FPGA instead of an embedded processor, the
simulation is called FPGA-in-the-Loop (FIL). See how to run FIL simulations using HDL
Verifier:
https://www.mathworks.com/help/hdlverifier/ug/fpga-in-the-loop-fil-simulation.html
Actual Hardware
Once your plant model has been verified using PIL, now you can replace the plant model with
the original hardware, say lab model and run a test. Let's say, it is a DC motor whose speed
controller is being designed and then the controller is in FPGA/processor which is now
interfaced to the DC motor by connecting the inputs and outputs/states at the right points of
sensors/transducers).

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