Functional Specification

Low Latency 10G Ethernet – MAC

Dynamic Generated Example Design

Chandra
Kean Harn Lim
Soon Chye Chan
Yung Jia Loh

22 September 2021Sep 07, 2015

Altera Corporation Confidential

Altera LL10GE-MAC Example Design Integration Specification

Table of Contents
1 Document Revision............................................................................................................................10
2 Introduction.......................................................................................................................................11
2.1 Example Design Objective..........................................................................................................11
2.2 Example Design Variants............................................................................................................11
2.3 Device Family Support...............................................................................................................12
2.4 Existing Example Design.............................................................................................................12
2.5 Example Design Quick Start Document......................................................................................12
2.6 Example Design Quick Start Video.............................................................................................12
2.7 Unified Reset Architecture.........................................................................................................13
2.7.1 Ideal Reset Flow.................................................................................................................13
2.7.2 Architecture to realize the ideal flow.................................................................................14
2.7.3 Analysis of the new reset architecture with respect to the customer issues.....................16
2.7.4 Backward compatibility......................................................................................................17
2.7.5 ACDS Plan...........................................................................................................................18
2.7.6 Practical considerations.....................................................................................................19
2.7.7 Points to be double-checked.............................................................................................19
3 User Flow...........................................................................................................................................20
3.1 Delivering the Example Design..................................................................................................20
3.2 Selecting IP/ED Parameters.......................................................................................................21
3.2.1 IP Parameters.....................................................................................................................23
3.2.2 Example Design Parameters..............................................................................................23
3.2.3 IP Parameter Compatibility with Example Design..............................................................29
3.3 Generating Example Design.......................................................................................................30
3.3.1 Generation Method...........................................................................................................30
3.3.2 Generation Output.............................................................................................................30
3.4 Simulating Example Design........................................................................................................31
3.4.1 Simulators Supported........................................................................................................31
3.4.2 Simulation Warning...........................................................................................................31
3.4.3 Simulation Testbench........................................................................................................32
3.5 Compiling Example Design using Quartus..................................................................................32
3.5.1 Compilation Warning.........................................................................................................33

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Altera LL10GE-MAC Example Design Integration Specification

3.6 Testing Example Design in Hardware.........................................................................................33

3.6.1 Example Design Hardware Setup.......................................................................................33
3.6.2 Hardware test cases description........................................................................................34
4 Functional Description: 10M/100M/1G/10G Ethernet Example Design............................................41
4.1 Software and Hardware Requirement.......................................................................................41
4.2 Feature......................................................................................................................................41
4.3 Clocking.....................................................................................................................................43
4.4 Reset..........................................................................................................................................45
4.5 Parameter Setting......................................................................................................................47
4.5.1 Example Design Parameters..............................................................................................47
4.5.2 PHY Pre-Set Parameters.....................................................................................................48
4.6 Interface Signaling.....................................................................................................................50
4.6.1 Clock & Reset.....................................................................................................................50
4.6.2 Avalon-MM Interface.........................................................................................................51
4.6.3 Avalon-ST Interface............................................................................................................51
4.6.4 Phy Interface......................................................................................................................55
4.6.5 1588v2 Timestamp Interface.............................................................................................55
4.6.6 Packet Classifier Interface..................................................................................................56
4.6.7 TOD Interface.....................................................................................................................58
4.7 Register Mapping.......................................................................................................................58
4.7.1 Master TOD........................................................................................................................59
4.7.2 1G TOD...............................................................................................................................60
4.7.3 10G TOD.............................................................................................................................61
4.7.4 PHY.....................................................................................................................................62
4.7.5 1G/10G MAC......................................................................................................................64
4.8 Simulating the Example Design..................................................................................................68
4.8.1 Simulation Collateral..........................................................................................................68
4.8.2 Simulation Test Cases........................................................................................................68
4.9 Testing the Example Design in Hardware..................................................................................70
4.9.1 Hardware Setup.................................................................................................................70
4.9.2 Timing Closure...................................................................................................................71
4.9.3 SignalTap Signaling.............................................................................................................72
5 Functional Description: 1G-10G Ethernet Example Design................................................................78

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5.1 Software and Hardware Requirement.......................................................................................78

5.2 Feature......................................................................................................................................78
5.3 Clocking.....................................................................................................................................79
5.4 Reset..........................................................................................................................................79
5.5 Parameter Setting......................................................................................................................79
5.5.1 Example Design Parameters..............................................................................................79
5.5.2 PHY Pre-Set Parameters.....................................................................................................80
5.6 Interface Signaling.....................................................................................................................80
5.6.1 Clock & Reset.....................................................................................................................80
5.6.2 Avalon-MM Interface.........................................................................................................81
5.6.3 Avalon-ST Interface............................................................................................................82
5.6.4 Phy Interface......................................................................................................................85
5.6.5 1588v2 Timestamp Interface.............................................................................................85
5.6.6 Packet Classifier Interface..................................................................................................87
5.6.7 TOD Interface.....................................................................................................................88
5.7 Register Mapping.......................................................................................................................89
5.8 Simulating the Example Design..................................................................................................89
5.8.1 Simulation Collateral..........................................................................................................89
5.8.2 Simulation Test Cases........................................................................................................89
5.9 Testing the Example Design in Hardware..................................................................................89
5.9.1 Hardware Setup.................................................................................................................90
5.9.2 Timing Closure...................................................................................................................90
5.9.3 SignalTap Signaling.............................................................................................................90
6 Functional Description: 10G Base-R Register Mode Example Design................................................92
6.1 Software and Hardware Requirement.......................................................................................92
6.2 Feature......................................................................................................................................92
6.3 Clocking.....................................................................................................................................94
6.4 Reset..........................................................................................................................................94
6.5 Parameter Setting......................................................................................................................94
6.5.1 Example Design Parameters..............................................................................................95
6.5.2 PHY Pre-Set Parameters.....................................................................................................95
6.6 Interface Signaling...................................................................................................................103
6.7 Register Mapping.....................................................................................................................104

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6.8 Simulating the Example Design................................................................................................104

6.8.1 Simulation Collateral........................................................................................................104
6.8.2 Simulation Test Cases......................................................................................................105
6.9 Testing the Example Design in Hardware................................................................................105
6.9.1 Hardware Setup...............................................................................................................105
6.9.2 Timing Closure.................................................................................................................106
6.9.3 SignalTap Signaling...........................................................................................................106
7 Functional Description: 1G/2.5GbE MAC + PHY example design.....................................................111
7.1 Software and Hardware Requirements....................................................................................111
7.2 Features...................................................................................................................................111
7.2.1 High Level Block Diagram.................................................................................................112
7.3 Clocking Scheme......................................................................................................................112
7.4 Reset Scheme..........................................................................................................................114
7.5 Generation Flow with parameter setting.................................................................................115
7.5.1 Using the design example................................................................................................115
7.5.2 Changing the number of channels...................................................................................115
7.5.3 Regenerate IP files when upgrade to new version of ACDS.............................................116
7.6 Interface Signals.......................................................................................................................117
7.6.1 Clock and Reset Signals....................................................................................................117
7.6.2 Avalon-MM Interface Signals...........................................................................................117
7.6.3 Avalon-ST Interface Signals..............................................................................................119
7.6.4 PHY Interface Signals.......................................................................................................119
7.7 Register Map............................................................................................................................120
7.7.1 1G/2.5G Ethernet Reconfiguration Controller.................................................................120
7.7.2 1G/2.5G Ethernet MAC....................................................................................................122
7.7.3 PHY...................................................................................................................................122
7.8 Simulating the example design Testbench...............................................................................123
7.8.1 Simulation Collateral........................................................................................................123
7.8.2 Test Cases........................................................................................................................125
7.9 Testing the ED in hardware......................................................................................................126
7.9.1 Hardware setup...............................................................................................................126
7.9.2 Timing closure..................................................................................................................129
7.9.3 SingalTap signaling...........................................................................................................129

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8 Functional description: 1G/2.5GbE MAC + PHY with IEEE 1588v2...................................................129

8.1 Software and Hardware Requirements....................................................................................129
8.2 Features...................................................................................................................................129
8.2.1 High Level Block Diagram.................................................................................................131
8.3 Clocking Scheme......................................................................................................................132
8.4 Reset Scheme..........................................................................................................................133
8.5 Generation Flow with parameter setting.................................................................................133
8.5.1 Using the design example................................................................................................133
8.5.2 Changing the number of channels...................................................................................133
8.5.3 Regenerate IP files when upgrade to new version of ACDS.............................................134
8.6 Interface Signals.......................................................................................................................135
8.6.1 Clock and Reset Signals....................................................................................................135
8.6.2 Avalon-MM Interface Signals...........................................................................................135
8.6.3 Avalon-ST Interface Signals..............................................................................................137
8.6.4 IEEE 1588v2 Timestamp Interface Signals........................................................................137
8.6.5 Packet Classifier Interface Signals....................................................................................138
8.6.6 PHY Interface Signals.......................................................................................................138
8.6.7 TOD Interface Signals.......................................................................................................139
8.7 Register Map............................................................................................................................140
8.7.1 1G/2.5G Ethernet Reconfiguration Controller.................................................................140
8.7.2 TOD Master......................................................................................................................141
8.7.3 1G/2.5G Ethernet MAC....................................................................................................141
8.7.4 PHY...................................................................................................................................142
8.8 Simulating the example design................................................................................................143
8.8.1 Simulation Collateral........................................................................................................143
8.8.2 Test Cases........................................................................................................................145
8.9 Testing the ED in hardware......................................................................................................146
8.10 Known Issues...........................................................................................................................146
9 Functional Description: 1G/2.5/5/10GbE (USXGMII) MAC + PHY Example Design..........................147
9.1 Software and Hardware Requirements....................................................................................147
9.2 Features...................................................................................................................................148
9.2.1 High Level Block Diagram.................................................................................................148
9.3 Clocking Scheme......................................................................................................................149

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9.4 Reset Scheme..........................................................................................................................150

9.5 Interface Signals.......................................................................................................................151
9.5.1 Clock and Reset Signals....................................................................................................151
9.5.2 Avalon-MM Interface Signals...........................................................................................151
9.5.3 Avalon-ST Interface Signals..............................................................................................152
9.5.4 PHY Interface Signals.......................................................................................................152
9.5.5 PHY Interface Signals.......................................................................................................152
9.6 Register Map............................................................................................................................153
9.7 Simulating the example design Testbench...............................................................................153
9.7.1 Simulation Collateral........................................................................................................153
9.7.2 Test Cases........................................................................................................................156
9.8 Testing the ED in hardware......................................................................................................157
9.8.1 Hardware setup...............................................................................................................157
9.8.2 Timing closure..................................................................................................................157
9.8.3 SingalTap signaling...........................................................................................................157
10 Functional Description: 1G/2.5G/10GbE MAC + PHY example design.........................................157
10.1 Software and Hardware Requirements....................................................................................157
10.2 Features...................................................................................................................................158
10.2.1 High Level Block Diagram.................................................................................................159
10.3 Clocking Scheme......................................................................................................................159
10.4 Reset Scheme..........................................................................................................................161
10.5 Generation Flow with parameter setting.................................................................................162
10.5.1 Using the design example................................................................................................162
10.5.2 Changing the number of channels...................................................................................162
10.5.3 Regenerate IP files when upgrade to new version of ACDS.............................................163
10.6 Interface Signals.......................................................................................................................164
10.6.1 Clock and Reset Signals....................................................................................................164
10.6.2 Avalon-MM Interface Signals...........................................................................................164
10.6.3 Avalon-ST Interface Signals..............................................................................................166
10.6.4 PHY Interface Signals.......................................................................................................166
10.7 Register Map............................................................................................................................167
10.7.1 1G/2.5/10G Ethernet Reconfiguration Controller............................................................167
10.7.2 1G/2.5/10G Ethernet MAC...............................................................................................169

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10.7.3 PHY...................................................................................................................................169
10.8 Simulating the example design Testbench...............................................................................170
10.8.1 Simulation Collateral........................................................................................................170
10.8.2 Test Cases........................................................................................................................172
10.9 Testing the ED in hardware......................................................................................................173
10.9.1 Hardware setup...............................................................................................................173
10.9.2 Timing closure..................................................................................................................176
10.9.3 SingalTap signaling...........................................................................................................176
11 Functional Description: 10G Base-R Example Design..................................................................176
11.1 Software and Hardware Requirement.....................................................................................177
11.2 Feature....................................................................................................................................177
11.3 Clocking...................................................................................................................................179
11.4 Reset........................................................................................................................................179
11.5 Parameter Setting....................................................................................................................179
11.5.1 Example Design Parameters............................................................................................180
11.5.2 PHY Pre-Set Parameters...................................................................................................180
11.6 Interface Signaling...................................................................................................................188
11.7 Register Mapping.....................................................................................................................189
11.8 Simulating the Example Design................................................................................................189
11.8.1 Simulation Collateral........................................................................................................189
11.8.2 Simulation Test Cases......................................................................................................190
11.9 Testing the Example Design in Hardware................................................................................190
11.9.1 Hardware Setup...............................................................................................................190
11.9.2 Timing Closure.................................................................................................................191
11.9.3 SignalTap Signaling...........................................................................................................191
12 Example Design Components......................................................................................................196
12.1 Mac IP......................................................................................................................................196
12.2 Phy IP.......................................................................................................................................196
12.3 Xcvr Reset Controller...............................................................................................................196
12.4 PLLs..........................................................................................................................................196
12.5 Pattern Generator & Checker..................................................................................................196
12.6 Avn-MM Address Decoder.......................................................................................................196
12.7 FIFO..........................................................................................................................................196

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12.8 32-64 Bit Adaptor....................................................................................................................196

12.9 Jtag to Avn-MM Block..............................................................................................................196
12.10 Reset Synchronizer..............................................................................................................196
12.11 MIDO...................................................................................................................................196
12.12 1588 Components................................................................................................................196
13 Example Design HW.TCL Packaging.............................................................................................197
13.1 HW.TCL Approach....................................................................................................................197
13.2 Internal ED Packaging Collaterals Organization.......................................................................197
13.3 Future improvement for ED packaging....................................................................................199
14 Example Design Timing Closure...................................................................................................200
14.1 Example Design Timing Closure Approach...............................................................................200
14.2 Example Design Constraints.....................................................................................................200
15 Appendix......................................................................................................................................201
15.1 Example Design Quick Start Sample........................................................................................201
15.2 Engineering Development Contact..........................................................................................201
15.3 Opens & Assumptions..............................................................................................................201
16 Change Log..................................................................................................................................202

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Altera LL10GE-MAC Example Design Integration Specification

1 Document Revision

Version Pub Date Review Date Author Description

0.00 Apr 27, 2015 Kean Harn ED info consolidation from existing EDs –
AN701 & AlteraWiki (10GBASER)
0.30 May 29, Jun 02, 2015 Kean Harn Content flow scrub per Usability FS
2015 template
0.50 Sep 07, 2015 Sep 07, 2015 Kean Harn Consolidate all info – requirement from
usability & existing info from AppNote/Wiki
with feedback from TechPub
0.70 Sep 22, 2015 Chandra Completion of ‘ToDo’ list except for the
following.
Debug signals, base-R testcases
0.90 Sep 24, 2015 Chandra Debug signals for the first 4 variants (except
base –R) are incorporated.
Replicated the ED components description
for the 3rd and 4th variants (Chapter 5).
Pending:
Base-R variant debug signals, testcases’
details.
0.95 Sept 25, Chandra The missing ToD information is updated in
2015 the FS.
Pending: Base-R variant debug signals and
testcases’ details.
0.96 Sept 26, Base-R variant debug signals are added,
2015 testcase details are added & hardware
setup is explained.
0.98 Oct 05, 2015 Chandra Added the chapters for the following
variants
1g2p5g
1g2p5g with 1588
1.0 Nov 07, 2015 Chandra Updated the Phy parameters with GUI
parameters.
Note: Some parameters are not present in
the GUI. We need to analyze further.
1.0 Nov 11, 2015 Chandra 4.9.1 is updated
1.1 Dec 07, 2015 Chandra 1. Si Xing added functional description
for 1/2.5/5/10G example design
2. Added the section 3.6.2 describing
testcases in detail
3. Updated the diagrams based on
Faizah’s feedback
1.2 Apr 19, 2016 Soon Chye 1. Soon Chye added section 3.2.2.5.1
/Chandra with ACDS 16.0 Enhancement:
Custom Device & Custom
Development Kit
2. Chandra updated Chapter 11 –

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10GBASE-R ED with S10 support

1.3 Jan 31, 2017 Yung Jia Updated Chapter 8 - 1G/2.5G 1588 ED to
add S10 support in ACDS 17.1IR2.
1.4 Feb 14, 2017 Soon Chye Updated Chapter 10 – 1G/2.5G/10G ED and
Chapter 11 – 10GBASE-R ED to add S10
support in ACDS 17.1IR2.
1.5 Jul 26, 2017 Jul 28, 2017 Seng Kuan 1. Added section 3.2.2.3.3 with Partial
Reconfiguration description, and
updated Chapter 7 – 1G/2.5G ED,
Chapter 8 – 1G/2.5G 1588 ED and
Chapter 10 – 1G/2.5G/10G ED with
Partial Reconfiguration description
for A10 in ACDS 17.1.
2. Added new Chapter 12 –
10M/100M/1G/2.5G/10G ED for
S10 in ACDS 17.1.
3. Removed S10 support from Chapter
10 – 1G/2.5G/10G ED in ACDS 17.1
1.6 Jul 27, 2017 Jul 28, 2017 Yung Jia 1. Updated Chapter 9 –
1G/2.5G/5G/10G (USXGMII) ED to
add S10 support in ACDS 17.1.
2. Added new Chapter 11 –
1G/2.5G/10G 1588 ED for S10 in
ACDS 17.1 (shifted existing
10GBASE-R ED to Chapter 12, and
10M/100M/1G/2.5G/10G ED to
Chapter 13).
3. Updated Chapter 12 – 10GBASE-R
ED for A10 and S10 in ACDS 17.1
 Update register map
(section 12.7)
 Change CSR clock to 125
MHz (section 12.4, 12.6,
12.9.1)

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Altera LL10GE-MAC Example Design Integration Specification

2 Introduction

The purpose of this Functional Specification is to provide a specific description of the technical as well as
user interface features of the Example Design (ED) for Low Latency 10G Ethernet MAC (LL10GE-MAC) IP
core.

This Functional specification describes the architecture of Low Latency Ethernet 10G MAC Example
Design, its components integration, interface signals, register map, clocking and reset scheme, ACDS
packaging, simulation and hardware testing.

The Example Design is developed per different variants setting of 32-bits MAC in ACDS-15.1 coupled
with a pre-parameterized Arria 10 (Night Fury) PHY. For Ethernet PHY-Only Example Design with full
parameterization of PHY, please refer to respective Ethernet PHY IP.

Chapter-3 describes user steps on generating, simulating, compiling and testing the Example Design in
hardware. The user flow described is common and applied to all Example Design variants. This is the
chapter for TechPub reference in developing Example Design Quick Start Guide.

The Chapters from 4 onwards describe functionality of each of the delivered Example Design variants:
top level block diagram, clocking and reset, parameter setting, register mapping as well as variant-
dependent information. This is the chapters for TechPub reference in developing Example Design User
Guide.

The last 5 chapters are for internal engineering consumption only. Not to be included in Example Design
User Guide.

2.1 Example Design Objective

The Example Design integrates the Low Latency 10G Ethernet MAC into a system with a pre-selected
Ethernet PHY. The source code for the Example Design is provided to customer as a reference, along
with a simulation testbench, and the files necessary to run the design as a demonstration on an Arria 10
FPGA Development Kit.

The Example Design is served as a reference to customer on how a system could be possibly built, but
definitely not the only way of building up the Ethernet system. The Example Design variants provided
are not meant to cover all possible parameterization of MAC IP with all possible pairing of PHY.

The Example Design is also not served as a vehicle that responsible for the full functional verification
coverage of the IP. The full functional verification coverage of IP should be covered with a separated
Altera in-house IP simulation environment with proper IP testplan & comprehensive validation coverage.
MAC+PHY integration full testing should be covered at IP simulation validation as well.

2.2 Example Design Variants

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The Example Design comes with variants as below with LL10GE-MAC coupling with different PHY by
stages per ACDS releases.

Example Design Variants PHY Target ACDS

MSE (10M/100M/1G/10G) Lineside with 1588v2 64-bit 1G/10G PHY 15.1 (x12ch)
MSE (10M/100M/1G/10G) Lineside without 1588v2 64-bit 1G/10G PHY 15.1 (x12ch)
1G/10G Lineside with 1588v2 64-bit 1G/10G PHY 15.1 (x12ch)
1G/10G Lineside without 1588v2 64-bit 1G/10G PHY 15.1 (x12ch)
10G Base-R Register Mode 32-bit Native PHY 15.1 (x1ch)
1G/2.5G/10G without 1588v2 1G/2.5G/10G PHY 16.0 (x2ch)
1G/2.5G with 1588v2 1G/2.5G/10G PHY 16.0 (x2ch)
1G/2.5G without 1588v2 1G/2.5G/10G PHY 16.0 (x2ch)
10G Lineside without 1588v2 (Default variant) 64-bit 1G/10G PHY 16.0 (x12ch)
MSE (10M/100M/1G/10G) Backplane without 1588v2 64-bit Base-KR PHY
1G/10G Backplane without 1588v2 64-bit Base-KR PHY
10G Backplane without 1588v2 64-bit Base-KR PHY
10G XAUI (hard) without 1588v2 XAUI PHY
10G XAUI (soft) without 1588v2 XAUI PHY
10G Base-R with 1588v2 32-bit Native PHY

2.3 Device Family Support

The Example Design supports only Arria 10 and Stratix 10 devices for ACDS-1517.1.

2.4 Existing Example Design

Existing LL10GE-MAC Example Design prior to ACDS-15.1 can be found below.

MSE (10M/100M/1G/10G) with & without 1588v2 (AN701)

http://www.altera.com/literature/lit-an.jsp

10G Base-R Register Mode

http://www.alterawiki.com/wiki/Low_Latency_Ethernet_10G_MAC_using_Arria_10_PHY_10GBASE-
R_Register_Mode

2.5 Example Design Quick Start Document

This document provides a crisp and pictorial description of how to get the example design up and
running. The detailed functional description is provided in the IP User guide as usual. However the
purpose of this document is to provide a quick start guide for the Example Design.

Please refer to Appendix for sample Quick Start document.

2.6 Example Design Quick Start Video

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Altera LL10GE-MAC Example Design Integration Specification

This highly desirable collateral is a video (or animation) tutorial that covers all the items described above
in the Quick Start Document section.

LL10GE-MAC Example Design has no plan for the Video Tutorial in ACDS-15.1.

2.7 Unified Reset Architecture

The necessity for the improved reset architecture has arisen due to some customer issues. At the same
time, there is a need for unified reset architecture across the example designs using Ethernet MACs and
Phys.

2.7.1 Ideal Reset Flow

The reset deassertion flow is given below. We will keep Tx and Rx flows separately.

 CSR up & running

 Phy out of reset -> PLL lock, clock stable
 PCS out of reset (usually handled by the Phy reset controller)
 MAC out of reset
The reset assertion flow is given below. We will keep Tx and Rx flows separately.

 MAC in reset after flushing out all the buffers

 PCS in reset (usually handled by the Phy reset controller)
 Phy in reset
 CSR up & running (finally down if required)

The reason for separation of Tx and Rx resets is that in multicast networks, it is quite possible that the
video/audio streaming is unidirectional. So, only the Tx path of the transmitting node and the Rx path of
receiving nodes are active, implying that the Rx path of the transmitting node and the Tx path of
receiving node can be under reset. Further, such separate Tx and Rx reset flows are in line with
philosophy of EEE (Energy Efficient Ethernet) that unused paths are kept under reset in order to save
power.

In case of auto negotiation, the ideal reset flow is as follows.

For the case of software controlled reset flow,

 Auto-negotiation happens
 Speed/throughput changes
 There is a polling/interrupt routine which notes the change
 The software routine initiates the MAC reset

For the case of fully hardware controlled reset flow,

 Auto-negotiation happens

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Altera LL10GE-MAC Example Design Integration Specification

 Speed/throughput changes
 A port from the Phy indicates the change
 The reset state-machine makes the state-change to the ‘reset-MAC’ state

2.7.2 Architecture to realize the ideal flow

Some specific details about the design while realizing the above ideal reset flow are mentioned below.

Whenever the link is down due to cable tear or pulling the sfp+ plug out, the ‘link status’ from the Phy is
noted by either a polling routine or interrupt service routine (sw code) and will initiate the reset
assertion flow as detailed in the section 2.7.1. This is typically called a managed flow where the software
and hardware work together to resolve the issues. However, in case of unmanaged flow, we have two
mechanisms to deal with the issue of the link down condition – (a) using a microcontroller transparently
to achieve the same purpose as is the case with a processor (b) using a reset state machine entirely in
the hardware. In case of (b), the status change on link down condition causes a state transition in the
reset machine, which then initiates the reset assertion flow. Usually, FPGAs with Ethernet ports are used
in the managed switching networks. However, in both the cases of managed and unmanaged
networks, the system-level reset flow is handled beyond the scope of the example designs. However,
our reset architecture facilitates both managed and unmanaged reset flows.

Currently, the Phy asserts a reset to the MAC directly due to some conditions such as link speed change
or deassertion of rx_is_lockedtodata. This condition of Phy asserting reset directly might not be friendly
to the system designs and hence we ensure in our example designs that there is no reset from the Phy
to the MAC. Further, we have observed that ‘rx_is_lockedtodata’ from the Phy is not as reliable as
‘block_lock(10G)/led_link(1G)’ or ‘rx_data_ready’ from the same Phy. Hence, we need to request the
customers to use the ports ‘block_lock(10G)/led_link(1G)’ or ‘rx_data_ready’ for their system level reset
architectures.

Our example design, on speed changes (1G <->10G), the example design will change the design so that
the speed transition from the Phy is ‘noted’ and then ‘digital reset’ to the MAC is asserted, without any
direct reset connection from the Phy reset controller to the MAC.

If the existing customers still want to use the reset from the Phy to MAC, they might be advised to turn
to the CSR implementation, where in, an enable bit, on write to 1, enables the reset from the Phy to the
MAC. The default behavior is to avoid the direct reset from the Phy to the MAC for any issue in the Phy.
In fact, the RTL changes from 15.1 in the example design will facilitate the same and the customers can
take base their implementation on our example design RTL changes.

The following diagrams capture the requirements of the ideal reset flow. The first diagram shows the
older reset diagram and the 2nd diagram shows the required reset architecture for ideal/improved reset
flow.

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Figure: Old Reset architecture

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Figure: New reset architecture

Following requests for enhancing the reset scheme are under consideration.

 Accessibility of MAC and Phy resets via ED CSR for automation

 Accessibility of status signals from MAC and Phy via ED CSR

2.7.3 Analysis of the new reset architecture with respect to the customer issues

E// reports that LinkFault status toggles between OK and LocalFault causing the MAC to send out IDLE or
RemoteFault. It is root-caused to ‘rx_is_lockedtodata’ toggling leading to toggling of the reset from the
Phy to the MAC. The explanation is as follows. The digital reset makes the Phy output LocalFault
sequence but MAC out of reset has its fault status set to 0. But, after reset, the MAC-Rx receives local
fault sequences from the Phy and intimates the MAC-Tx the reception of the local fault sequences. The
MAC-Tx then transmits remote fault sequences to its partner. When a loss of signal happens, the Phy
reset controller sends local faults and at the same time asserts MAC Rx reset too. So, the MAC link fault
status bit will be 0 on every reset due to toggling ‘rx_is_lockedtodata’, which in turn is due to the
occasional loss of signal on the wire. But, the MAC changes the status bit to 1’b1, when it receives the
local faults from the Phy due to the loss of signal. Thus, the status bit toggles between 0 and 1. It is clear
that we need to remove the influence of the Phy on the MAC in terms of the reset.

Following are the highlights that lead to the conclusion that Phy and MAC resets need to be separated.

PCS out of reset must output LocalFault as per protocol

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When MAC out of reset, will have its fault status set to no fault status

Then it observes the data coming from the PCS and changes the fault status to LocalFault

Thus, MAC after reset, will track the PCS data (good or bad)

Phy should not assert the Rx digital reset to the MAC block

 In case of any Phy issues, the PCS issues the respective fault signals such as error
termination or fault signalling

 MAC can track such PCS signalling and take decisions such as asking MAC TX to send
remote faults or IDLEs

 Any speed/throughput changes (1G <->) will be ‘noted’ by the ED and ‘reset’ will be
asserted to the MAC but no direct reset from the Phy to the MAC

So, the resets of MAC and Phy (with the PCS) must be independent

Protocol background (IEEE 802.3):

With reference to the following diagram,

 Reception of local fault status messages causes local RS to inhibit frame transmission and
transmit remote fault messages on the XGMII
 Reception of remote fault status messages indicates that remote RS has detected a fault at the
far end, causes local RS to inhibit frame transmission and transmit IDLE characters on the XGMII
 Reception of 4 link faults leads to setting the respective status bit
 Absence of fault messages for 128 columns resets the link fault status bit
 Local fault is recognized by the PCS Receive process, when align_status = FAIL or when powered-
up/reset (indicating not fully ready to receive/transmit data)
 Status of lane-to-lane code group alignment
 Remote fault conditions are NOT detected by PCS, only the RS detects them

Figure: Fault link behaviour

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2.7.4 Backward compatibility

We can ensure backward compatibility between older reset architecture and newer reset architecture
so that the customers, if bent towards older reset architecture for some reasons, we donot block them
from using it. Following are the design changes and the considerations for the backward compatibility.

Connect rx digital reset coming from a Phy to the existing CSR Rx reset and gating with
‘phy2mac_reset_en’

 Default is 0 as we do not want the customers to see the issue

 If required by any customer through private communication, we can ask him to enable
the bit

 Assumption: rx digital reset from Phy and CSR rx reset behave and impact the design
exactly in the same way

Design changes due to bugs (15.1)

 Will not expose to the customer but still will keep the backward compatibility options to
service any special requests from the customers

Design changes due to planned enhancements (16.0 onwards)

 Exposed as an option to the customer giving backward compatibility

2.7.5 ACDS Plan

ACDS Reset Feature Analysis
16.0 Separate MAC and Phy resets 1.The focus is on disconnecting
the reset to the MAC from the
phy reset controller
2. Maintain the backward
compatibility through the CSR
3. Still conforms to existing
single reset ED.
16.1 Separate mm_reset and 1.Separating mm_reset and
datapath_reset datapath_reset (master and
channel resets)
2.Separating the MAC, Phy
resets is right reset architecture,
given the orthogonality,
mapped to CSR.
3. Add CSR bits for debug
capability and reset (Hung
Chiew’s request)
17.0 Separate Tx and Rx resets for 1. Better reset flow to the
better reset control customer
2. Compliance across Base-
R and KR
Clean Reset Architecture enabling power efficient Architectures

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Additional requests timeline:

Accessibility of MAC and Phy resets via ED CSR for automation

 16.0: Nothing planned

 16.1: Separation of MAC and Phy resets and their accessibility via ED CSR

 17.0: Separation of MAC Tx and Rx and Phy Tx and Rx resets and their accessibility via ED
CSR

 16.1 & 17.0 help design better power efficient architectures

Accessibility of status signals from MAC and Phy via ED CSR

 Out of scope for reset architecture but in scope of ED architecutre

 Hung Chiew to come up with the list of status signals

 To discuss with Soon Chye what are already available and what are missing in terms of
accessibility from the CSR

 Issue of coherence – should we access Phy status and MAC status at the same time or in
any order? If so, our CSR architecture/design should facilitate that.

For coherence, we need to bring out the relevant status signals to the same
register so that we can access the register in one go via ED CSR.

2.7.6 Practical considerations

At the moment, there is no port from the Phy indicating speed/throughput change (1G <-> 10G). We
have adopted the following mechanisms to deal with it during autonegotiation.

 Requesting Phy team to provide speed/throughput change status (1G <-> 10G etc) for future
EDs, so that we can keep hardware controlled reset flow in such cases

 Temporary: A CSR routine with a polling timer in the current ED is not a bad idea to mimic the
real scenario.

 Temporary: Do we have any any other status port or group of status port such block_lock etc to
indicate the speed/throughput transition?

o bank on such ports to generate MAC reset

2.7.7 Points to be double-checked

 Phy reset controller to ensure no valid conditions from the Phy are missing out on
resetting the MAC Rx

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(We see NONE)

 Local/Remote fault in response from PCS but not out of digital rx reset

MAC has to get LF or RF to take actions but does not generate any LF/RF on its
own

 PCS out of reset, or real link faults (sfp plug out) should still send LocalFault, MAC-Rx will
intimate MAC-Tx, Tx will send out Remote faults

Correct behaviour

 Should we couple mm_reset (master reset) and datapath_reset (channel reset)?

NO

 Need more clarity on differences of the reset scheme in 10G Base-R ED and 1/10G KR
ED.

The architecture has to be agreed upon, across the EDs

3 User Flow

3.1 Delivering the Example Design

The LL10GE-MAC Example Design is delivered alongside of the IP core via ACDS-15.1. For IP cores
released via ACDS-15.1, the Example Design is delivered and generated using IP Parameter Editor in a
fashion shown as follows.

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1. From Quartus IP Catalog, select targeted Device Family. For LL10GE-MAC Dynamic Generated
Example Design, it will be made available only when Arria 10 (GX/SX/GT) is selected.
2. From the IPs listed in IP Catalog, the LL10GE-MAC IP is named as Low Latency Ethernet 10G MAC.
3. Double click on the IP to give us IP Parameter Editor for parameter setting of the IP as well as
available Example Design.

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4. On top of IP Parameter Editor, a pop-up window requires users to specify the Entity name of the IP
that is going to be created as well as the targeted location of working area per Save in folder path.
5. Ensure the correct Family and select the targeted Device part number. Device is showing a default
value set by Quartus.
6. Complete the info and click OK to get back to IP Parameter Editor for parameters setting.

Note: ACDS-15.1 is not supporting LL10GE-MAC Example Design generation through Qsys IP Catalog.
(FB#318367)

3.2 Selecting IP/ED Parameters

For ACDS-15.1 onwards, the IP Parameter Editor of LL10GE-MAC is organized to allow selections of
options for both IP core and the Example Design and in a way that is fairly interdependent but also
reasonably independent as needed.

The parameter selection for the Example Design and associated IP core and devices is made through the
two separated TABs shown below. IP tab provides all the parameter selections for LL10GE-MAC IP core
whereby Example Design tab provides choices pertaining only to the Example Design.

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Note: For ACDS-15.1, a warning is given at Messages box by default stating that the default setting of IP
gives no available Example Design, which is 10G Ethernet without 1588v2. Availability of the Example
Design variant that matches the IP default parameter setting will be revisited post ACDS-15.1. (FB#)

For ACDS-15.1, there’re 5 Example Design variants made available to users. Parameter settings of the 5
variants are as below. Parameters highlighted are controllable by users with the range or value
mentioned.

Parameterization Example Design Variants

1G/10G Ethernet with
10M/100M/1G/10G

10M/100M/1G/10G

10GBase-R Register
Ethernet with 1588

1G/10G Ethernet
Ethernet

Mode
1588

IP Parameters
Speed 10M/ 10M/ 1G/10G 1G/10G 10G
100M/ 100M/

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1G/10G 1G/10G
Datapath options Tx & Rx Tx & Rx Tx & Rx Tx & Rx Tx & Rx
Enable ECC on memory blocks uncheck uncheck uncheck uncheck uncheck
Enable preamble pass-through mode uncheck uncheck uncheck uncheck uncheck
Enable priority-based flow control (PFC) uncheck uncheck uncheck uncheck uncheck
Number of PFC queues Don’t Don’t Don’t Don’t Don’t
care care care care care
Enable unidirectional feature uncheck uncheck uncheck uncheck uncheck
Enable 10GBASE-R register mode uncheck uncheck uncheck uncheck checked
Enable supplementary address User User User User User
input input input input input
Enable statistics collection checked checked checked checked checked
Statistics counters User User User User User
input input input input input
Enable time stamping uncheck checked uncheck checked uncheck
Enable PTP one-step clock support Don’t checked Don’t checked Don’t
care care care
Timestamp fingerprint width Don’t 4 Don’t 4 Don’t
care care care
Time Of Day Format Don’t Enable Don’t Enable Don’t
care both 96b care both 96b care
& 64b & 64b
Use legacy XGMII interface checked checked checked checked uncheck
Use legacy Avalon Memory-Mapped checked checked checked checked checked
interface
Use legacy Avalon Streaming interface checked checked checked checked uncheck
Example Design Parameters
Specific Number of Channels 1 – 12 1 – 12 1 – 12 1 – 12 1

3.2.1 IP Parameters

Please refer to LL10GE-MAC IP User Guide for detailed description of the IP parameters.

3.2.2 Example Design Parameters

A brief description of all the options under Example Design tab is given in the Details box.

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3.2.2.1 Available Example Designs: “Select Design”

The pull-down list lists all Example Designs available for the selected set of IP parameters. If there is no
available Example Design per the IP parameter setting, “None” will be shown with all of Example Design
setting options being grey-out.

3.2.2.2 Example Design Parameters: “Specify Number of Channels”

For the available Example Design variants, users are allowed to select the number of channels as below.

Parameterization Example Design Variants

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1G/10G Ethernet with

10M/100M/1G/10G

10M/100M/1G/10G

10GBase-R Register
Ethernet with 1588

1G/10G Ethernet
Ethernet

Mode
1588
Specific Number of Channels 1 – 12 1 – 12 1 – 12 1 – 12 1

3.2.2.3 Files Type Generated: “Generate Files for”

The purpose of this check-box option is to allow user to select the type of fileset he or she wants to
generate for Example Design. The goal is to let the user use an example design through various phases
of the development flow. Both Simulation and Synthesis options are pre-selected by default. User must
select at least one of the options else an error will be blocking users from further generation steps.
These parameters are defined further as below.

3.2.2.3.1 Simulation

When this option is selected, Example Design files necessary for simulating will be populated in user’s
Example Design generation directory.

3.2.2.3.2 Synthesis

When synthesis is enabled, synthesis files are created in user space. These files are fully sufficient to
demonstrate the Quartus compilation as well as static timing analysis development flow.

3.2.2.3.3 Partial Reconfiguration Ready

 When this option is enabled, the generated Example Design hierarchy is compliance to partial
reconfiguration flow, where there is clear separation between hard IP and soft IP, without any
functionality changes. Hard IP such as Native PHY, JTAG, TXPLL will be instantiated at the top-
level wrapper of Example Design.

3.2.2.4 Generated HDL Format: “Generate File Format”

The purpose of this pull-down list is to allow users to select either Verilog or VHDL as the HDL format of
generated RTL files.

Note that the selection will take effect on Qsys-generated IP block including both LL10GE-MAC and PHY.
The Example Design top level is always in Verilog HDL format.

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3.2.2.5 Target Development Kit: “Select Board”

When Synthesis checkbox is checked, users can choose to perform Altera provided hardware tests on
one of the hardware boards listed from the pull-down menu. Each Development kit comes with a
specific device and pin assignments. For ACDS-15.1, Arria 10 FPGA Signal Integrity Kit is provided as the
option with device 10AX115S4F4513SGE2.

If “None” was selected from the pull-down list, a virtually assigned pin setting will be provided for the
Example Design.

3.2.2.5.1 ACDS 16.0 Enhancement: Custom Device & Custom Development Kit

In ACDS 16.0, this option has been enhanced to support custom devices and custom development kits. A
visual of the layout in Example Design Tab is below and details described in the following paragraphs:

Below shows the different between 15.1 and 16.0 on the “Target Development Kit” parameter selection
under ED tab.

Target Development Kit 15.1 16.0

None  

No Development Kit  

Custom Development kit  

Arria 10 GX Transceiver Signal Integrity  

Development Kit

 No Development Kit: This selection replaces the “None” in 15.1. When selected this option, the
Example Design generation will produce necessary files for Quartus compile. The Quartus
Settings File (QSF) will have pin assignments set to virtual pins. If user needs to change the
target device, user should change it following instructions provided under Target Device option
(described later). The layout and text description for this option is as below.

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 Altera Development kit: When selected this option, the Example Design generation will produce
necessary files for Quartus project targeted to the selected Altera Development Kit. The Quartus
Settings File (QSF) will have pin assignments appropriately set. If a user has a different Rev of
this board with a variation of the device selected, user should change it following instructions
provided under Target Device option (described later). The layout and text description for this
option is as below.

 Custom Development Kit: This mechanism is provided to enable users to select a development
kit or hardware board that is not listed as an entry in the drop down menu above. This
mechanism lets user generate the Example Design on a different Altera Development kit, their
own board or may be a partner board with Altera device on it. When this option is selected, the
Example Design QSF file is still generated, however it has board specific settings left empty. The
user is instructed to later edit the file to add board specific quartus assignments before
compiling on the section marked with

# =================================================================
# Pin & Location Assignments
# =================================================================
# PLEASE ADD LOCATION ASSIGNMENT FOR YOUR BOARD HERE !!

The layout and text description for this option is as below.

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3.2.2.6 Target Device (ACDS 16.0 enhancement)

In ACDS 16.0, this option is added to allow Target Devices to be changed by using an established Quartus
mechanism. This mechanism is to use menu bar as shown below.

This mechanism allows changing Target Device on any of the selection under “Target Development Kit”
option.

For Altera Development Kit, only possible device grade variations are allowed. The following device
grade variations are allowed. This means if a user wants to change device on Altera Development kit and
the new device has one or all of the following items different from current device on development kit,
then the change is valid and the new device will be the new Target Device.

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 Transceiver Speed grade: Allowed Transceiver Speed grades:1 (fastest),2,3,4

 Power Options: Allowed Transceiver power options: S : Standard, L : Low, M : VCC
PowerManager
 Operating Temperature: Allowed operating temperatures are: I : Industrial , E : Extended ,M :
Military
 Fabric Speed grade: Allowed Fabric Speed grades:1 (fastest),2,3,4
 Production Level: Allowed values are:
1. Engineering Sample
2. Engineering Sample 2
3. Engineering Sample 3
4. Production Silicon

The GUI display and instruction text for different “Target Developmenet Kit” selection is as below.

 No Development Kit / Custom Development Kit

 Altera Development Kit

3.2.3 IP Parameter Compatibility with Example Design

The IP instance in the Example Design (“the DUT”) has parameter values exactly the same as the
selections made from the IP tab in IP Parameter Editor.

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For instance of parameter setting under IP tab is not matching any of the Example Design variants
delivered, Available Example Designs: Select Design under Example Design tab will just display a
“None” with the remaining sections of the Example Design tab being grey-out, no further selection by
users is allowed and Generate Example Design button at the top will give an error.

Anyway, clicking the Generate HDL button at the bottom will still generate LL10GE-MAC IP itself per the
IP parameter setting selected in IP tab.

3.3 Generating Example Design

3.3.1 Generation Method

There are two ways of generating available Example Design: 1) Through matching IP parameter settings
from IP tab 2) Selecting available Example Design variant settings through Presets window.

For any IP parameter settings that match the available Example Design, the respective Example Design
variant will be bolded in the Presets window. With the bolded Example Design variant, users can
proceed to Example Design tab for further option selection before generating the Example Design.

A quicker way of obtaining the available Example Design is to directly double-click on the desired
Example Design variant in Presets window. The action will update all the IP parameters to the Example
Design variant setting.

Note: To preserve existing IP parameter setting by users, users should save it before double-clicking on
the Example Design variant from Presets, which will overwrite all the parameters with preset value.

Once a good set of parameter selection is completed, Example Design is generated by clicking the
Generate Example Design button at the top of IP Parameter Editor. A pop-up window will prompt users
for location for dumping the Example Design. Specify desired location and click OK to proceed the
Example Design generation.

Note: Example Design generation will take ~5-15 minutes without any interruption.

3.3.2 Generation Output

The Example Design generated is self-contained. It does not require users to generate IP core or any
other mega-function separately.

The Example Design generated is organized as directory structure below.

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<Example Design>

rtl simulation hwtesting output_files altera_eth_top.qpf

<ED top level(s).sv ed_sim system_console altera_eth_top.qsf

<ED Component> models altera_eth_top.sv

...

cadence altera_eth_top.sv
<ED Component>
mentor

synopsys

vcs

Example Design Collaterals Description

altera_eth_top.qpf Quartus project file
altera_eth_top.qsf Quartus settings file
altera_eth_top.sv Example Design top level HDL
altera_eth_top.sdc Synopsys Design Constraints (SDC) file
rtl Example Design synthesizable components
rtl/<ED top level(s)>.sv Example Design DUT top level.
rtl/<ED Component> Synthesizable components including Qsys generated IPs i.e.
LL10GE-MAC, PHY, Address Decoder, FIFO, PLLs, Xcvr Reset
Controller.
simulation/ed_sim/models Simulation testbench
simulation/ed_sim/cadence NCsim simulation run script & working area.
simulation/ed_sim/mentor Modelsim-AE and Modelsim-SE simulation run script & working
area.
simulation/ed_sim/synopsys/vcs VCS simulation run script & working area.
hwtesting/system_console System Console scripts for hardware testing
output_files Quartus run output files including all the Quartus compilation
reports.

3.4 Simulating Example Design

1. Users would have to obtain ACDS-15.1 resource as well as targeted EDA simulator environment
license.
2. Simulation collateral can be referred under <Example Design>/simulation/ed_sim/models.
3. Go to <Example Design>/simulation/ed_sim/<simulator> to invoke the simulation run script of
targeted EDA simulator.

Simulator Simulation Directory Invoke run script

NCsim simulation/ed_sim/cadence source tb_run.sh
Modelsim-AE & Modelsim-SE simulation/ed_sim/mentor vsim -c -do tb_run.tcl
VCS simulation/ed_sim/synopsys/vcs source tb_run.sh

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4. Simulation will run till completion once run script is invoked. Simulation runtime is depends on
Number of Channel selected. Advisable to choose 1-2 channels for early check-out for a shorter
simulation runtime.
5. Simulation result will be under the same simulator subdirectory.

3.4.1 Simulators Supported

ACDS-15.1 is supporting NCsim, Modelsim-AE, Modelsim-SE and VCS. VCSMX and Riviera will be enabled
post ACDS-15.1.

3.4.2 Simulation Warning

Simulation warning of Example Design is not totally clean for ACDS-15.1 but all are waive-able.

3.4.3 Simulation Testbench

Simulation testbench is operating in loopback mode. The following figure shows the flow of the packets
in the Example Design.

Component Description
Device Under Test (DUT) The Example Design

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Avalon Driver Uses Avalon-ST master bus functional models (BFMs) to form
transmit and receive paths. The driver also uses the master
Avalon-MM BFM to access the Avalon-MM interfaces of the
Example Design components.
Packet Monitor Monitor transmit and receive datapath and display the frames
in the simulator console.

3.5 Compiling Example Design using Quartus

1.       With the Example Design generated, load up <Example Design>/altera_eth_top.qpf from Quartus.
2.       From Processing menu, click on Start Compilation to start Quartus compilation, which includes
timing analysis.
3.       Once completed, below is the report files for users review.
Synthesis report: <Example Design>/output_files/altera_eth_top.map.rpt
Fitting report: <Example Design>/output_files/altera_eth_top.fit.rpt
Timing report: <Example Design>/output_files/altera_eth_top.sta.rpt

To Do (Need to check in acds16.0): The reports generated are with Quartus Prime Standard. Quartus
Prime Pro is missing a map.rpt that needs to be figured out by end of day. ACDS-15.1 is with Quartus
Prime Pro as beta version targeting for certain customer only, not a public released version.

3.5.1 Compilation Warning

Compilation warning of Example Design is not totally clean for ACDS-15.1 but all are waive-able. This not
includes timing check Critical Warning if there’s any from timing analysis run. Users have to ensure clean
timing check prior to bringing the Example Design to hardware check-out.

3.6 Testing Example Design in Hardware

Putting Example Design in hardware is to ensure the Example Design is working correctly on Altera FPGA
Development Board under normal room temperature condition.

1. Users must ensure Example Design is passing Quartus compilation and timing check prior to bringing
the Example Design to hardware.
2. Configure Arria 10 FPGA Development Board using <Example
Design>/output_files/altera_eth_top.sof
3. Open Clock Control tool and set new frequency for Y5 and Y6 as below for all the ED variants:
y5:644.53125 MHz
y6:125 MHz
except the 10G Base-R, which uses
Y5: 322.265625MHz
4. Press PB0 push button to reset system after configuration done.
5. Select Tools/System Debugging Tools/System Console from Quartus menu.
6. In System Console command shell, change directory to <Example
Design>/hwtesting/system_console
7. Run command “source main.tcl” to initialize Example Design command list.

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8. Perform any of pre-defined hardware tests by running the test command in System Console
command shell.

To Do (Done): Verify the steps with hardware testing to ensure flow validity. Update accordingly per
latest approach.

3.6.1 Example Design Hardware Setup

Below shows the top level setup of Example Design hardware testing using Arria 10 Development Kit.

Arria 10 Development Kit

Arria 10 FPGA
JTAG TAP Eth Packet Gen & altera_eth_channel
Controller Mon (Master) (Channel 0)

Eth Packet Gen & altera_eth_channel

Mon (Slave) (Channel 1)

...
System Console
Eth Packet altera_eth_channel
Gen & Mon (Channel N-1)
...

Eth Packet altera_eth_channel

Gen & Mon (Channel N)

Altera System
N = Number of Channels per
Console Software ED variant supported range

3.6.2 Hardware test cases description

1) 10M/100M/1G/10G Ethernet with 1588, 10M/100M/1G/10G Ethernet,

1G/10G Ethernet with 1588, 1G/10G Ethernet
a. Perform the following test by running the command in the System Console command
shell:
i. PHY internal serial loopback
Command:
TEST_PHYSERIAL_LOOPBACK {channel speed_test burst_size}

Example: TEST_PHYSERIAL_LOOPBACK 0 10G 1000

ii. SMA loopback

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Command:
TEST_SMA_LB {channel speed_test burst_size} (for variant with 1588)
TEST_SMA_LOOPBACK {channel speed_test burst_size} (for variant
without 1588)

Example: TEST_SMA_LB 0 10G 1000

The following table provides description of each parameter of the command.

Parameter Description Valid value
Channel To specify the channel number the test 0 to <max channel in
intended to run on. design>
speed_test To specify the speed mode of the test 10G, 1G, 100M, 10M (for
10M-10G variant)

10G, 1G (for 1g/10g

variant)
burst_size To specify the number of packet the Integer value
test will generate

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b. Observe the following output of each test run to confirm it is working. Both PHY internal
serial loopback and SMA loopback test will have the similar output.

i. This output shows that the monitor module receives the correct number of
packet without any bad packet.

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ii. This output shows the MAC TX and RX statistic counter report correct number of
frame transmitted and received without packet corruption

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2) 10GBase-R Register Mode

a. Perform the following test by running the command in the System Console command
shell:
i. SFP+ loopback
Command:
1) source gen_conf.tcl (Generate and send 0xffff2000 packets)
2) wait for about 6 minutes (the generator send about 4 billion packets, it
takes time to receive all the packets) , then source monitor_conf.tcl (To
check the number of good and bad packets received)
3) source show_stats.tcl (To show the statistics counter values)
ii. Avalon-ST loopback
Command:
1) source loopback_conf.tcl (enable Avalon-ST loopback)

b. Observe the following output of SFP+ loopback test to confirm it is working. Avalon-ST
loopback test is mainly use for testing with external tester, e.g. Spirent tester.

i. This output shows that the monitor module receives the correct number of
packet without any bad packet.

ii. This output shows the MAC TX and RX statistic counter report correct number of
frame transmitted and received without packet corruption

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4 Functional Description: 10M/100M/1G/10G Ethernet Example

Design

The following Example Designs demonstrate Altera Low Latency Ethernet 10G MAC IP systems using
Arria 10 PHY in multi-speed 10M/100M/1G/10G mode.

4.1 Software and Hardware Requirement

Altera uses the following software and hardware to test the Example Design and testbench in Linux
platform.

 Quartus Prime.
 System Console. The user guide can be found at link:
http://www.altera.com/literature/ug/ug_system_console.pdf
 Simulators: Modelsim-AE, Modelsim-SE, NCsim or VCS (for complete simulators revision please refer
to link-TBD).
 Hardware: Arria 10 FPGA Development Kit (device TBD).

4.2 Feature

The Example Design offers the following features:

• Support multi speed operation of 10 Megabits per second (Mbps) to 10 Gigabits per second (Gbps)
with Arria 10 1G/10G PHY.
• Support scalability from 1 to 12 channels Ethernet MAC and PHY.
• Provide packet monitoring system on transmit and receive data paths and report Ethernet MAC
statistics counters for transmit and receive datapath.
• Support testing using different types of Ethernet packet transfer with or without IEEE 1588v2
features.

Block Diagram of Example Design without IEEE 1588v2

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Block Diagram of Example Design with IEEE 1588v2

To Do (Done): Update diagram with mdio removed. Currently, the above diagrams are not in visio and
hence the engineering team could not modify the above. However, the techpub team can remove the
MDIO from the above diagrams.

Example Design Components

ED Component Without IEEE 1588v2 With IEEE 1588v2

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Low latency Ethernet 10G Ethernet MAC IP core

MAC
Arria 10 1G/10G PHY Altera 1G/10G and 10GBASE-KR PHY IP
Address decoder channel Address decoder module for each component within the channel,
for example, MAC and PHY.
Address decoder multichannel Address decoder module for all channels and components within
multichannel level, for example Master TOD.
Reset controller Reset modules which handle reset synchronization for all ED
components.
Master PLL Generates clocks for all the components in the Example Design.
Arria 10 ATX PLL Generates a TX serial clock for Arria 10 10G transceiver.
Arria 10 fractional PLL Generates a TX serial clock for Arria 10 1G transceiver.
FIFO Avalon Streaming (Avalon-ST) ---
singleclock or dual-clock FIFO
that buffers the receive and
transmit data between the MAC
and client.
Master Time-of-Day --- Provides a master TOD for all
(TOD) channels.
TOD Sync --- Module to synch time of day
from Master TOD to Local TOD
for all channels.
Local TOD --- TOD module in each channel.
Master pulse per second --- Returns pulse per second (pps)
module to user for all channels.
1G/10G Pulse Per Second --- Returns pulse per second (pps)
module to user in each channel.
PTP packet classifier --- Decodes the packet type of
incoming PTP packets and
returns the decoded
information to the Ethernet
MAC.

4.3 Clocking

The following diagrams show the clocking scheme of the Example Design without and with IEEE 1588v2.

Clocking Scheme for Example Design without IEEE 1588v2

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Clocking Scheme for Example Design with IEEE 1588v2

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4.4 Reset

At the Example Design level, there are one master_reset_n and <N> channel_reset_n signals. All the
signals are asynchronous and active-low signal. The signals are synced to different clock domain
internally. When the master_reset_n is asserted, the signal will bring down all <N> Ethernet channels
and all modules in the Example Design.

The channel_reset_n[0..N] only reset all the components in the individual channel.

Master reset is needed when the Example Design is powered up.

Example Design without IEEE 1588v2: Multi Channel Level Reset Scheme
The following diagram shows the reset scheme at altera_eth_multi_channel level. master_reset_n is
used to reset the whole Example Design, while channel_reset_n is used to reset the individual Ethernet
channel.

Reset scheme at altera_eth_multi_channel

Example Design without IEEE 1588v2: Channel Level Reset Scheme

The following diagram shows the reset scheme per channel. mm_reset is used to reset the registers in
MAC, PHY and address_decoder block while datapath_reset is used to reset all digital blocks including
PHY reset controller. However, mm_reset and datapath_reset are tied together at multichannel level in
the Example Design. Therefore they can't be triggered separately.

Reset scheme at altera_eth_channel

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Example Design with IEEE 1588v2: Multi Channel Level Reset Scheme
The following diagram shows the reset scheme at altera_eth_multi_channel_1588 level. master_reset_n
is used to reset the whole Example Design, while channel_reset_n is used to reset the individual
Ethernet channel.

Reset Scheme at altera_eth_multi_channel_1588

Example Design with IEEE 1588v2: Channel Level Reset Scheme

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The following diagram shows the reset scheme per channel. mm_reset is used to reset the registers in
MAC, PHY, TOD, MDIO and address decoder block, while datapath_reset is used to reset MAC, PHY reset
controller and TOD. However, mm_reset and datapath_reset are tied together at multi-channel level in
the Example Design. Therefore it is not possible to trigger them separately.

Reset scheme at altera_eth_channel_1588

4.5 Parameter Setting

4.5.1 Example Design Parameters

Parameter Without IEEE 1588v2 With IEEE 1588v2

IP Parameters
Speed 10M/100M/1G/10G 10M/100M/1G/10G
Datapath options Tx & Rx Tx & Rx
Enable ECC on memory blocks uncheck uncheck
Enable preamble pass-through mode uncheck uncheck
Enable priority-based flow control (PFC) uncheck uncheck
Number of PFC queues Don’t care Don’t care
Enable unidirectional feature uncheck uncheck
Enable 10GBASE-R register mode uncheck uncheck
Enable supplementary address User input User input
Enable statistics collection checked checked
Statistics counters User input User input
Enable time stamping uncheck checked

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Enable PTP one-step clock support Don’t care checked

Timestamp fingerprint width Don’t care 4
Time Of Day Format Don’t care Enable both 96b & 64b
Use legacy XGMII interface checked checked
Use legacy Avalon Memory-Mapped checked checked
interface
Use legacy Avalon Streaming interface checked checked
Example Design Parameters
Specific Number of Channels 1 – 12 1 – 12

4.5.2 PHY Pre-Set Parameters

The Example Design is using Arria 10 1G/10GbE and 10GBASE-KR PHY with a pre-set PHY parameter
setting that matches the pairing with LL10GE-MAC IP.

PHY Parameters Without With IEEE

IEEE 1588v2
1588v2
Expanded name Abbreviated name
AN_100G 0 0
AN_40GBP 0 0
AN_40GCR 0 0
AN_BASER 1 1
CAPABLE_FEC ENABLE_FEC AN_FEC 0 0
Pause Ability -C0 AN_PAUSE_C0 1 1
Pause Ability –C1 AN_PAUSE_C1 1 1
AN_SELECTOR Selector AN_SELECTOR 1 1
Field
AN_TECH Technology AN_XAUI 0 0
Ability
Maximum bit error BERWIDTH_gui 511 511
count
Set FEC_ability bit CAPABLE_FEC 1 1
on power up or reset
PHY core version (16 DEV_VERSION 0 0
bits)
Set FEC_Enable bit on ENABLE_FEC 1 1
power up or reset
EN_CORECLK_1G 0 0
ERR_INDICATION 1 1
GOOD_PARITY 4 4
Enable Hard PRBS HARD_PRBS_ENABLE 0 0
support
HARD_PRBS_ENABLE_PORT 0 0
INITMAINVAL INITMAINVAL 25 25
INITPOSTVAL INITPOSTVAL 22 22
INITPREVAL INITPREVAL 3 3

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INI_DATAPATH 10G 10G

INVALD_PARITY 8 8
Link fail inhibit LINK_TIMER_KR 504.00 504.00
time for 10Gb
Ethernet
Link fail inhibit LINK_TIMER_KX 48.00 48.00
time for 1Gb Ethernet
Enable additional OPTIONAL_10G 1 1
control and status
ports
OPTIONAL_FEC 0 0
Enable rx_pma_clkout OPTIONAL_RXPMA_CLK 1 1
port
Enable rx_clkout port OPTIONAL_RX_CLKOUT 1 0
Enable rx_divclk port OPTIONAL_RX_DIV33CLK 0 0
Enable tx_pma_clkout OPTIONAL_TXPMA_CLK 1 1
port
Enable tx_clkout port OPTIONAL_TX_CLKOUT 1 1
Enable tx_divclk port OPTIONAL_TX_DIV33CLK 0 0
PHY ID (32 bits) PHY_IDENTIFIER 0 0
PREMAINVAL PREMAINVAL 30 30
PREPOSTVAL PREPOSTVAL 0 0
PREPREVAL PREPREVAL 0 0
10GbE Reference clock REF_CLK_FREQ_10G 644.531 644.531
frequency 25 25
1G Reference clock REF_CLK_FREQ_1G 125.00 125.00
frequency
Enable IEEE 1588 SYNTH_1588_ALL 0 1
Precision Time Protocol
Enable Auto- SYNTH_AN 0 0
negotiation
Include FEC sublayer SYNTH_FEC 0 0
Enable 1Gb Ethernet SYNTH_GIGE 1 1
protocol
SYNTH_GMII_gui 1 1
Enable Link Training SYNTH_LT 0 0
Enable 10Mb/100Mb SYNTH_MII 1 1
Ethernet
functionality
Enable internal PCS SYNTH_RCFG 1 1
reconfiguration logic
Enable automatic SYNTH_SEQ 1 1
speed detection
SYNTH_SGMII 1 1
Number of frames to TRNWTWIDTH_gui 127 127
send before sending
actual data
USE_DEBUG_CPU 0 0

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Enable M20K block ECC USE_ECC_CPU 0 0

protection
VMAXRULE VMAXRULE 30 30
VMINRULE VMINRULE 6 6
VODMINRULE VODMINRULE 14 14
VPOSTRULE VPOSTRULE 25 25
VPRERULE VPRERULE 16 16
XGMII_32BIT_MODE 0 0
device 10AX115 10AX115
S4F45I3 S4F45I3
SGE2 SGE2
Avalon-MM clock phy_mgmt_clk_freq 125 156.25
frequency
sel_backplane_linesid 1Gb/ 1Gb/
e 10Gb 10Gb
Etherne Etherne
t t

To Do (Done): List down all preset PHY parameter values for users reference.

4.6 Interface Signaling

This section describes the interface signals at Example Design level.

The NUM_UNSHARED_CHANNELS are determined by the equation below:

NUM_UNSHARED_CHANNELS = (SHARED_REFCLK_EN == 1) ? 1: NUM_CHANNELS

NUM_CHANNELS is parameter set by users from IP Parameter Editor.

4.6.1 Clock & Reset

Signal Direction Width Description

mm_clk input 1 Configuration clock for Avalon-
MM interface. Frequency is
125 MHz.
pll_ref_clk_1g input [NUM_UNSHARED_CHANNELS Reference clock for the TX PLL
] in 1G mode. Frequency is 125
MHz.
pll_ref_clk_10g input [NUM_UNSHARED_CHANNELS Reference clock for the TX PLL
] in 10G mode. Frequency is
644.53125 MHz.
cdr_ref_clk_1g input [NUM_UNSHARED_CHANNELS Reference clock for the RX PLL
] in 1G mode. Frequency is 125
MHz.
cdr_ref_clk_10g input [NUM_UNSHARED_CHANNELS Reference clock for the RX PLL
] in 10G mode. Frequency is
644.53125 MHz.

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channel_reset_n input [NUM_CHANNELS] To reset individual Ethernet

channel. This does not impact
the components running at
multi_channel level, e.g.
master TOD, master PPS and
fPLLs. Asynchronous and
active low signal.
master_reset_n input 1 To reset the whole Example
Design. Asynchronous and
active low signal.
xgmii_clk output [NUM_UNSHARED_CHANNELS Clock used for single data rate
] (SDR) XGMII TX & RX interface
in between MAC and PHY. This
clock is also used for Avalon-ST
interface. Frequency is
156.25MHz.
rx_recovered_clk output [NUM_CHANNELS] This is the RX clock, which is
recovered from the received
data.

4.6.2 Avalon-MM Interface

Signal Direction Width Description

write input 1 Assert this signal to request a
write.
read input 1 Assert this signal to request a
read.
address input 20 Use this bus to specify the register
address you want to read from or
write to.
writedata input 32 Carries the data to be written to
the specified register.
readdata output 32 Carries the data read from the
specified register.
waitrequest output 1 When asserted, this signal
indicates that the IP core is busy
and not ready to accept any read
or write requests.

4.6.3 Avalon-ST Interface

Signal Direction Width Description

avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to mark the
startofpacket beginning of the transmit data on
the Avalon-ST interface.
avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to mark the end
endofpacket of the transmit data on the

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Avalon-ST interface.
avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to indicate that
valid avalon_st_tx_data and other
signals on this interface are valid.
avalon_st_tx_ output [NUM_CHANNELS] When asserted, this signal
ready indicates that the MAC IP core is
ready to accept data.
avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to indicate the
error current transmit packet contains
errors.
avalon_st_tx_data input [NUM_CHANNELS][64] Carries the transmit data from
the client.
avalon_st_tx_ input [NUM_CHANNELS][3] Use this signal to specify the
empty number of bytes that are empty
(not used) during cycles that
contain the end of a packet.
0x0=All bytes are valid.
0x1=The last byte is invalid.
0x2=The last two bytes are
invalid.
0x3=The last three bytes are
invalid.
avalon_st_rx_ output [NUM_CHANNELS] When asserted, this signal marks
startofpacket the beginning of the receive data
on the Avalon-ST interface.
avalon_st_rx_ output [NUM_CHANNELS] When asserted, this signal marks
endofpacket the end of the receive data on the
Avalon-ST interface.
avalon_st_rx_ output [NUM_CHANNELS] When asserted, this signal
valid indicates that
avalon_st_rx_data[]and other
signals on this interface are valid.
avalon_st_rx_ input [NUM_CHANNELS] Assert this signal when the client
ready is ready to accept data.
avalon_st_rx_ output [NUM_CHANNELS][6] When set to 1, the respective bits
error indicate an error type:
• Bit 0—PHY error. For 10 Gbps,
the data on xgmii_rx_data
contains a control error character
(FE). For 10 Mbps,100 Mbps,1
Gbps, gmii_rx_err or mii_rx_err is
asserted.
• Bit 1—CRC error. The computed
CRC value differs from the
received CRC.
• Bit 2—Undersized frame. The
receive frame length is less than
64 bytes.
• Bit 3—Oversized frame. The

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receive frame length is more than

MAX_FRAME_SIZE.
• Bit 4—Payload length error. The
actual frame payload length is
different from the value in the
length/type field.
• Bit 5—Overflow error. The
receive FIFO buffer is full while it
is still receiving data from the
MAC IP core.
avalon_st_rx_data output [NUM_CHANNELS][64] Carries the receive data to the
client.
avalon_st_rx_ output [NUM_CHANNELS][3] Contains the number of bytes
empty that are empty (not used) during
cycles that contain the end of a
packet.
avalon_st_tx_ output [NUM_CHANNELS] When asserted, this signal
status_valid qualifies
avalon_st_txstatus_data[] and
avalon_st_txstatus_error[].
avalon_st_tx_ output [NUM_CHANNELS][40] Contains information about the
status_data transmit frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates
a stacked VLAN frame.
• Bit 33: When set to 1, indicates
a VLAN frame.
• Bit 34: When set to 1, indicates
a control frame.
• Bit 35: When set to 1, indicates
a pause frame.
• Bit 36: When set to 1, indicates
a broadcast frame.
• Bit 37: When set to 1, indicates
a multicast frame.
• Bit 38: When set to 1, indicates
a unicast frame.
• Bit 39: When set to 1, indicates
a PFC frame.
avalon_st_tx_ output [NUM_CHANNELS][7] When set to 1, the respective bit
status_error indicates the following error type
in the receive frame.
• Bit 0: Undersized frame.
• Bit 1: Oversized frame.
• Bit 2: Payload length error.
• Bit 3: Unused.
• Bit 4: Underflow.
• Bit 5: Client error.

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• Bit 6: Unused.
The error status is invalid when
an overflow occurs.
avalon_st_rxstatus_ output [NUM_CHANNELS] When asserted, this signal
valid qualifies
avalon_st_txstatus_data[] and
avalon_st_txstatus_error[]. The
MAC IP core asserts this signal in
the same clock cycle
avalon_st_rx_endofpacket is
asserted.
avalon_st_rxstatus_ output [NUM_CHANNELS][40] Contains information about the
data transmit frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates
a stacked VLAN frame.
• Bit 33: When set to 1, indicates
a VLAN frame.
• Bit 34: When set to 1, indicates
a control frame.
• Bit 35: When set to 1, indicates
a pause frame.
• Bit 36: When set to 1, indicates
a broadcast frame.
• Bit 37: When set to 1, indicates
a multicast frame.
• Bit 38: When set to 1, indicates
a unicast frame.
• Bit 39: When set to 1, indicates
a PFC frame.
avalon_st_rxstatus_ output [NUM_CHANNELS][7] When set to 1, the respective bit
error indicates the following error type
in the receive frame.
• Bit 0: Undersized frame.
• Bit 1: Oversized frame.
• Bit 2: Payload length error.
• Bit 3: Unused.
• Bit 4: Underflow.
• Bit 5: Client error.
• Bit 6: Unused.
The error status is invalid when
an overflow occurs.
avalon_st_pause_ input [NUM_CHANNELS][2] Set this signal to the following
data values to trigger the
corresponding actions.
• 0x0: Stops pause frame
generation.
• 0x1: Generates an XON pause

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frame.
• 0x2: Generates an XOFF pause
frame. The MAC IP core sets the
pause quanta field in the pause
frame to the value in the
tx_pauseframe_quanta register.
• 0x3: Reserved.
Note: This signal only takes
effect if
tx_pauseframe_enable[2:1] is 00
(default)

4.6.4 Phy Interface

Signal Direction Width Description

rx_serial_data input [NUM_CHANNELS] RX serial input data
tx_serial_data output [NUM_CHANNELS] TX serial output data
ethernet_1g_an output [NUM_CHANNELS] Clause 37 Auto-Negotiation
status. The PCS function asserts
this signal when auto-negotiation
completes.
ethernet_1g_char_err output [NUM_CHANNELS] 10-bit character error
ethernet_1g_disp_err output [NUM_CHANNELS] Disparity error signal indicating a
10-bit running disparity error.
channel_ready output [NUM_CHANNELS] This signal is asserted when the
channel is ready for data
transmission.

4.6.5 1588v2 Timestamp Interface

Signal Direction Width Description

tx_egress_timestamp_96b_ output [NUM_CHANNELS] When asserted, this signal qualifies
valid the timestamp on
tx_egress_timestamp_96b_data[]
for the transmit frame whose
fingerprint is specified by
tx_egress_timestamp_96b_fingerpri
nt[].
tx_egress_timestamp_96b_ output [NUM_CHANNELS] Carries the 96-bit egress timestamp
data [96] in the following
format:
• Bits 48 to 95: 48-bit seconds
field
• Bits 16 to 47: 32-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field

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tx_egress_timestamp_96b_ output [NUM_CHANNELS] The fingerprint of the transmit

fingerprint [TSTAMP_FP_WIDT frame, which is received on
H] tx_egress_timestamp_request_data[
]. This fingerprint specifies the
transmit frame the egress
timestamp on
tx_egress_timestamp_96b_data[] is
for.
tx_egress_timestamp_64b_val output [NUM_CHANNELS] When asserted, this signal qualifies
id the timestamp on
tx_egress_timestamp_64b_data[]
for the transmit frame whose
fingerprint is specified by
tx_egress_timestamp_64b_fingerpri
nt[].
tx_egress_timestamp_64b_ output [NUM_CHANNELS] Carries the 64-bit egress timestamp
data [64] in the following format:
• Bits 16 to 63: 48-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_64b_ output [NUM_CHANNELS] The fingerprint of the transmit
fingerprint [TSTAMP_FP_WIDT frame, which is received on
H] tx_egress_timestamp_request_data[
]. This fingerprint specifies the
transmit frame the egress
timestamp on
tx_egress_timestamp_64b_data[] is
for.
rx_ingress_timestamp_96b_ output [NUM_CHANNELS] When asserted, this signal qualifies
valid the timestamp on
rx_ingress_timestamp_96b_data[].
The MAC IP core asserts this signal in
the same clock cycle it asserts
avalon_st_rx_startofpacket.
rx_ingress_timestamp_96b_ output [NUM_CHANNELS] Carries the 96-bit ingress timestamp
data [96] in the following format:
• Bits 48 to 95: 48-bit seconds field
• Bits 16 to 47: 32-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
rx_ingress_timestamp_64b_ output [NUM_CHANNELS] When asserted, this signal qualifies
valid the timestamp on
rx_ingress_timestamp_64b_data[].
The MAC IP core asserts this signal in
the same clock cycle it asserts
avalon_st_rx_startofpacket.
rx_ingress_timestamp_64b_ output [NUM_CHANNELS] Carries the 64-bit ingress timestamp

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data [64] in the following format:

• Bits 16 to 63: 48-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field

4.6.6 Packet Classifier Interface

Signal Direction Width Description

tx_egress_timestamp_request_in_val input [NUM_CHANNELS] Assert this signal when
id timestamp is required for the
particular frame. This signal
must be aligned to the start
of an incoming packet.
tx_egress_timestamp_request_in_fin input [NUM_CHANNELS] A width-configurable
gerprint [TSTAMP_ fingerprint that correlates
FP_WIDTH] timestamps for incoming
packets.
clock_operation_mode_mode input [NUM_CHANNELS] Determines the clock mode.
[2] • 00: Ordinary clock
• 01: Boundary clock
• 10: End to end
transparent clock
• 11: Peer to peer
transparent clock
pkt_with_crc_mode input [NUM_CHANNELS] Indicates whether or not a
packet contains CRC.
• 0: Packet contains
CRC
• 1: Packet does not
contain CRC
tx_ingress_timestamp_valid input [NUM_CHANNELS] Indicates the update for
residence time.
• 0: Prevents update for
residence time
• 1: Allows update for
residence time based on
decoded results
When this signal is
deasserted,
tx_etstamp_ins_ctrl_out_resi
dence_ti me_update also
gets deasserted.
tx_ingress_timestamp_96b_data input [NUM_CHANNELS] 96-bit format of ingress
[96] timestamp that holds data so
that the output can align
with the start of an incoming
packet.

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tx_ingress_timestamp_64b_data input [NUM_CHANNELS] 64-bit format of ingress

[64] timestamp that holds data so
that the output can align
with the start of an incoming
packet.
tx_ingress_timestamp_format input [NUM_CHANNELS] Format of the timestamp to
be used for calculating
residence time. This signal
must be aligned to the start
of an incoming packet. A
value of 0 indicates 96 bit
timestamp format while 1
indicates 64 bit timestamp
format.

4.6.7 TOD Interface

Signal Direction Width Description

master_pulse_per_ output 1 Pulse per second output from
second Master PPS module.
The pulse per second output
asserts for 10ms.
start_tod_sync input [NUM_CHANNELS] Start TOD synchronization
process. As long as this signal is
asserted high, the
synchronization process will
continue and time of day from
master TOD will be repeatedly
synchronized to local TOD.
pulse_per_second_ output [NUM_CHANNELS] Pulse per second output from
10g 10G PPS module in channel-n.
The pulse per second output
asserts for 10ms.
pulse_per_second_ output [NUM_CHANNELS] Pulse per second output from 1G
1g PPS module in channel-n. The
pulse per second output asserts
for 10ms.

4.7 Register Mapping

The following table shows the address offset for the Example Design and client logic at the Example
Design level.

Byte Offset Block

0x00_0000 - 0x00_EFFF Client Logic
0x00_F000 - 0x00_FFFF Reserved for Altera
0x01_0000 Master TOD

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0x02_0000 Port 0
0x03_0000 Port 1
0x04_0000 Port 2
0x05_0000 Port 3
0x06_0000 Port 4
0x07_0000 Port 5
0x08_0000 Port 6
0x09_0000 Port 7
0x0A_0000 Port 8
0x0B_0000 Port 9
0x0C_0000 Port 10
0x0D_0000 Port 11
0x0E_0000 onwards Client Logic

The following table shows per-port address offset for Example Design and client logic.

Byte Offset Sub-Block

0x0000 – 0x3FFF Reserved for Altera
0x4000 PHY
0x7800 10G TOD
0x7900 1G TOD
0x8000 1G/10G MAC

4.7.1 Master TOD

Master TOD registers are applicable only to Example Design with IEEE 1588v2.
The base address of the Master TOD registers is 0x01_0000.

Register Description and Address Offset for Master TOD

Byte Offset R/W Name Description HW Reset
0x0000 RW SecondsH Bits 0-15: High-order 16-bit second field 0x0
Bits 16-31: Not used
0x0004 RW SecondsL Bits 0-32: Low-order 32-bit second field 0x0
0x0008 RW NanoSec Bits 0-32: 32-bit nano-second field 0x0
0x0010 RW Period Bits 0-15: Period in fractional nano-second N
Bits 16-19: Period in nano-second
Bits 20-31: Not used
0x0014 RW AdjustPeriod The period for the offset adjustment 0x0
Bits 0-15: Period in fractional nano-second
Bits 16-19: Period in nano-second
Bits 20-31: Not used
0x0018 RW AdjustCount Bits 0-19: The number of AdjustedPeriod 0x0
clock cycles used during offset adjustment
Bits 20-31: Not used
0x1C RW DriftAdjust The drift of ToD adjusted periodically by 0x0
adding or subtracting a correction value as
configured in this register space.
• Bits 0 to 15: Adjustment value in fractional

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nanosecond (DRIFT_ADJUST_FNS). This value

is added to or subtracted from the current
ToD during the adjustment. The default value
is 0.
• Bits 16 to 19: Adjustment value in
nanosecond (DRIFT_ADJUST_NS). This value
is added to or subtracted from the current
ToD during the adjustment. The default value
is 0.
• Bits 20 to 31: Not used.
0x20 RW DriftAdjustRate The count of clock cycles for each ToD’s 0x0
drift adjustment to take effect.
• Bits 0 to 15: The number of clock cycles
(ADJUST_RATE). The ToD adjustment
happens once after every period in number of
clock cycles as indicated by this register
space.
• Bits 16 to 30: Not used.
• Bit 31: The direction of drift adjustment
• 0: Addition
• 1: Subtraction

4.7.2 1G TOD

1G TOD registers are only applicable for Example Design with IEEE 1588v2.
The base address of the per-port 1G TOD registers is defined as below.

Channel 1G TOD Registers Base Address

0 0x02_7900
1 0x03_7900
2 0x04_7900
3 0x05_7900
4 0x06_7900
5 0x07_7900
6 0x08_7900
7 0x09_7900
8 0x0A_7900
9 0x0B_7900
10 0x0C_7900
11 0x0D_7900

Register Description and Address Offset for 1G TOD

Byte Offset R/W Name Description HW Reset
0x0000 RW SecondsH Bits 0-15: High-order 16-bit second field 0x0
Bits 16-31: Not used
0x0004 RW SecondsL Bits 0-32: Low-order 32-bit second field 0x0
0x0008 RW NanoSec Bits 0-32: 32-bit nano-second field 0x0
0x0010 RW Period Bits 0-15: Period in fractional nano-second N
Bits 16-19: Period in nano-second

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Bits 20-31: Not used

0x0014 RW AdjustPeriod The period for the offset adjustment 0x0
Bits 0-15: Period in fractional nano-second
Bits 16-19: Period in nano-second
Bits 20-31: Not used
0x0018 RW AdjustCount Bits 0-19: The number of AdjustedPeriod 0x0
clock cycles used during offset adjustment
Bits 20-31: Not used
0x1C RW DriftAdjust The drift of ToD adjusted periodically by 0x0
adding or subtracting a correction value as
configured in this register space.
• Bits 0 to 15: Adjustment value in fractional
nanosecond (DRIFT_ADJUST_FNS). This value
is added to or subtracted from the current
ToD during the adjustment. The default value
is 0.
• Bits 16 to 19: Adjustment value in
nanosecond (DRIFT_ADJUST_NS). This value
is added to or subtracted from the current
ToD during the adjustment. The default value
is 0.
• Bits 20 to 31: Not used.
0x20 RW DriftAdjustRate The count of clock cycles for each ToD’s 0x0
drift adjustment to take effect.
• Bits 0 to 15: The number of clock cycles
(ADJUST_RATE). The ToD adjustment
happens once after every period in number of
clock cycles as indicated by this register
space.
• Bits 16 to 30: Not used.
• Bit 31: The direction of drift adjustment
• 0: Addition
• 1: Subtraction

4.7.3 10G TOD

10G TOD registers are only applicable for Example Design with IEEE 1588v2.
The base address of the per-port 10G TOD registers is defined as below.

Channel 1G TOD Registers Base Address

0 0x02_7800
1 0x03_7800
2 0x04_7800
3 0x05_7800
4 0x06_7800
5 0x07_7800
6 0x08_7800
7 0x09_7800
8 0x0A_7800

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9 0x0B_7800
10 0x0C_7800
11 0x0D_7800

Register Description and Address Offset for 10G TOD

Byte Offset R/W Name Description HW Reset
0x0000 RW SecondsH Bits 0-15: High-order 16-bit second field 0x0
Bits 16-31: Not used
0x0004 RW SecondsL Bits 0-32: Low-order 32-bit second field 0x0
0x0008 RW NanoSec Bits 0-32: 32-bit nano-second field 0x0
0x0010 RW Period Bits 0-15: Period in fractional nano-second N
Bits 16-19: Period in nano-second
Bits 20-31: Not used
0x0014 RW AdjustPeriod The period for the offset adjustment 0x0
Bits 0-15: Period in fractional nano-second
Bits 16-19: Period in nano-second
Bits 20-31: Not used
0x0018 RW AdjustCount Bits 0-19: The number of AdjustedPeriod 0x0
clock cycles used during offset adjustment
Bits 20-31: Not used
0x1C RW DriftAdjust The drift of ToD adjusted periodically by 0x0
adding or subtracting a correction value as
configured in this register space.
• Bits 0 to 15: Adjustment value in fractional
nanosecond (DRIFT_ADJUST_FNS). This value
is added to or subtracted from the current
ToD during the adjustment. The default value
is 0.
• Bits 16 to 19: Adjustment value in
nanosecond (DRIFT_ADJUST_NS). This value
is added to or subtracted from the current
ToD during the adjustment. The default value
is 0.
• Bits 20 to 31: Not used.
0x20 RW DriftAdjustRate The count of clock cycles for each ToD’s 0x0
drift adjustment to take effect.
• Bits 0 to 15: The number of clock cycles
(ADJUST_RATE). The ToD adjustment
happens once after every period in number of
clock cycles as indicated by this register
space.
• Bits 16 to 30: Not used.
• Bit 31: The direction of drift adjustment
• 0: Addition
• 1: Subtraction

4.7.4 PHY

PHY registers are applicable for both Example Design with and without IEEE 1588v2.

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The base address of the PHY registers is defined as below.

Channel 1G TOD Registers Base Address

0 0x02_4000
1 0x03_4000
2 0x04_4000
3 0x05_4000
4 0x06_4000
5 0x07_4000
6 0x08_4000
7 0x09_4000
8 0x0A_4000
9 0x0B_4000
10 0x0C_4000
11 0x0D_4000

Note: For detailed description of each PHY register please refer to Arria 10 Transceiver PHY IP User
Guide.

Note: The address offset in following PHY tables are in byte whereby the register map table in Arria 10
Transceiver PHY IP User Guide is in word.

PMA Registers
Byte Offset Bit R/W Name
0x1110 1 RW Reset_tx_digital
2 RW Reset_rx_analog
3 RW Reset_rx_digital
0x1184 RW Phy_serial_loopback
0x1190 RW Pma_rx_set_locktodata
0x1194 RW Pma_rx_set_locktoref
0x1198 RO Pma_rx_is_lockedtodata
0x119C RO Pma_rx_is_lockedtoref
0x12A0 0 RW Tx_invpolarity
1 RW Rx_invpolarity
2 RW Rx_bitreversal_enable
3 RW Rx_bytereversal_enable
4 RW Force_electrical_idle
0x12A4 0 R Rx_syncstatus
1 R Rx_patterndetect
2 R Rx_rlv
3 R Rx_rmfifodatainserted
4 R Rx_rmfifodatadeleted
5 R Rx_disperr
6 R Rx_errdetect

PCS Registers
Byte Offset Bit R/W Name
0x1200 RW Indirect_addr

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0x1204 2 RW Rclr_errblk_cnt
3 RW Rclr_ber_count
0x1208 1 RO Hi_ber
2 RO Block_lock
3 RO Tx_full
4 RO Rx_full
7 RO Rx_data_ready

Arria 10 GMII PCS Registers

Byte Offset Bit R/W Name
0x1240 9 RW Restart_auto_negotiation
12 RW Auto_negotiation_enable
15 RW Reset
0x1244 2 R Link_status
3 R Auto_negotiation_ability
5 R Auto_negotiation_complete
0x1250 5 RW FD
6 RW HD
8:7 RW PS2, PS1
13:12 RW RF2, RF1
14 RO ACK
15 RW NP
0x1254 5 R FD
6 R HD
8:7 R PS2, PS1
13:12 R RF2, RF1
14 R ACK
15 R NP
0x1258 0 R Link_partner_auto_negotiation_able
1 R Page_receive
0x1288 15:0 RW An_link_timer[15:0]
0x128C 4:0 RW An_link_timer[4:0]
0x1290 0 RW SGMII_ena
1 RW Use_SGMII_an
3:2 RW SGMII_speed

10GBASE-KR Registers
Byte Offset Bit R/W Name
0x12C0 0 RW Reset_seq
1 RW Disable_an_timer
2 RW Disable_lf_timer
6:4 RW Seq_force_mode[2:0]
16 RW FEC_ability
18 RW FEC_request
0x12C4 0 R Seq_link_request
1 R Seq_an_timeout
2 R Seq_lt_timeout
13:8 RW Seq_reconfig_mode[5:0]

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16 R KR_FEC_ability
17 R KR_FEC_err_ind_ability

4.7.5 1G/10G MAC

1G/10G MAC registers are applicable for both Example Design with and without IEEE 1588v2.
The base address of the 1G/10G MAC registers is defined as below.

Channel 1G TOD Registers Base Address

0 0x02_8000
1 0x03_8000
2 0x04_8000
3 0x05_8000
4 0x06_8000
5 0x07_8000
6 0x08_8000
7 0x09_8000
8 0x0A_8000
9 0x0B_8000
10 0x0C_8000
11 0x0D_8000

Note: For detailed description of each 1G/10G register please refer to Low Latency Ethernet 10G MAC
User Guide.

Note: The address offset in following 1G/10G tables are in byte whereby the register map table in Low
Latency Ethernet 10G MAC User Guide is in word.

Primary MAC Registers

Byte Offset R/W Name HW Reset
0x2008 RW Primary_mac_addr0 0x0
0x200C RW Primary_mac_addr1 0x0

Transmit Configuration and Status Registers

Byte Offset R/W Name HW Reset
0x4000 RW Tx_packet_control 0x0
0x4004 RO Tx_packet_status 0x0
0x4100 RW Tx_pad_control 0x1
0x4200 RW Tx_crc_control 0x3
0x4400 RW Tx_preamble_control 0x0
0x6004 RW Tx_frame_maxlength 0x5EE(1518)
0x4300 RO Tx_underflow_counter0 0x0
0x4304 RO Tx_underflow_counter1 0x0

Flow Control Registers

Byte Offset R/W Name HW Reset
0x4500 RW Tx_pauseframe_control 0x0

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0x4504 RW Tx_pauseframe_quanta 0x0

0x4508 RW Tx_pauseframe_enable 0x1
0x4680 RW Tx_pfc_priority_enable 0x0
0x4600 RW Pfc_pause_quanta_0 0x0
0x4604 RW Pfc_pause_quanta_1 0x0
0x4608 RW Pfc_pause_quanta_2 0x0
0x460C RW Pfc_pause_quanta_3 0x0
0x4610 RW Pfc_pause_quanta_4 0x0
0x4614 RW Pfc_pause_quanta_5 0x0
0x4618 RW Pfc_pause_quanta_6 0x0
0x461C RW Pfc_pause_quanta_7 0x0
0x4640 RW Pfc_holdoff_quanta_0 0x1
0x4644 RW Pfc_holdoff_quanta_1 0x1
0x4648 RW Pfc_holdoff_quanta_2 0x1
0x464C RW Pfc_holdoff_quanta_3 0x1
0x4650 RW Pfc_holdoff_quanta_4 0x1
0x4654 RW Pfc_holdoff_quanta_5 0x1
0x4658 RW Pfc_holdoff_quanta_6 0x1
0x465C RW Pfc_holdoff_quanta_7 0x1

Receive Configuration and Status Registers

Byte Offset R/W Name HW Reset
0x0000 RW Rx_transfer_control 0x0
0x0004 RO Rx_transfer_status 0x0
0x0100 RW Rx_padcrc_control 0x1
0x0200 RW Rx_crccheck_control 0x2
0x0400 RW Rx_custom_preamble_forward 0x0
0x0500 RW Rx_preamble_control 0x0
0x2000 RW Rx_frame_control 0x3
0x2004 RW Rx_frame_maxlength 1518
0x2010 RW Rx_frame_spaddr0_0 0x0
0x2014 RW Rx_frame_spaddr0_1 0x0
0x2018 RW Rx_frame_spaddr1_0 0x0
0x201C RW Rx_frame_spaddr1_1 0x0
0x2020 RW Rx_frame_spaddr2_0 0x0
0x2024 RW Rx_frame_spaddr2_1 0x0
0x2028 RW Rx_frame_spaddr3_0 0x0
0x202C RW Rx_frame_spaddr3_1 0x0
0x2060 RW Rx_pfc_control 0x1
0x0300 RO Rx_pktovrflow_error 0x0

Transmit Timestamp Registers

Byte Offset R/W Name HW Reset
0x4440 RW Tx_period_10G 0x33333
0x4448 RW Tx_fns_adjustment_10G 0x0
0x444C RW Tx_ns_adjustment_10G 0x0
0x4460 RW Tx_period_mult_speed 0x80000
0x4468 RW Tx_fns_adjustment_mult_speed 0x0

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0x446C RW Tx_ns_adjustment_mult_speed 0x0

Receive Timestamp Registers

Byte Offset R/W Name HW Reset
0x0440 RW Rx_period_10G 0x33333
0x0448 RW Rx_fns_adjustment_10G 0x0
0x044C RW Rx_ns_adjustment_10G 0x0
0x0460 RW Rx_period_mult_speed 0x80000
0x0468 RW Rx_fns_adjustment_mult_speed 0x0
0x046C RW Rx_ns_adjustment_mult_speed 0x0

Transmit and Receive Statistics Registers

Byte Offset R/W Name HW Reset
0x7000 RO Tx_stats_clr 0x0
0x3000 RO Rx_stats_clr 0x0
0x7008:0x700C RO Tx_stats_framesOK 0x0
0x3008:0x300C RO Rx_stats_framesOK 0x0
0x7010:0x7014 RO Tx_stats_framesErr 0x0
0x3010:0x3014 RO Rx_stats_framesErr 0x0
0x7018:0x701C RO Tx_stats_framesCRCErr 0x0
0x3018:0x301C RO Rx_stats_framesCRCErr 0x0
0x7020:0x7024 RO Tx_stats_octetsOK 0x0
0x3020:0x3024 RO Rx_stats_octetsOK 0x0
0x7028:0x702C RO Tx_stats_pauseMACCtrl_Frames 0x0
0x3028:0x302C RO Rx_stats_pauseMACCtrl_Frames 0x0
0x7030:0x7034 RO Tx_stats_1fErrors 0x0
0x3030:0x3034 RO Rx_stats_1fErrors 0x0
0x7038:0x703C RO Tx_stats_unicast_FramesOK 0x0
0x3038:0x303C RO Rx_stats_unicast_FramesOK 0x0
0x7040:0x7044 RO Tx_stats_unicast_FramesErr 0x0
0x3040:0x3044 RO Rx_stats_unicast_FramesErr 0x0
0x7048:0x704C RO Tx_stats_multicast_FramesOK 0x0
0x3048:0x304C RO Rx_stats_multicast_FramesOK 0x0
0x7050:0x7054 RO Tx_stats_multicast_FramesErr 0x0
0x3050:0x3054 RO Rx_stats_multicast_FramesErr 0x0
0x7058:0x705C RO Tx_stats_broadcast_FramesOK 0x0
0x3058:0x305C RO Rx_stats_broadcast_FramesOK 0x0
0x7060:0x7064 RO Tx_stats_broadcast_FramesErr 0x0
0x3060:0x3064 RO Rx_stats_broadcast_FramesErr 0x0
0x7068:0x706C RO Tx_stats_etherStatsOctets 0x0
0x3068:0x306C RO Rx_stats_etherStatsOctets 0x0
0x7070:0x7074 RO Tx_stats_etherStatsPkts 0x0
0x3070:0x3074 RO Rx_stats_etherStatsPkts 0x0
0x7078:0x707C RO Tx_stats_etherStatsUndersizePkts 0x0
0x3078:0x307C RO Rx_stats_etherStatsUndersizePkts 0x0
0x7080:0x7084 RO Tx_stats_etherStatsOversizePkts 0x0
0x3080:0x3084 RO Rx_stats_etherStatsOversizePkts 0x0
0x7088:0x708C RO Tx_stats_etherStatsPkts64Octets 0x0

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0x3088:0x308C RO Rx_stats_etherStatsPkts64Octets 0x0

0x7090:0x7094 RO Tx_stats_etherStatsPkts65to127Octets 0x0
0x3090:0x3094 RO Rx_stats_etherStatsPkts65to127Octets 0x0
0x7098:0x709C RO Tx_stats_etherStatsPkts128to255Octets 0x0
0x3098:0x309C RO Rx_stats_etherStatsPkts128to255Octets 0x0
0x70A0:0x70A4 RO Tx_stats_etherStatsPkts256to511Octets 0x0
0x30A0:0x30A4 RO Rx_stats_etherStatsPkts256to511Octets 0x0
0x70A8:0x70AC RO Tx_stats_etherStatsPkts512to1023Octets 0x0
0x30A8:0x30AC RO Rx_stats_etherStatsPkts512to1023Octets 0x0
0x70B0:0x70B4 RO Tx_stats_etherStatsPkts1024to1518Octets 0x0
0x30B0:0x30B4 RO Rx_stats_etherStatsPkts1024to1518Octets 0x0
0x70B8:0x70BC RO Tx_stats_etherStatsPkts1519toXOctets 0x0
0x30B8:0x30BC RO Rx_stats_etherStatsPkts1519toXOctets 0x0
0x70C0:0x70C4 RO Tx_stats_etherStatsFragments 0x0
0x30C0:0x30C4 RO Rx_stats_etherStatsFragments 0x0
0x70C8:0x70CC RO Tx_stats_etherStatsJabbers 0x0
0x30C8:0x30CC RO Rx_stats_etherStatsJabbers 0x0
0x70D0:0x70D4 RO Tx_stats_etherStatsCRCErr 0x0
0x30D0:0x30D4 RO Rx_stats_etherStatsCRCErr 0x0
0x70D8:0x70DC RO Tx_stats_unicastMACCtrlFrames 0x0
0x30D8:0x30DC RO Rx_stats_unicastMACCtrlFrames 0x0
0x70E0:0x70E4 RO Tx_stats_multicastMACCtrlFrames 0x0
0x30E0:0x30E4 RO Rx_stats_multicastMACCtrlFrames 0x0
0x70E8:0x70EC RO Tx_stats_broadcastMACCtrlFrames 0x0
0x30E8:0x30EC RO Rx_stats_broadcastMACCtrlFrames 0x0
0x70F0:0x70F4 RO Tx_stats_PFCMACCtrlFrames 0x0
0x30F0:0x30F4 RO Rx_stats_PFCMACCtrlFrames 0x0

4.8 Simulating the Example Design

4.8.1 Simulation Collateral

The following table describes files that implement the Example Design testbench. The collateral can be
found under <Example Design>/simulation/ed_sim/models.

File Description
all_modes.mif Memory initialization file (MIF) used for reconfiguration to
change speed.
avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that uses the BFMs to form the
transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to the
DUT, you must not change the contents of this file.

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avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST

transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.

4.8.2 Simulation Test Cases

The test cases are included to demonstrate how to change the channel speed to 10G/1G/100M/10M
and MAC & PHY configuration. The test cases are using circular loopback on total number of channels
selected by users through IP Parameter Editor during Example Design generation.

Configuring PHY Speed

After reset, all ports are set in 10G and auto speed detection mode by default. Use the PHY memory
map to change to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X or 1G/100M/10M
SGMII.

Changing Speed between 10G and 1G in 1000BaseX mode

The software can turn off auto speed detection and force the PHY to either 1G or 10G by writing a
different value to the PHY register address at offset 0x12C0.

Register value for speed change in 1000BaseX mode in Arria 10 Transceiver PHY IP
Value Description
0x01 Reset back to auto speed detection mode
0x11 Turn off auto speed detection and force the PHY to 1G
0x41 Turn off auto speed detection and force the PHY to 10G

Example 1: Forcing Port 0 to 1000Base-X mode

Set Port 0 to 1000Base-X: write_32 0x02_52C0 0x11

Example 2: Reset Port 0 to auto speed detection mode

Set Port 0 to auto speed detection mode: write_32 0x02_52C0 0x01

Changing Speed between 1G, 100M and 10M SGMII

To enable SGMII, the software needs to write a different value to the PHY register address offset
0x1290. Set the port to 1000Base-X mode first before select any SGMII modes.

Register value for speed change in SGMII mode in Arria 10 Transceiver PHY IP
Value Description
0x01 Enable SGMII mode and force speed to 10M
0x03 Enable SGMII mode and use SGMII auto negotiation
0x05 Enable SGMII mode and force speed to 100M
0x09 Enable SGMII mode and force speed to 1G

Example 3: Forcing Port 0 to SGMII 100M mode

Set Port 0 to 1000Base-X: write_32 0x02_52C0 0x11
Set Port 0 to SGMII 100M: write_32 0x02_5290 0x05

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Test Scenario for Example Design without IEEE 1588v2

1. Set the start up with channel configured to 10G mode.
2. Perform basic MAC configuration, PHY speed configuration and FIFO configuration for all 2 channels.
3. Wait for the Example Design to assert the channel_ready signals for all 2 channels.
4. Send the following packets:
• Normal data frame, 64Bytes
• SVLAN data frame, broadcast, 64Bytes
• VLAN data frame, unicast, 500Bytes
5. Repeat Step 2 to Step 4 for 1G, 100M and 10M speed mode.
6. When the simulation ends, refer to the transcript window for channel 0 MAC TX and RX statistic
counter results.
7. If channel 0 Avalon_st RX interface successfully received all 28 packets, the transcript will display a
PASSED.

Channel 0 MAC Tx Statistic Counter

<Snapshot of simulation output>

Channel 0 MAC Rx Statistic Counter

<Snapshot of simulation output>

Test Scenario for Example Design with IEEE 1588v2

1. Set the start up with channel configured to 10G mode.
2. Perform basic MAC configuration, PHY speed configuration, 1588 component configuration and PTP
clock mode configuration for all 2 channels.
3. Wait for the Example Design to assert the channel_ready signals for all 2 channels.
4. Send the following packets:
• Non-PTP
• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
5. Repeat Step 2 to Step 4 for 1G, 100M and 10M speed mode.
6. When the simulation ends, refer to the transcript window for channel 0 MAC TX and RX statistic
counter results.
7. If channel 0 Avalon_st RX interface successfully received all 28 packets, the transcript will display a
PASSED.

Channel 0 MAC Tx Statistic Counter

<Snapshot of simulation output>

Channel 0 MAC Rx Statistic Counter

<Snapshot of simulation output>

4.9 Testing the Example Design in Hardware

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4.9.1 Hardware Setup

The following hardware boards are supported for the sample Example Design. For each hardware board,
we provide a predefined pin assignment. The Example Design recommendations require that System
console must be used for controlling the hardware platform and providing User Interface.

Arria 10 GX Transceiver Signal Integrity Development Kit is supported for acds 15.1

The predefined pin assignment is inside the generated .qsf file. In order to use the design with
predefined pin assignment for hardware test, user needs to select “ Arria 10 GX Transceiver Signal Integrity
Development Kit” as target development kit in the GUI.

Note: The current devkit display in the GUI is “Arria 10 FPGA Signal Integrity Kit”, which is not correct
and will be fixed in 15.1.1

The following diagram illustrates the board setup for hardware test.

4.9.2 Timing Closure

Example Design component’s timing constraints will be automatically loaded during Quartus
compilation. Example Design level timing constraints can be found at <Example
Design>/altera_eth_top.sdc.

User needs to include the loading of ToD and ToDSync sdc file command in the .qsf file, if generating the
ED does not include the following automatically. The following is the example.

set_global_assignment -name SDC_FILE rtl/altera_eth_1588_tod/altera_eth_1588_tod.sdc

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set_global_assignment –name SDC_FILE

rtl/altera_eth_1588_tod_sync/altera_eth_1588_tod_synchronizer.sdc

These 2 lines are already inside the .qsf for 1588 variant when user generates the ED.

There are multiple SDC constraints involved here:

-PHY SDC - to cut paths between 1G/10G;

-MAC SDC - this includes DC-FIFO constraints;
-Top-level - for clock and PHY <-> MAC interaction

The key constraints for 10M/100M/1G/10G with 1588 are

set_clock_groups -asynchronous -group [get_clocks rxclk_8g_ch*] -group [get_clocks ${rx_10g_clk}]
set_clock_groups -asynchronous -group [get_clocks txclk_8g_ch*] -group [get_clocks ${tx_10g_clk}]

The additional constraints needed when connecting LL 10G MAC to 10G base-KR IP are
(assuming user has already created clocks for 10G and 1G)
set_clock_groups -asynchronous -group [get_clocks <TX 1G clock>] -group [get_clocks ${TX 10G clock}]
set_clock_groups -asynchronous -group [get_clocks <RX 1G clock>] -group [get_clocks ${RX 10G clock}]

To Do (Done): To include some notes from FB#303505: Example Design constraints that users would
have to include in own system setup.

4.9.3 SignalTap Signaling

The following table captures the SignalTap debug signals.

10M/100M/1G/10G Ethernet without 1588

1G/10G Ethernet without 1588

Compone Module Name Signal

nt

Example altera_eth_top mm_clk

Design
Top Level ref_clk_1g

ref_clk_10g

channel_ready_n

channel_reset_n

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master_reset_n

Multi altera_eth_top. altera_eth_multi_channel pll_locked

Channel
pll_1_locked

pll_locked_10g

pll_locked_1g

MAC altera_eth_top. altera_eth_multi_channel. avalon_st_rx_data

altera_eth_channel.altera_eth_10g_mac
avalon_st_rx_empty

avalon_st_rx_endofpacket

avalon_st_rx_error

avalon_st_rx_startofpacke
t

avalon_st_rx_ready

avalon_st_rx_valid

avalon_st_tx_data

avalon_st_tx_empty

avalon_st_tx_endofpacket

avalon_st_tx_error

avalon_st_tx_ready

avalon_st_tx_startofpacke
t

avalon_st_tx_valid

PHY altera_eth_top. altera_eth_multi_channel. led_an

altera_eth_channel.altera_eth_10gkr_phy
led_char_err

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led_disp_err

led_link

mii_speed_sel (Only for

10M/100M/1G/10G
Ethernet)

rx_analogreset

rx_block_lock

rx_cal_busy

rx_is_lockedtodata

rx_digitalreset

rx_data_ready

tx_analogreset

tx_digitalreset

XGMII altera_eth_top. altera_eth_multi_channel. xgmii_rx_control

Interface altera_eth_channel.altera_eth_10g_mac.alt_em10g32.alt_e
xgmii_rx_data
m10g32unit
xgmii_tx_control

xgmii_tx_data

link_fault_status_xgmii_rx
_data

GMII altera_eth_top. altera_eth_multi_channel. gmii_rx_d

Interface altera_eth_channel.altera_eth_10g_mac
gmii_rx_dv

gmii_rx_err

gmii_tx_d

gmii_tx_en

gmii_tx_err

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MII altera_eth_top. altera_eth_multi_channel. mii_rx_dv

Interface altera_eth_channel.altera_eth_10g_mac
mii_rx_err

mii_tx_d
(Only for 10M/100M/1G/10G Ethernet)
mii_tx_en

mii_tx_err

10M/100M/1G/10G Ethernet with 1588

1G/10G Ethernet with 1588

Comp Module Name Signal

onent

Examp altera_eth_top mm_clk

le
ref_clk_1g
Desig
n Top ref_clk_10g
Level
channel_ready_n

channel_reset_n

master_reset_n

Multi altera_eth_top.altera_eth_multi_channel_1588 pll_locked

Chann
pll_1_locked
el
pll_2_locked

pll_locked_10g

pll_locked_1g

MAC altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_15 avalon_st_rx_dat

88.altera_eth_10g_mac a

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avalon_st_rx_em
pty

avalon_st_rx_end
ofpacket

avalon_st_rx_erro
r

avalon_st_rx_star
tofpacket

avalon_st_rx_rea
dy

avalon_st_rx_vali
d

avalon_st_tx_dat
a

avalon_st_tx_em
pty

avalon_st_tx_end
ofpacket

avalon_st_tx_erro
r

avalon_st_tx_rea
dy

avalon_st_tx_star
tofpacket

avalon_st_tx_vali
d

PHY altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_15 led_an

88.altera_eth_10gkr_phy
led_char_err

led_disp_err

led_link

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mii_speed_sel
(Only for
10M/100M/1G/1
0G Ethernet with
1588)

rx_analogreset

rx_block_lock

rx_cal_busy

rx_is_lockedtodat
a

rx_digitalreset

rx_data_ready

tx_analogreset

tx_digitalreset

XGMII altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_15 xgmii_rx_control

Interf 88.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit
ace xgmii_rx_data

xgmii_tx_control

xgmii_tx_data

link_fault_status_
xgmii_rx_data

GMII altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_15 gmii_rx_d

Interf 88.altera_eth_10g_mac
ace gmii_rx_dv

gmii_rx_err

gmii_tx_d

gmii_tx_en

gmii_tx_err

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MII altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_15 mii_rx_dv

Interf 88.altera_eth_10g_mac
ace mii_rx_err

mii_tx_d
(Only for 10M/100M/1G/10G Ethernet with 1588)
mii_tx_en

mii_tx_err

To Do (Done): Provide useful debugging signals if users would want to include SignalTap in Hardware
bring-up and debugging. Please note that SignalTap instantiation will impact timing closure and users
would need to ensure timing closure with SignalTap prior to hardware bring-up.

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5 Functional Description: 1G-10G Ethernet Example Design

The following Example Designs demonstrate Altera Low Latency Ethernet 10G MAC IP systems using
Arria 10 PHY in 1G-10G mode.

Instead of copying all the information from the Chapter 4, the key differences are mentioned below.
 All the MII (10M/100M) related ports/registers will be absent here.
 The Phy will not have the port ‘ mii_speed_sel’
 The value of the synthesis parameter ‘SYNTH_MII’ is 0

To Do (Done): Sync all info from Chapter 4 with updated required on 1G-10G speed mode switch.

5.1 Software and Hardware Requirement

Altera uses the following software and hardware to test the Example Design and testbench in Linux
platform.

 Quartus Prime.
 System Console. The user guide can be found at link:
http://www.altera.com/literature/ug/ug_system_console.pdf
 Simulators: Modelsim-AE, Modelsim-SE, NCsim or VCS (for complete simulators revision please refer
to link-TBD).
 Hardware: Arria 10 FPGA Development Kit (device TBD).

5.2 Feature

The Example Design offers the following features:

• Support 1 Gigabits per second (Gbps) and 10 Gigabits per second (Gbps) with Arria 10 1G/10G PHY.
• Support scalability from 1 to 12 channels Ethernet MAC and PHY.
• Provide packet monitoring system on transmit and receive data paths and report Ethernet MAC
statistics counters for transmit and receive datapath.
• Support testing using different types of Ethernet packet transfer with or without IEEE 1588v2
features.

The block diagrams and the example design components remain the same as in the section 4.2. MDIO
block and its connections need to be removed.

Example Design Components

ED Component Without IEEE 1588v2 With IEEE 1588v2

Low latency Ethernet 10G Ethernet MAC IP core
MAC
Arria 10 1G/10G PHY Altera 1G/10G and 10GBASE-KR PHY IP
Address decoder channel Address decoder module for each component within the channel,
for example, MAC and PHY.

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Address decoder multichannel Address decoder module for all channels and components within
multichannel level, for example Master TOD.
Reset controller Reset modules which handle reset synchronization for all ED
components.
Master PLL Generates clocks for all the components in the Example Design.
Arria 10 ATX PLL Generates a TX serial clock for Arria 10 10G transceiver.
Arria 10 fractional PLL Generates a TX serial clock for Arria 10 1G transceiver.
FIFO Avalon Streaming (Avalon-ST) ---
singleclock or dual-clock FIFO
that buffers the receive and
transmit data between the MAC
and client.
Master Time-of-Day --- Provides a master TOD for all
(TOD) channels.
TOD Sync --- Module to synch time of day
from Master TOD to Local TOD
for all channels.
Local TOD --- TOD module in each channel.
Master pulse per second --- Returns pulse per second (pps)
module to user for all channels.
1G/10G Pulse Per Second --- Returns pulse per second (pps)
module to user in each channel.
PTP packet classifier --- Decodes the packet type of
incoming PTP packets and
returns the decoded
information to the Ethernet
MAC.

5.3 Clocking

Refer to the section 4.3. MDIO block and its connections need to be removed.

5.4 Reset

Refer to the section 4.4. MDIO block and its connections need to be removed.

5.5 Parameter Setting

5.5.1 Example Design Parameters

Parameter Without IEEE 1588v2 With IEEE 1588v2

IP Parameters
Speed 1G/10G 1G/10G
Datapath options Tx & Rx Tx & Rx
Enable ECC on memory blocks uncheck uncheck
Enable preamble pass-through mode uncheck uncheck

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Enable priority-based flow control (PFC) uncheck uncheck

Number of PFC queues Don’t care Don’t care
Enable unidirectional feature uncheck uncheck
Enable 10GBASE-R register mode uncheck uncheck
Enable supplementary address User input User input
Enable statistics collection checked checked
Statistics counters User input User input
Enable time stamping uncheck checked
Enable PTP one-step clock support Don’t care checked
Timestamp fingerprint width Don’t care 4
Time Of Day Format Don’t care Enable both 96b & 64b
Use legacy XGMII interface checked checked
Use legacy Avalon Memory-Mapped checked checked
interface
Use legacy Avalon Streaming interface checked checked
Example Design Parameters
Specific Number of Channels 1 – 12 1 – 12

5.5.2 PHY Pre-Set Parameters

The Example Design is using Arria 10 1G/10GbE with a pre-set PHY parameter setting that matches the
pairing with LL10GE-MAC IP. Refer to the section 4.5.2 for the list of the parameters. The differing
parameter is shown below.

Phy Parameter Without IEEE With IEEE

1588v2 1588v2
Expanded name Abbreviated name
Enable SYNTH_MII 0 0
10Mb/100Mb
Ethernet
functionality

To Do (Done): List down all preset PHY parameter values for users reference.

5.6 Interface Signaling

This section describes the interface signals at Example Design level.

The NUM_UNSHARED_CHANNELS are determined by the equation below:

NUM_UNSHARED_CHANNELS = (SHARED_REFCLK_EN == 1) ? 1: NUM_CHANNELS

NUM_CHANNELS is parameter set by users from IP Parameter Editor.

5.6.1 Clock & Reset

Signal Direction Width Description

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mm_clk input 1 Configuration clock for Avalon-

MM interface. Frequency is
125 MHz.
pll_ref_clk_1g input [NUM_UNSHARED_CHANNELS Reference clock for the TX PLL
] in 1G mode. Frequency is 125
MHz.
pll_ref_clk_10g input [NUM_UNSHARED_CHANNELS Reference clock for the TX PLL
] in 10G mode. Frequency is
644.53125 MHz.
cdr_ref_clk_1g input [NUM_UNSHARED_CHANNELS Reference clock for the RX PLL
] in 1G mode. Frequency is 125
MHz.
cdr_ref_clk_10g input [NUM_UNSHARED_CHANNELS Reference clock for the RX PLL
] in 10G mode. Frequency is
644.53125 MHz.
channel_reset_n input [NUM_CHANNELS] To reset individual Ethernet
channel. This does not impact
the components running at
multi_channel level, e.g.
master TOD, master PPS and
fPLLs. Asynchronous and
active low signal.
master_reset_n input 1 To reset the whole Example
Design. Asynchronous and
active low signal.
xgmii_clk output [NUM_UNSHARED_CHANNELS Clock used for single data rate
] (SDR) XGMII TX & RX interface
in between MAC and PHY. This
clock is also used for Avalon-ST
interface. Frequency is
156.25MHz.
rx_recovered_clk output [NUM_CHANNELS] This is the RX clock, which is
recovered from the received
data.

5.6.2 Avalon-MM Interface

Signal Direction Width Description

write input 1 Assert this signal to request a
write.
read input 1 Assert this signal to request a
read.
address input 20 Use this bus to specify the register
address you want to read from or
write to.
writedata input 32 Carries the data to be written to
the specified register.
readdata output 32 Carries the data read from the

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specified register.
waitrequest output 1 When asserted, this signal
indicates that the IP core is busy
and not ready to accept any read
or write requests.

5.6.3 Avalon-ST Interface

Signal Direction Width Description

avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to mark the
startofpacket beginning of the transmit data on
the Avalon-ST interface.
avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to mark the end
endofpacket of the transmit data on the
Avalon-ST interface.
avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to indicate that
valid avalon_st_tx_data and other
signals on this interface are valid.
avalon_st_tx_ output [NUM_CHANNELS] When asserted, this signal
ready indicates that the MAC IP core is
ready to accept data.
avalon_st_tx_ input [NUM_CHANNELS] Assert this signal to indicate the
error current transmit packet contains
errors.
avalon_st_tx_data input [NUM_CHANNELS][64] Carries the transmit data from
the client.
avalon_st_tx_ input [NUM_CHANNELS][3] Use this signal to specify the
empty number of bytes that are empty
(not used) during cycles that
contain the end of a packet.
0x0=All bytes are valid.
0x1=The last byte is invalid.
0x2=The last two bytes are
invalid.
0x3=The last three bytes are
invalid.
avalon_st_rx_ output [NUM_CHANNELS] When asserted, this signal marks
startofpacket the beginning of the receive data
on the Avalon-ST interface.
avalon_st_rx_ output [NUM_CHANNELS] When asserted, this signal marks
endofpacket the end of the receive data on the
Avalon-ST interface.
avalon_st_rx_ output [NUM_CHANNELS] When asserted, this signal
valid indicates that
avalon_st_rx_data[]and other
signals on this interface are valid.
avalon_st_rx_ input [NUM_CHANNELS] Assert this signal when the client
ready is ready to accept data.

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avalon_st_rx_ output [NUM_CHANNELS][6] When set to 1, the respective bits

error indicate an error type:
• Bit 0—PHY error. For 10 Gbps,
the data on xgmii_rx_data
contains a control error character
(FE). For 10 Mbps,100 Mbps,1
Gbps, gmii_rx_err or mii_rx_err is
asserted.
• Bit 1—CRC error. The computed
CRC value differs from the
received CRC.
• Bit 2—Undersized frame. The
receive frame length is less than
64 bytes.
• Bit 3—Oversized frame. The
receive frame length is more than
MAX_FRAME_SIZE.
• Bit 4—Payload length error. The
actual frame payload length is
different from the value in the
length/type field.
• Bit 5—Overflow error. The
receive FIFO buffer is full while it
is still receiving data from the
MAC IP core.
avalon_st_rx_data output [NUM_CHANNELS][64] Carries the receive data to the
client.
avalon_st_rx_ output [NUM_CHANNELS][3] Contains the number of bytes
empty that are empty (not used) during
cycles that contain the end of a
packet.
avalon_st_tx_ output [NUM_CHANNELS] When asserted, this signal
status_valid qualifies
avalon_st_txstatus_data[] and
avalon_st_txstatus_error[].
avalon_st_tx_ output [NUM_CHANNELS][40] Contains information about the
status_data transmit frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates
a stacked VLAN frame.
• Bit 33: When set to 1, indicates
a VLAN frame.
• Bit 34: When set to 1, indicates
a control frame.
• Bit 35: When set to 1, indicates
a pause frame.
• Bit 36: When set to 1, indicates
a broadcast frame.

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• Bit 37: When set to 1, indicates

a multicast frame.
• Bit 38: When set to 1, indicates
a unicast frame.
• Bit 39: When set to 1, indicates
a PFC frame.
avalon_st_tx_ output [NUM_CHANNELS][7] When set to 1, the respective bit
status_error indicates the following error type
in the receive frame.
• Bit 0: Undersized frame.
• Bit 1: Oversized frame.
• Bit 2: Payload length error.
• Bit 3: Unused.
• Bit 4: Underflow.
• Bit 5: Client error.
• Bit 6: Unused.
The error status is invalid when
an overflow occurs.
avalon_st_rxstatus_ output [NUM_CHANNELS] When asserted, this signal
valid qualifies
avalon_st_txstatus_data[] and
avalon_st_txstatus_error[]. The
MAC IP core asserts this signal in
the same clock cycle
avalon_st_rx_endofpacket is
asserted.
avalon_st_rxstatus_ output [NUM_CHANNELS][40] Contains information about the
data transmit frame.
• Bits 0 to 15: Payload length.
• Bits 16 to 31: Packet length.
• Bit 32: When set to 1, indicates
a stacked VLAN frame.
• Bit 33: When set to 1, indicates
a VLAN frame.
• Bit 34: When set to 1, indicates
a control frame.
• Bit 35: When set to 1, indicates
a pause frame.
• Bit 36: When set to 1, indicates
a broadcast frame.
• Bit 37: When set to 1, indicates
a multicast frame.
• Bit 38: When set to 1, indicates
a unicast frame.
• Bit 39: When set to 1, indicates
a PFC frame.
avalon_st_rxstatus_ output [NUM_CHANNELS][7] When set to 1, the respective bit
error indicates the following error type
in the receive frame.

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• Bit 0: Undersized frame.

• Bit 1: Oversized frame.
• Bit 2: Payload length error.
• Bit 3: Unused.
• Bit 4: Underflow.
• Bit 5: Client error.
• Bit 6: Unused.
The error status is invalid when
an overflow occurs.
avalon_st_pause_ input [NUM_CHANNELS][2] Set this signal to the following
data values to trigger the
corresponding actions.
• 0x0: Stops pause frame
generation.
• 0x1: Generates an XON pause
frame.
• 0x2: Generates an XOFF pause
frame. The MAC IP core sets the
pause quanta field in the pause
frame to the value in the
tx_pauseframe_quanta register.
• 0x3: Reserved.
Note: This signal only takes
effect if
tx_pauseframe_enable[2:1] is 00
(default)

5.6.4 Phy Interface

Signal Direction Width Description

rx_serial_data input [NUM_CHANNELS] RX serial input data
tx_serial_data output [NUM_CHANNELS] TX serial output data
ethernet_1g_an output [NUM_CHANNELS] Clause 37 Auto-Negotiation
status. The PCS function asserts
this signal when auto-negotiation
completes.
ethernet_1g_char_err output [NUM_CHANNELS] 10-bit character error
ethernet_1g_disp_err output [NUM_CHANNELS] Disparity error signal indicating a
10-bit running disparity error.
channel_ready output [NUM_CHANNELS] This signal is asserted when the
channel is ready for data
transmission.

5.6.5 1588v2 Timestamp Interface

Signal Direction Width Description

tx_egress_timestamp_96b_ output [NUM_CHANNELS] When asserted, this signal qualifies

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valid the timestamp on

tx_egress_timestamp_96b_data[]
for the transmit frame whose
fingerprint is specified by
tx_egress_timestamp_96b_fingerpri
nt[].
tx_egress_timestamp_96b_ output [NUM_CHANNELS] Carries the 96-bit egress timestamp
data [96] in the following
format:
• Bits 48 to 95: 48-bit seconds
field
• Bits 16 to 47: 32-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_96b_ output [NUM_CHANNELS] The fingerprint of the transmit
fingerprint [TSTAMP_FP_WIDT frame, which is received on
H] tx_egress_timestamp_request_data[
]. This fingerprint specifies the
transmit frame the egress
timestamp on
tx_egress_timestamp_96b_data[] is
for.
tx_egress_timestamp_64b_val output [NUM_CHANNELS] When asserted, this signal qualifies
id the timestamp on
tx_egress_timestamp_64b_data[]
for the transmit frame whose
fingerprint is specified by
tx_egress_timestamp_64b_fingerpri
nt[].
tx_egress_timestamp_64b_ output [NUM_CHANNELS] Carries the 64-bit egress timestamp
data [64] in the following format:
• Bits 16 to 63: 48-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_64b_ output [NUM_CHANNELS] The fingerprint of the transmit
fingerprint [TSTAMP_FP_WIDT frame, which is received on
H] tx_egress_timestamp_request_data[
]. This fingerprint specifies the
transmit frame the egress
timestamp on
tx_egress_timestamp_64b_data[] is
for.
rx_ingress_timestamp_96b_ output [NUM_CHANNELS] When asserted, this signal qualifies
valid the timestamp on
rx_ingress_timestamp_96b_data[].
The MAC IP core asserts this signal in
the same clock cycle it asserts

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avalon_st_rx_startofpacket.
rx_ingress_timestamp_96b_ output [NUM_CHANNELS] Carries the 96-bit ingress timestamp
data [96] in the following format:
• Bits 48 to 95: 48-bit seconds field
• Bits 16 to 47: 32-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field
rx_ingress_timestamp_64b_ output [NUM_CHANNELS] When asserted, this signal qualifies
valid the timestamp on
rx_ingress_timestamp_64b_data[].
The MAC IP core asserts this signal in
the same clock cycle it asserts
avalon_st_rx_startofpacket.
rx_ingress_timestamp_64b_ output [NUM_CHANNELS] Carries the 64-bit ingress timestamp
data [64] in the following format:
• Bits 16 to 63: 48-bit nanoseconds
field
• Bits 0 to 15: 16-bit fractional
nanoseconds field

5.6.6 Packet Classifier Interface

Signal Direction Width Description

tx_egress_timestamp_request_in_val input [NUM_CHANNELS] Assert this signal when
id timestamp is required for the
particular frame. This signal
must be aligned to the start
of an incoming packet.
tx_egress_timestamp_request_in_fin input [NUM_CHANNELS] A width-configurable
gerprint [TSTAMP_ fingerprint that correlates
FP_WIDTH] timestamps for incoming
packets.
clock_operation_mode_mode input [NUM_CHANNELS] Determines the clock mode.
[2] • 00: Ordinary clock
• 01: Boundary clock
• 10: End to end
transparent clock
• 11: Peer to peer
transparent clock
pkt_with_crc_mode input [NUM_CHANNELS] Indicates whether or not a
packet contains CRC.
• 0: Packet contains
CRC
• 1: Packet does not
contain CRC

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tx_ingress_timestamp_valid input [NUM_CHANNELS] Indicates the update for

residence time.
• 0: Prevents update for
residence time
• 1: Allows update for
residence time based on
decoded results
When this signal is
deasserted,
tx_etstamp_ins_ctrl_out_resi
dence_ti me_update also
gets deasserted.
tx_ingress_timestamp_96b_data input [NUM_CHANNELS] 96-bit format of ingress
[96] timestamp that holds data so
that the output can align
with the start of an incoming
packet.
tx_ingress_timestamp_64b_data input [NUM_CHANNELS] 64-bit format of ingress
[64] timestamp that holds data so
that the output can align
with the start of an incoming
packet.
tx_ingress_timestamp_format input [NUM_CHANNELS] Format of the timestamp to
be used for calculating
residence time. This signal
must be aligned to the start
of an incoming packet. A
value of 0 indicates 96 bit
timestamp format while 1
indicates 64 bit timestamp
format.

5.6.7 TOD Interface

Signal Direction Width Description

master_pulse_per_ output 1 Pulse per second output from
second Master PPS module.
The pulse per second output
asserts for 10ms.
start_tod_sync input [NUM_CHANNELS] Start TOD synchronization
process. As long as this signal is
asserted high, the
synchronization process will
continue and time of day from
master TOD will be repeatedly
synchronized to local TOD.
pulse_per_second_ output [NUM_CHANNELS] Pulse per second output from
10g 10G PPS module in channel-n.

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The pulse per second output

asserts for 10ms.
pulse_per_second_ output [NUM_CHANNELS] Pulse per second output from 1G
1g PPS module in channel-n. The
pulse per second output asserts
for 10ms.

5.7 Register Mapping

The tables in 4.7 show the address offsets for the Example Design and client logic at the Example Design
level.

5.8 Simulating the Example Design

5.8.1 Simulation Collateral

The following table describes files that implement the Example Design testbench. The collateral can be
found under <Example Design>/simulation/ed_sim/models.

File Description
all_modes.mif Memory initialization file (MIF) used for reconfiguration to
change speed.
avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that uses the BFMs to form the
transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to the
DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.

5.8.2 Simulation Test Cases

The test cases are included to demonstrate how to change the channel speed to 10G/1G and MAC &
PHY configuration. The test cases are using circular loopback on total number of channels selected by
users through IP Parameter Editor during Example Design generation. The section 4.8.2 may be referred
to, for more details.

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5.9 Testing the Example Design in Hardware

5.9.1 Hardware Setup

The following hardware boards are supported for the sample Example Design. For each hardware board,
we provide a predefined pin assignment. The Example Design recommendations require that System
console must be used for controlling the hardware platform and providing User Interface.

Arria 10 TBD Development Board (###) is used for hardware testing.

The following diagram illustrates the board setup for hardware test.

5.9.2 Timing Closure

Example Design component’s timing constraints will be automatically loaded during Quartus
compilation. Example Design level timing constraints can be found at <Example
Design>/altera_eth_top.sdc. The section 4.9.2 may be referred to, for more details.

To Do (Done): To include some notes from FB#303505: Example Design constraints that users would
have to include in own system setup.

5.9.3 SignalTap Signaling

Refer to the section 4.9.3

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To Do (Done): Provide useful debugging signals if users would want to include SignalTap in Hardware
bring-up and debugging. Please note that SignalTap instantiation will impact timing closure and users
would need to ensure timing closure with SignalTap prior to hardware bring-up.

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6 Functional Description: 10G Base-R Register Mode Example Design

This Example Design demonstrates Low Latency 10G Ethernet IP solution for Arria 10 using Low Latency
10G Ethernet MAC and Native PHY IP cores with small form factor pluggable plus (SFP+). It is capable to
achieve low roundtrip latency, 136.677ns (time taken to transmit the first data from Avalon-ST TX
interface to be available at Avalon-ST RX interface) in the simulation. Besides, it supports packet
monitoring system on transmit and receive paths and report Ethernet MAC statistics counter for
transmit and receive data paths.

6.1 Software and Hardware Requirement

Altera uses the following software and hardware to test the Example Design and testbench in Linux
platform.

 Quartus Prime.
 System Console. The user guide can be found at link:
http://www.altera.com/literature/ug/ug_system_console.pdf
 Simulators: Modelsim-AE, Modelsim-SE, NCsim or VCS (for complete simulators revision please refer
to link-TBD).
 Hardware: Arria 10 FPGA Development Kit (device: 10AX115S4F45I3SGE2).
 Clock control

6.2 Feature

The Example Design offers the following features:

• Support single channel 10 Gigabits per second (Gbps) with Arria 10 Native PHY.
• Capable to achieve low roundtrip latency 136.677ns proven in simulation.
• Provide packet monitoring system on transmit and receive paths and report Ethernet MAC statistics
counter for transmit and receive data paths.
• Support testing using different types of Ethernet packet transfer.

The top level diagram of the ED is as shown below.

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The figures 4.2 is modified as follows to arrive at the above figure.

 Keep only one channel removing ‘address_decoder_multi_channel’.
 Replace the name ‘altera_eth_multi_channel’ with the top name ‘altera_eth_top’ and the
related connections.
 Remove MDIO and the related connections.
 The fpll is removed as it is meant for 1G operation.

To Do (Done): Provide a top level diagram of the Example Design.

Example Design Components

Component Description
Low Latency Ethernet 10G MAC Ethernet MAC IP core
Native PHY Native PHY IP with 10G BASE-R register mode
preset applied (change TX FIFO MODE to Fast
Register in addition)
Address Decoder Address decoder module for each components

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Reset Controller Reset module which handle reset sequence for

the native PHY
Arria 10 ATX PLL Generates a TX serial clock for Arria 10 10G
transceiver
Adapter Convert 32-bit Avalon ST interface to 64-bit and
vice versa
FIFO Avalon Streaming (Avalon ST) single clock & dual
clock FIFO that buffers the receive & transmit
data between the MAC and client

6.3 Clocking
The following diagram in the section 6.4 captures the clocks and their frequencies in the example
design.

6.4 Reset

The following diagram shows the clocking and reset scheme for the Example Design. At the top-level of
the design, there are two external clock sources, ref_clk_clk (322.265625MHz) and csr_clk (100MHz) and
one master reset, master_reset_n. The master reset is asynchronous and active low reset signal. This
reset signal is then synced to different clock domain internally. When the master_reset_n is asserted, it
brings down all modules in the Example Design.

6.5 Parameter Setting

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6.5.1 Example Design Parameters

Parameter 10GBase-R Register Mode

IP Parameters
Speed 10G
Datapath options Tx & Rx
Enable ECC on memory blocks uncheck
Enable preamble pass-through mode uncheck
Enable priority-based flow control (PFC) uncheck
Number of PFC queues Don’t care
Enable unidirectional feature uncheck
Enable 10GBASE-R register mode checked
Enable supplementary address User input
Enable statistics collection checked
Statistics counters User input
Enable time stamping uncheck
Enable PTP one-step clock support Don’t care
Timestamp fingerprint width Don’t care
Time Of Day Format Don’t care
Use legacy XGMII interface uncheck
Use legacy Avalon Memory-Mapped interface checked
Use legacy Avalon Streaming interface uncheck
Example Design Parameters
Specific Number of Channels 1

6.5.2 PHY Pre-Set Parameters

The Example Design is using Arria 10 Native PHY with a pre-set PHY parameter setting that matches the
pairing with LL10GE-MAC IP.

Phy Parameter 10GBase-R Register Mode

Expanded name Abbreviated name
base_device NIGHTFURY5ES2
TX channel bonding mode bonded_mode not_bonded
Number of CDR reference cdr_refclk_cnt 1
clocks
Selected CDR reference cdr_refclk_select 0
clock
Number of data channels channels 1
design_environment NATIVE
device 10AX115S4F45I3SGE2
device_family Arria 10
Tranceiver mode duplex_mode duplex
enable_hard_reset 0
enable_hip 0
enable_parallel_loopbac 0
k
Enable enable_port_krfec_rx_en 0

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krfec_rx_enh_frame port h_frame

Enable enable_port_krfec_rx_en 0
krfec_rx_enh_frame_diag h_frame_diag_status
_status port
Enable enable_port_krfec_tx_en 0
krfec_tx_enh_frame port h_frame
Enable pipe_rx_polarity enable_port_pipe_rx_pol 0
port arity
Enable rx_enh_bitslip enable_port_rx_enh_bits 0
port lip
Enable rx_enh_blk_lock enable_port_rx_enh_blk_ 1
port lock
Enable enable_port_rx_enh_clr_ 0
rx_enh_clr_errblk_count errblk_count
port
Enable enable_port_rx_enh_crc3 0
port_rx_enh_crc32_err 2_err
port
Enable enable_port_rx_enh_data 1
rx_enh_data_valid port _valid
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_align_clr _align_clr
port (Interlaken)
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_align_val _align_val
port (Interlaken)
Enable rx_enh_fifo_cnt enable_port_rx_enh_fifo 0
port _cnt
Enable rx_enh_fifo_del enable_port_rx_enh_fifo 0
port(10GBASE-R) _del
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_empty port _empty
Enable rx_enh_fifo_full enable_port_rx_enh_fifo 0
port _full
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_insert _insert
port(10GBASE-R)
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_pempty port _pempty
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_pfull port _pfull
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_rd_en port _rd_en
Enable rx_enh_frame enable_port_rx_enh_fram 0
port e
Enable enable_port_rx_enh_fram 0
rx_enh_frame_diag_statu e_diag_status
s port
Enable enable_port_rx_enh_fram 0
rx_enh_frame_lock port e_lock
Enable rx_enh_highber enable_port_rx_enh_high 1
port ber

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Enable enable_port_rx_enh_high 0
rx_enh_highber_clr_cnt ber_clr_cnt
port
Enable enable_port_rx_is_locke 1
rx_is_lockedtodata port dtodata
Enable enable_port_rx_is_locke 1
rx_is_lockedtoref port dtoref
Enable rx_pma_clkout enable_port_rx_pma_clko 0
port ut
Enable rx_pma_clkslip enable_port_rx_pma_clks 0
port lip
Enable enable_port_rx_pma_div_ 1
rx_pma_div_clkout port clkout
Enable enable_port_rx_pma_iqtx 0
rx_pma_iqtxrx_clkout rx_clkout
port
Enable enable_port_rx_pma_qpen 0
rx_pma_qpenable_port_rx able_port_rx_polinv
_polinv port
Enable rx_pma_qpipulldn enable_port_rx_pma_qpip 0
port (QPI) ulldn
lpbken 0
Enable rx_seriallpbken port enable_port_rx_seriallp 0
bken_tx
Enable rx_signaldetect enable_port_rx_signalde 0
port tect
Enable enable_port_rx_std_bitr 0
rx_std_bitrev_ena port ev_ena
Enable rx_std_bitslip enable_port_rx_std_bits 0
port lip
Enable enable_port_rx_std_bits 0
rx_std_bitslipboundarys lipboundarysel
el port
Enable enable_port_rx_std_byte 0
rx_std_byterev_ena port rev_ena
Enable rx_std_pcfifo_empty port enable_port_rx_std_pcfi 0
fo_empty
Enable rx_std_pcfifo_full port enable_port_rx_std_pcfi 0
fo_full
Enable enable_port_rx_std_rmfi 0
rx_std_rmfifo_empty fo_empty
port
Enable enable_port_rx_std_rmfi 0
rx_std_rmfifo_full port fo_full
Enable enable_port_rx_std_sign 0
rx_std_signaldetect aldetect
port
Enable enable_port_rx_std_wa_a 0
rx_std_wa_a1a2size port 1a2size
Enable enable_port_rx_std_wa_p 0
rx_std_wa_patternalign atternalign
port

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Enable tx_enh_bitslip enable_port_tx_enh_bits 0

port lip
Enable tx_enh_fifo_cnt enable_port_tx_enh_fifo 0
port _cnt
Enable enable_port_tx_enh_fifo 0
tx_enh_fifo_empty port _empty
Enable tx_enh_fifo_full enable_port_tx_enh_fifo 0
port _full
Enable enable_port_tx_enh_fifo 0
tx_enh_fifo_pempty port _pempty
Enable enable_port_tx_enh_fifo 0
tx_enh_fifo_pfull port _pfull
Enable tx_enh_frame enable_port_tx_enh_fram 0
port e
Enable enable_port_tx_enh_fram 0
tx_enh_frame_burst_en e_burst_en
port
Enable enable_port_tx_enh_fram 0
tx_enh_frame_diag_statu e_diag_status
s port
Enable tx_pma_clkout port enable_port_tx_pma_clko 0
ut
Enable tx_pma_div_clkout port enable_port_tx_pma_div_ 1
clkout
Enable tx_pma_elecidle port enable_port_tx_pma_elec 0
idle
Enable enable_port_tx_pma_iqtx 0
tx_pma_iqtxrx_clkout rx_clkout
port
Enable tx_pma_qpipulldn port enable_port_tx_pma_qpip 0
(QPI) ulldn
Enable tx_pma_qpipullup port enable_port_tx_pma_qpip 0
(QPI) ullup
Enable tx_pma_rxfound port (QPI) enable_port_tx_pma_rxfo 0
und
Enable tx_pma_txdetectrx port enable_port_tx_pma_txde 0
(QPI) tectrx
Enable tx_polinv port enable_port_tx_polinv 0
Enable enable_port_tx_std_bits 0
tx_std_bitslipboundarys lipboundarysel
el port
Enable tx_std_pcfifo_empty port enable_port_tx_std_pcfi 0
fo_empty
Enable tx_std_pcfifo_full port enable_port_tx_std_pcfi 0
fo_full
Enable enable_ports_adaptation 0
enable_ports_pipe_g3_an 0
alog
enable_ports_pipe_hclk 0
enable_ports_pipe_rx_el 0
ecidle

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enable_ports_pipe_sw 0
Enable enable_ports_rx_manual_ 0
rx_set_locktodata and cdr_mode
rx_set_locktoref ports
enable_ports_rx_manual_ 0
ppm
Enable PRBS verifier enable_ports_rx_prbs 0
control and status
ports
enable_rx_pma_floatingt 0
ap
Enable simplified data enable_simple_interface 1
interface
enable_split_interface 0
enable_transparent_pcs 0
Enable ‘Enhanced PCS’ enh_low_latency_enable 0
low latency mode
Enhanced PCS/PMA enh_pcs_pma_width 32
interface width
FPGA fabric/ Enhanced enh_pld_pcs_width 66
PCS interface width
Enable Rx 64b/66b enh_rx_64b66b_enable 1
decoder
Enable Rx data bitslip enh_rx_bitslip_enable 0
Enable Rx block enh_rx_blksync_enable 1
synchronizer
Enable Interlaken RX enh_rx_crcchk_enable 0
CRC-32 checker
Enable Rx descrambler enh_rx_descram_enable 1
(10Gbase-R/Interlaken)
Enable Interlaken Rx enh_rx_dispchk_enable 0
disparity checker
Enable Interlaken frame enh_rx_frmsync_enable 0
synchronizer
Frame Synchronizer meta enh_rx_frmsync_mfrm_len 2048
frame length gth
Enable Rx KR-FEC error enh_rx_krfec_err_mark_e 0
marking nable
Error marking type enh_rx_krfec_err_mark_t 10G
ype
Enable Rx data polarity enh_rx_polinv_enable 0
inversion
Enable RX FIFO enh_rxfifo_align_del 0
alignment word deletion
(Interlaken)
Enable RX FIFO control enh_rxfifo_control_del 0
word deletion
(Interlaken)
Rx FIFO mode enh_rxfifo_mode Register
Rx FIFO partially empty enh_rxfifo_pempty 2
threshold
Rx FIFO partially full enh_rxfifo_pfull 23

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threshold
Enable Rx/Tx FIFO enh_rxtxfifo_double_wid 0
double width mode th
Enable Tx 64b/66b enh_tx_64b66b_enable 1
encoder
Enable Tx data bitslip enh_tx_bitslip_enable 0
Enable Interlaken Tx enh_tx_crcerr_enable 0
CRC-32 generator error
insertion
Enable Interlaken Tx enh_tx_crcgen_enable 0
CRC-32 generator
Enable Interlaken Tx enh_tx_dispgen_enable 0
disparity generator
Enable frame generator enh_tx_frmgen_burst_ena 0
burst control ble
Enable Interlaken frame enh_tx_frmgen_enable 0
generator
Frame generator meta enh_tx_frmgen_mfrm_leng 2048
frame length th
Enable KR-FEC Tx error enh_tx_krfec_burst_err_ 0
insertion enable
KR-FEC Tx error enh_tx_krfec_burst_err_ 1
insertion spacing len
Enable Tx data polarity enh_tx_polinv_enable 0
inversion
Enable Interlaken Tx enh_tx_randomdispbit_en 0
Random disparity bit able
Enable Tx-scrambler enh_tx_scram_enable 1
(10Gbase-R, Interlaken)
Tx-scrambler enh_tx_scram_seed 288230376151711743
seed(10Gbase-R,
Interlaken)
Enable Tx Sync header enh_tx_sh_err 0
error insertion
Tx FIFO mode enh_txfifo_mode Fast register
Tx FIFO partially empty enh_txfifo_pempty 2
threshold
Tx FIFO partially full enh_txfifo_pfull 11
threshold
generate_add_hdl_instan 0
ce_example
Generate parameter generate_docs 1
documentation file
Message level for rule message_level error
violations
number_physical_bonding 1
_clocks
pcie_rate_match Bypass
Actual PCS Tx Channel pcs_bonding_master 0
bonding master
pcs_direct_width 8
Initial Tx PLL clock pll_select 0

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input selection
Number of Tx PLL clock plls 1
inputs per channel
PMA configuration rules pma_mode basic
Tranceiver protocol_mode teng_1588_mode
configuration rules
rapid_validate 0
Enable dynamic rcfg_enable 1
reconfiguration
Configuration file rcfg_file_prefix
prefix
Generate C header file rcfg_h_file_enable 0
Enable datapath and rcfg_iface_enable 0
interface
reconfiguration
Enable Altera Debug rcfg_jtag_enable 0
master endpoint
Generate MIF (Memory rcfg_mif_file_enable 0
Initialization File)
Enable multiple rcfg_multi_enable 0
reconfiguration files
Number of rcfg_profile_cnt 2
reconfiguration
profiles
Reconfiguration Profile rcfg_profile_data0
0
Reconfiguration Profile rcfg_profile_data1
1
Reconfiguration Profile rcfg_profile_data2
2
Reconfiguration Profile rcfg_profile_data3
3
Reconfiguration Profile rcfg_profile_data4
4
Reconfiguration Profile rcfg_profile_data5
5
Reconfiguration Profile rcfg_profile_data6
6
Reconfiguration Profile rcfg_profile_data7
7
Selected rcfg_profile_select 1
reconfiguration profile
Generate reduced rcfg_reduced_files_enab 0
reconfiguration files le
Share reconfiguration rcfg_shared 0
interface
Generate SystemVerilog rcfg_sv_file_enable 0
package file
CTLE adaptation mode rx_pma_ctle_adaptation_ manual
mode
DFE adaptation mode rx_pma_dfe_adaptation_m disabled
ode

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Number of fixed dfe rx_pma_dfe_fixed_taps 3

taps
Rx_pma_div_clkout rx_pma_div_clkout_divid 2
division factor er
PPM detector threshold rx_ppm_detect_threshold 1000
Enable capability set_capability_reg_enab 0
registers le
Selected CDR reference set_cdr_refclk_freq 322.265625
clock frequency
Enable control and set_csr_soft_logic_enab 0
status registers le
Data rate set_data_rate 10312.5
set_embedded_debug_enab 0
le
set_enable_calibration 0
Enable ODI acceleration set_odi_soft_logic_enab 0
logic le
set_hip_cal_en 0
PCS Tx channel bonding set_pcs_bonding_master Auto
master
Enable PRBS soft set_prbs_soft_logic_ena 0
accumulators ble
Enable embedded Set_rcfg_emb_strm_enabl
reconfiguration e
streamer
Set user-defined IP set_user_identifier 0
identifier
std_low_latency_bypass_ 0
enable
Standard PCS / PMA interface std_pcs_pma_width 10
width
Enable RX 8B/10B decoder std_rx_8b10b_enable 0
std_rx_bitrev_enable 0
RX byte deserializer mode std_rx_byte_deser_mode Disabled
std_rx_byterev_enable 0
RX FIFO mode std_rx_pcfifo_mode low_latency
std_rx_polinv_enable 0
RX rate match FIFO mode std_rx_rmfifo_mode disabled
RX rate match insert / delete -ve std_rx_rmfifo_pattern_n 0
pattern (hex)
RX rate match insert / delete +ve std_rx_rmfifo_pattern_p 0
pattern (hex)
std_rx_word_aligner_fas 0
t_sync_status_enable
RX word aligner mode std_rx_word_aligner_mod bitslip
e
RX word aligner pattern (hex) std_rx_word_aligner_pat 0
tern
RX word aligner pattern length std_rx_word_aligner_pat 7
tern_len
std_rx_word_aligner_ren 3

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umber
std_rx_word_aligner_rgn 3
umber
std_rx_word_aligner_rkn 3
umber
std_rx_word_aligner_rvn 0
umber
Enable TX 8B/10B disparity control std_tx_8b10b_disp_ctrl_ 0
enable
Enable TX 8B/10B encoder std_tx_8b10b_enable 0
std_tx_bitrev_enable 0
std_tx_bitslip_enable 0
TX byte serializer mode std_tx_byte_ser_mode Disabled mode
std_tx_byterev_enable 0
TX FIFO mode std_tx_pcfifo_mode low_latency
std_tx_polinv_enable 0
support_mode user_mode
TX local clock division factor tx_pma_clk_div 1
tx_pma_div_clkout division factor tx_pma_div_clkout_divid 2
er
validation_rule_select

To Do(Done): List down all preset PHY parameter values for users reference.

6.6 Interface Signaling

Signal Direction Width Description

csr_clk input 1 Configuration clock for Avalon-MM
interface. Frequency is 100Mhz
csr_rst_n input 1 Reset Avalon-MM interface
tx_xcvr_clk output 1 Clock for the Tx path. Frequency is
322.265625MHz
tx_serial_data Output 1 Serial data transmitted out
tx_rst_n input 1 Reset Tx interface
rx_xcvr_clk output 1 Clock for the Rx path. Frequency is
322.265625MHz
rx_serial_data Input 1 Serial data received.
rx_rst_n input 1 Reset Rx interface
rx_xcvr_half_clk output 1 Synchronous clock derived from
rx_xcvr_clk. Frequency is 161.133Mhz
tx_xcvr_half_clk output 1 Synchronous clock derived from
tx_xcvr_clk. Frequency is 161.133Mhz
ref_clk_clk input 1 Referejce clock for Tx PLL. Frequency is
322.265625MHz
csr_write input 1 Assert this signal to request a write
csr_read input 1 Assert this signal to request a read
csr_address input 16 Use this bus to specify the register
address you want to read from or write

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to
csr_writedata input 32 Carries the data to be written to the
specified register
csr_readdata output 32 Carries the data read from the specified
register
csr_waitrequest output 1 Asserted when IP core is busy and not
ready to accept any read or write request
tx_ready_export output 1 Asserted when the native PHY Tx path is
ready to transmit data
rx_ready_export output 1 Asserted when the native PHY Rx path
reset is complete
block_lock output 1 Asserted to indicate that the block
synchronizer has established
synchronization
atx_pll_locked output 1 Asserted when Tx PLL is locked

6.7 Register Mapping

All register space for this example design is 32 bit. The following tables show the address offset for the
Example Design and client logic at the top-level of the design.

Example Design Block Register Map

Byte Offset Block
0x0000_d000 – 0xFFFF_FFFF Client Logic
0x0000_0000 – 0x0000_CFFF Reserved for Altera

Example Design Sub Block Register Map

Byte Offset Block
0x0000_0000 MAC
0x0000_8000 Native PHY
0x0000_9600 Tx SC FIFO
0x0000_9400 Rx SC FIFO
0x0000_c000 Packet Generator & Checker

6.8 Simulating the Example Design

6.8.1 Simulation Collateral

The following table describes files that implement the Example Design testbench. The collateral can be
found under <Example Design>/simulation/ed_sim/models.

File Description
avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that uses the BFMs to form the
transmit and receive path, and access the Avalon-MM

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interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to the
DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
tb.sv The top level testbench file of which consists of the Device
Under Test (DUT) and other logic blocks.

6.8.2 Simulation Test Cases

The test cases are included to demonstrate how to change MAC & PHY configuration at 10Gbps
throughput. The test cases are meant for single channel usage of the example design.

Testbench is included in the design example package for simulation verification. Below are the steps to
run the simulation:
1. Download and restore the design example: LL_Ethernet_10G_A10_phy_10GBaser_Register_mode.
2. Launch Modelsim-SE 10.3c and change the directory to
LL_Ethernet_10G_A10_phy_10GBaser_Register_mode\testbench.
3. In the TCL console window, type the below command: tb_run.tcl

4. At the end of the simulation, Modelsim simulator will generate statistics of transmitted packets and
received packets in the Transcript window. While in the Wave window, the roundtrip latency for serial
loopback is indicated by the measurement cursors that show the time taken to transmit the first data
from Avalon-ST TX interface to be available at Avalon-ST RX interface.

To Do (Done): Details to be added.

6.9 Testing the Example Design in Hardware

6.9.1 Hardware Setup

The following hardware boards are supported for the sample Example Design. For each hardware board,
we provide a predefined pin assignment. The Example Design recommendations require that System
console must be used for controlling the hardware platform and providing User Interface.

Arria 10 TBD Development Board (10AX115S4F45I3SGE2) is used for hardware testing.

The following procedure illustrates the board setup for hardware test. (Diagram: To Do)

The design example package comes with pre-generated RTL files that implement a single Ethernet
channel uses the on-board small form factor pluggable plus (SFP+). Below are the steps to perform

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hardware test:
1. Download and restore the design example: (refer to the project link above).
2. Launch the Quartus II software and then open the project file, “altera_eth_top.qpf”.
3. Run full compilation for the design example. A “.sof” file will be generated once the compilation is
complete.
4. Configure the FPGA on Arria 10 GX SI Development Board using the generated, “altera_eth_top.sof”
file.
5. After configuration is done, open the Clock Control tool, “ClockControl.exe”. The Clock Control tool is
shipped with the “Installation Kit” for Arria 10 GX SI Development Board.
6. Set the new frequency for Y5 and Y6 as following: Y5= 322.265625 MHz; Y6= 100MHz

7. Press User Push Button S1 to reset the system.

Note: System must be hard reset after configuration done.
8. On Quartus II Tools menu, click on System Debugging Tools and then launch System
Console.
9. In the System Console command shell, change the directory to
“LL_Ethernet_10G_A10_phy_10GBaser_Register_mode/script”.
10. Perform the following test by running the command in the System Console command shell:

a. SFP+ loopback
Command:
i. source gen_conf.tcl (Generate and send 0xffff2000 packets)
ii. source monitor_conf.tcl (To check the number of good and bad packets received)
iii. source show_stats.tcl (To show the statistics counter values)
b. Avalon-ST loopback
Command: source loopback_conf.tcl (enable Avalon-ST loopback)

6.9.2 Timing Closure

Example Design component’s timing constraints will be automatically loaded during Quartus
compilation. Example Design level timing constraints can be found at <Example
Design>/altera_eth_top.sdc.

6.9.3 SignalTap Signaling

The following table captures the SignalTap signals for the ED comprising Base-R phy.

Co Module Name Signal

mp
one
nt

Exa altera_eth_top csr_clk

mpl
e ref_clk_clk
Des

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ign master_res
Top et_n
Lev
block_lock_
el
n

tx_ready_e
xport_n

rx_ready_e
xport_n

altera_eth_top.altera_eth_10g_mac_base_r_low_latency atx_pll_loc
ked

iopll_locke
d

MA altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_b avalon_st_r
C ase_r_low_latency_wrap.low_latency_mac x_data

avalon_st_r
x_empty

avalon_st_r
x_endofpac
ket

avalon_st_r
x_error

avalon_st_r
x_startofpa
cket

avalon_st_r
x_ready

avalon_st_r
x_valid

avalon_st_t
x_data

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avalon_st_t
x_empty

avalon_st_t
x_endofpac
ket

avalon_st_t
x_error

avalon_st_t
x_ready

avalon_st_t
x_startofpa
cket

avalon_st_t
x_valid

MA altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_b rs2top_eth
C ase_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_e _xgmii_vali
Tx m10g32_tx_top.alt_em10g32_tx_rs_layer.alt_em10g32_tx_rs_xgmii_layer_ultra d (xgmii tx
valid),
temp_rs2to
p_eth_xgm
ii_data
(xgmii tx
data),
temp_rs2to
p_eth_xgm
ii_ctrl
(xgmii tx
control)

Note: The
signals in
the
brackets
indicate
the actual
XGMII
interface
signals

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tapped.

MA altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_b rx_top2rs_
C ase_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_e xgmii_rx_v
Rx m10g32_rx_top.alt_em10g32_rx_rs_layer.alt_em10g32_rx_rs_xgmii_ultra alid (xgmii
rx valid),
rx_top2rs_
xgmii_rx_d
ata (xgmii
rx data),
rx_top2rs_
xgmii_rx_ct
rl (xgmii rx
control),
rx_link_faul
t_status_xg
mii_rx_dat
a (xgmii rx
link fault
status)

Note: The
signals in
the
brackets
indicate
the actual
XGMII
interface
signals
tapped.

PH altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_b tx_analogr
Y ase_r_low_latency_wrap. low_latency_baser eset

tx_digitalre
set

rx_analogr
eset

rx_digitalre
set

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tx_cal_busy

rx_cal_busy

rx_is_locke
dtodata

tx_clkout

rx_clkout

To Do (Done): Provide useful debugging signals if users would want to include SignalTap in Hardware
bring-up and debugging. Please note that SignalTap instantiation will impact timing closure and users
would need to ensure timing closure with SignalTap prior to hardware bring-up.

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7 Functional Description: 1G/2.5GbE MAC + PHY example design

This document describes the 1G/2.5GbE MAC + PHY reference design for Arria V, and Arria 10, the
testbench, and its components.

7.1 Software and Hardware Requirements

Altera uses the following hardware and software to test the 1G/2.5GbE MAC + PHY reference design and
testbench:

■ Altera Complete Design Suite 15.1

■ Arria V GT FPGA Development Board (5AGTFD7K3F40I3)
■ Arria 10 GX SI Development Board (10AX115S4F45I3SG)
■ ModelSim-SE 10.3d
■ Quartus Prime Pro (Partial Reconfiguration Ready)

7.2 Features

This reference design contains pre-generated RTL files which support 2-channels. You can use the
testbench and simulation script (ModelSim) provided to simulate the design in a simulator. This
reference design also support partial reconfiguration ready option.

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7.2.1 High Level Block Diagram

Figure 7 .1 in shows the block diagram of the design example.

Figure 7.1: 1G/2.5G Ethernet reference design block diagram

7.3 Partial Reconfiguration Ready

When Partial Reconfiguration Ready option is enabled, the generated Design Example hierarchy will be
compliance to partial reconfiguration flow. There will be clear separation between hard IP and soft IP.
Hard IP such as Native PHY, JTAG, TXPLL, FPLL will be instantiated at the top wrapper. Certain soft IP
such as XCVR reset controller and TXPLL reset controller will also be instantiated at the same level of
wrapper as their function is tighly coupled with the hard IP and not protocol based IP. There will be a
wrapper called alt_eth_pr which will contain all soft IP logic, which customer can put it in their PR
region. There is no functionality change after this option is enabled. The following diagram shows the
hierarchy difference before and after this option is enabled.

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Figure X: Example Design hierarchy before Partial Reconfiguration Ready option is enabled.

Figure X: Example Design hierarchy after Partial Reconfiguration Ready option is enabled.

7.4 Clocking Scheme

The following diagram shows the clocking scheme of the reference design.

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Figure 7.2: Clocking scheme of the reference design

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7.5 Reset Scheme

Figure 7.3 Reset scheme of reference design

There is an active high asynchronous global reset signal at reference design top level (alt_mge_rd).
Internal reset signals will be synchronized to respective clock domain internally, and generated by
Transceiver Reset Controller as shown in Figure 7 .3.

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7.6 Generation Flow with parameter setting

7.6.1 Using the design example

The design example package comes with pre-generated RTL files for 2 channels. To use the reference
design, perform the following steps:
…

1. Unzip the package at the project directory.

2. Change directory to alt_mge_rd.
3. Launch the Quartus II software and open the project file alt_mge_top.qpf
4. Click Start Compilation on the Processing menu to compile the design example.

7.6.2 Changing the number of channels

In order to change the number of channels, modify the “NUM_OF_CHANNEL” parameter of

alt_mge_top for Quartus II compilation flow (or alt_mge_rd for simulation flow).

For Arria V reference design, user needs to regenerate the Transceiver Reconfiguration Controller file
(acds_ip/alt_mge_xcvr_rcfg.qsys) in the reference design package. Refer to section 7.6.3 on how to
regenerate the IP files.

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7.6.3 Regenerate IP files when upgrade to new version of ACDS

The following table shows the IP that need regeneration and the tools involved.

IP Tools IP File Location

1G/2.5GbE MAC Qsys acds_ip/alt_mge_mac.qsys
1G/2.5GbE PHY Qsys acds_ip/alt_mge_1g_2p5g_phy.qsys
Transceiver Reconfiguration Qsys acds_ip/alt_mge_xcvr_rcfg.qsys (Arria V)
Controller
Transceiver Reset Controller for Qsys acds_ip/alt_mge_xcvr_reset_ctrl_channel.qsys
Channel
Transceiver Reset Controller for Qsys acds_ip/alt_mge_xcvr_reset_ctrl_txpll.qsys
TX PLL
Transceiver TX PLL for 2.5 GbE Qsys acds_ip/alt_mge_xcvr_cmu_pll_2p5g.qsys (Arria V)
acds_ip/alt_mge_xcvr_atx_pll_2p5g.qsys (Arria 10)
Transceiver TX PLL for 1 GbE Qsys acds_ip/alt_mge_xcvr_cmu_pll_1g.qsys (Arria V)
acds_ip/alt_mge_xcvr_fpll_1g.qsys (Arria 10)
PLL for MAC and User Logic Qsys acds_ip/alt_mge_core_pll.qsys
Avalon-MM JTAG Master Qsys acds_ip/alt_jtag_csr_master.qsys
Address Decoder Qsys addr_decoder/alt_mge_rd_addrdec_mch.qsys

Launch the tool and open the IP file as shown in the above table to regenerate the IP.

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7.7 Interface Signals

This section describes the interface signals at design example level, which is alt_mge_rd.

N: This is the number of channels parameter (NUM_OF_CHANNEL) set by user.

Some of the signals bus width is determined by NUM_OF_CHANNEL parameter.

7.7.1 Clock and Reset Signals

Signal Direction Width Description

csr_clk Input 1 Configuration clock for Avalon-MM
interface. The clock runs at 125MHz.
mac_clk Input 1 Clock for the MAC and Avalon-ST
interfaces. Its frequency is 156.25 MHz, and
must have 0 ppm frequency difference with
refclk.
refclk Input 1 Reference clock for the TX PLLs. Its
frequency is 125 MHz.
rx_pma_clkout Output 1 Recovered clock from CDR
reset Input 1 To reset the whole reference design.
Asynchronous and active high signal.
tx_digitalreset Output [N] Asynchronous active high reset signal for
TX data path of user logic.
rx_digitalreset Output [N] Asynchronous active high reset signal for
RX data path of user logic.

7.7.2 Avalon-MM Interface Signals

7.7.2.1 Ethernet MAC

Signal Direction Width Description

csr_mac_write Input [N] Assert this signal to request a write.
csr_mac_read Input [N] Assert this signal to request a read.
csr_mac_address Input [N][10] Use this bus to specify the register address
you want to read from or write to.
csr_mac_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_mac_readdata Output [N][32] Carries the data read from the specified
register.
csr_mac_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

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7.7.2.2 Ethernet PHY

Signal Direction Width Description

csr_phy_write Input [N] Assert this signal to request a write.
csr_phy_read Input [N] Assert this signal to request a read.
csr_phy_address Input [N][5] Use this bus to specify the register address
you want to read from or write to.
csr_phy_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_phy_readdata Output [N][32] Carries the data read from the specified
register.
csr_phy_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

7.7.2.3 1G/2.5G Ethernet Reconfiguration

Signal Direction Width Description

csr_rcfg_write Input 1 Assert this signal to request a write.
csr_rcfg_read Input 1 Assert this signal to request a read.
csr_rcfg_address Input 2 Use this bus to specify the register address
you want to read from or write to.
csr_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_rcfg_readdata Output 32 Carries the data read from the specified
register.

7.7.2.4 Direct Native PHY Reconfiguration (Arria 10 only)

Signal Direction Width Description

csr_native _phy_rcfg_write Input 1 Assert this signal to request a write.
csr_native _phy_rcfg_read Input 1 Assert this signal to request a read.
csr_native _phy_rcfg_address Input 10 Use this bus to specify the register address
you want to read from or write to.
csr_native _phy_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_native _phy_rcfg_readdata Output 32 Carries the data read from the specified
register.
csr_native _phy_rcfg_waitrequest Output 1 When asserted, this signal indicates that
the Native PHY is busy and not ready to
accept any read or write requests.

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7.7.3 Avalon-ST Interface Signals

Signal Direction Width Description

avalon_st_tx_startofpacket Input [N]
avalon_st_tx_endofpacket Input [N]
avalon_st_tx_valid Input [N]
avalon_st_tx_ready Output [N]
avalon_st_tx_data Input [N][32]
avalon_st_tx_empty Input [N][2]
avalon_st_tx_error Input [N]
avalon_st_rx_startofpacket Output [N]
avalon_st_rx_endofpacket Output [N] Refer to Low Latency Ethernet
avalon_st_rx_valid Output [N] 10G MAC User Guide, in section
avalon_st_rx_ready Input [N] 5-5 and 5-9, under “Avalon-ST
avalon_st_rx_data Output [N][32] Data Interfaces” and “Avalon-ST
avalon_st_rx_empty Output [N][2] Status Interfaces”
avalon_st_rx_error Output [N][6]
avalon_st_tx_status_valid Output [N]
avalon_st_tx_status_data Output [N][40]
avalon_st_tx_status_error Output [N][7]
avalon_st_rx_status_valid Output [N]
avalon_st_rx_status_data Output [N][40]
avalon_st_rx_status_error Output [N][7]
avalon_st_pause_data Input [N][2]

7.7.4 PHY Interface Signals

Signal Direction Width Description

rx_serial_data Input [N]
tx_serial_data Output [N] Refer to 1G/2.5G Ethernet PHY User
led_link Output [N] Guide, in section 3, under “1G/2.5G
led_char_err Output [N] Ethernet PHY Interface Signals”
led_disp_err Output [N]
led_an Output [N]
channel_tx_ready Output [N] This signal is asserted when the channel TX
data path is ready for data transmission.
channel_rx_ready Output [N] This signal is asserted when the channel RX
data path is ready for data transmission.

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7.8 Register Map

An address decoder module is provided in the reference design which is instantiated in simulation
testbench and hardware testing Quartus II project for demonstration purpose.

Table 1 .1 shows the address offsets in the 1G/2.5G Ethernet Reference Design.

Block/
Sub-block Address Offset Comments

1G/2.5G Ethernet 0x00_0000

Reconfiguration

Channel-0 0x01_0000

1G/2.5GbE MAC 0x0000

1G/2.5GbE PHY 0x8000

Native PHY Rcfg 0xA000 Available in Arria 10 only

Channel-1 0x02_0000

1G/2.5GbE MAC 0x0000

1G/2.5GbE PHY 0x8000

Native PHY Rcfg 0xA000 Available in Arria 10 only

Traffic Controller 0x10_0000

Table 1.1: Address Offset of Reference Design

7.8.1 1G/2.5G Ethernet Reconfiguration Controller

Table 1 .2, Table 1 .3, Table 1 .4 shows the register offset and bit offset of 1G/2.5G Ethernet
Reconfiguration Controller.

Word Offset Register Name Access Reset Value Descriptions

0x00 logical_channel_number RW 0x000 [9:0] Logical
number of the
reconfig
controller block

Write has no
effect when

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reconfig is busy.
0x01 control RW Refer to table Control
below reconfiguration
process
0x02 status RO Refer to table Indicates status
below of
reconfiguration
process
0x03 Reserved - - -
Table 1.2: Register Offset of 1G/2.5G Ethernet Reconfiguration Controller

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Bit Register Name Access Reset Value Descriptions

[1:0] speed_select RW 0x00 Select the
operating speed
of the
transceiver to be
reconfigured to.

2’b00: 1GbE
2’b01: 2.5GbE
2’b10: Reserved
2’b11: Reserved

Write has no
effect when
reconfig is busy.
[15:2] Reserved - 0x0000 -
16 reconfig_start RWC 0x0 When its value is
0, write 1 to start
reconfiguration
process.

Self-cleared
when
reconfiguration
is completed.

Write has no
effect when
reconfig is busy.
[31:17] Reserved - 0x000000 -
Table 1.3: Bit Offset of Control Register

Bit Register Name Access Reset Value Descriptions

0 reconfig_busy RO 0x0 Indicates
reconfiguration
is in progress
and busy.
Table 1.4: Bit Offset of Status Register

7.8.2 1G/2.5G Ethernet MAC

For register map and detail explanation of the register usage, refer to Low Latency Ethernet 10G MAC
User Guide, in section 4, under “Configuration Registers”.

7.8.3 PHY

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For register map and detail explanation of the register usage, refer to 1G/2.5G Ethernet PHY User
Guide, in section 4, under “1G/2.5G Ethernet PHY Configuration Registers”.

7.9 Simulating the example design Testbench

Altera provides testbench for you to demonstrate the behavior of 1G/2.5G Ethernet Reference Design.
The following sections describe the testbench, its components, and use.

7.9.1 Simulation Collateral

7.9.1.1 Testbench Block Diagram

The testbench operates in loopback mode. Figure 1 .4 shows the flow of the packets in the design
example.

Figure 1.4: Testbench Block Diagram

7.9.1.2 Testbench Components

The testbench comprise the following modules:

 Device under test (DUT)—the design example.

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 Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit
and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-
MM interfaces of the design example components.
 Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the
simulator console.

7.9.1.3 Testbench Files

The <project directory>/alt_mge_rd/testbench/ directory contains the testbench files.

Table 1 .5 describes the files that implement the reference design testbench.

File Name Description

avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
gen_sim_script.sh A script to generate simulation scripts required for simulators.
Execute this script if IP cores are regenerated.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top.sv The top-level testbench file. This file includes the reference
design (alt_mge_rd), which is the device under test (DUT), a
client packet generator, and a client packet monitor along
with other logic blocks.
mentor/tb_run.tcl A Tcl script that starts a simulation session in the ModelSim
simulation software.
mentor/wave.do A signal tracing macro script for use with the ModelSim
simulation software to display testbench signals.
Table 1.5: Testbench Files

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7.9.1.4 Simulating Design Example Testbench

Simulation script uses QUARTUS_ROOTDIR environment variable to access Altera’s simulation model
libraries. QUARTUS_ROOTDIR should has been set and pointed to the Quartus II installation path after
proper installation. You need to set it manually if this environment variable is missing.

7.9.1.4.1 Using ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

1. Change directory to <project directory>/testbench/mentor/

2. Launch ModelSim, run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model with the
provided testbench:
 do tb_run.tcl

7.9.2 Test Cases

Test cases are included to show case how to change channel speed to 1G/2.5G and MAC configuration.

7.9.2.1 Reconfigure PHY Speed

By default, the 1G/2.5G PHY is operating in 2.5GbE mode. In order to switch the transceiver operating
speed from 2.5GbE to 1GbE or vice versa, user need to perform following steps to instruct 1G/2.5G
Ethernet Reconfiguration Controller to reconfigure the PHY.

1. Read from status register to ensure reconfig_busy bit is 0.

2. Write to logical_channel_number register to select the channel to be reconfigured.
3. Write the selected operating speed to speed_select and 1 to reconfig_start bit of control
register.
4. The reconfig_busy bit of status register will be read as 1 during reconfiguration process.
5. Then reconfiguration process is completed when the reconfig_busy bit is read as 0.
6. Transceiver reset sequence will be triggered automatically when the reconfiguration is
completed.

7.9.2.2 MIF File

For Arria V device family, MIF file is not required for transceiver reconfiguration to switch operating
speed. The data required for the reconfiguration is embedded in the RTL of alt_mge_rcfg_28nm
module.

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User should follow the read-modify-write reconfiguration data and sequence in their reconfiguration
logic.

For Arria 10 device family, MIF files for transceiver reconfiguration will be generated by 1G/2.5G PHY
according to

Error: Reference source not found.

Operating MIF Files

Mode
1GbE acds_ip/alt_mge_1g_2p5g_phy/altera_xcvr_native_a10_150/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG0.mif
2.5GbE acds_ip/alt_mge_1g_2p5g_phy/altera_xcvr_native_a10_150/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG1.mif

Table 1.6: Transceiver Reconfiguration MIF Files for Arria 10

7.9.2.3 Testcase 1

Configuration:

1. 2 channels
2. Circular loopback (as shown in diagram in Figure 1 .4)

Test Scenario:

1. Design start up with channel configured to 2.5G Ethernet mode.

2. Do basic MAC configuration and PHY speed configuration for all 2 channels.
3. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.
4. Send 3 different type of packets:
a. 64-byte packet
b. 1518-byte packet
c. 100-byte packet
5. Repeat step 2 to 4 for 1G Ethernet mode.

After the simulation stop, user can refer to the transcript window for channel 0 MAC TX and RX Statistic
counter result.

For each operating speed, if all the total 3 packets have been received successfully to channel 0 Avalon-
ST RX interface, the transcript will print out “Simulation PASSED”.

7.10 Testing the ED in hardware

7.10.1 Hardware setup

7.10.1.1 Hardware Testing: Multi Gigabit Ethernet (MGE) 1G/2.5G/5G

Hardware testing will be carryout in reference design level with the following
environment setting in both Arria V and Arria 10 family. The following equipment/tools
are needed to carry out hardware testing:

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o FPGA Dev. Kit:

 Arria V GT FPGA Dev Kit for Arria V testing
 Arria 10 Si Dev Kit for Arria 10 testing
o Cables:
 SMA cable
 SFP+
 Fiber Optic cable
o 3rd Party Tester:
 Spirent Test Center and LSI mission board for 2.5G/5G testing
 SmartBit for 1G testing

7.10.1.2 DUT Implementation with LSI Mission Board

The DUT is represented by LSI Mission board together with a development board shown
in Figure with 2.5G system image programmed into a development board. The framework
is illustrated in Figure . The board is a universal development board, but none of the other
components is used. The test flow is stimulus will be pumped into the DUT by the Spirent
Testcenter and later will return back to the testcenter.

Avalon-MM
Control Interface

DUT 2.5G SYSTEM

Pipeline Bridge

Spirent Testcenter LSI 2.5-Gbps 2.5-Gbps

Avalon-ST Dual-Clock FIFOs
Mission Board Ethernet PHY Ethernet MAC

Figure x: DUT Implementation with LSI Mission Board

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Figure x: DUT Implementation with LSI Mission Board

7.10.1.3 Hardware Testing: Dynamic Speed Switching Test

Speed Switching between 1G to 2.5 G and vice-versa.[ACDS 15.0]

1st test: Permute between all 3 operations speeds (1G, 2.5G and 5G) [ACDS 15.1]

Note:

 Limitation of hardware equipment to carry out dynamic switching on the same channel as
1G to be connect to SmartBit using SFP+ and 2.5G to be connect to LSI Mission Board
using SMA.
 Currently no external tester can be used for 5G testing.
 LSI mission board have limitation to received packet (max throughput, B2B with fixed 12b
IPG) directly from 10G spirent tester.
 Spirent tester port load need to set 25% or below for this testing to have 75% time on idle
character and data on 25%.
 Include clock frequency checking module to ensure tx_clkout and rx_clkcout is working
as per specification after speed switching. Alternatively is using oscilloscope.

2nd test: Use 2 dev. kit boards:

o 1st board used as generator and checker

o 2nd board as DUT

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7.10.1.4 Hardware Testing: Reception and Transmission of Data Frame (Stress Test)
This hardware test covers stressing the SUT operations specific to reception and
transmission of valid data frames under normal room temperature condition.

Program the Spirent tester to send large volume of traffic (min 1 hr to max 2 days) with
minimum IPG (notes that for the minimum supported IPG by Spirent tester is 12B), and
set the clock frequency difference between Tester and board with a ±100ppm, and then
verify there is NO packet lost and NO error. As CRC of frames generated by Spirent
tester will be removed at Rx and inserted again at Tx during transmission, the Tx CRC
generation is therefore checked by frames received by Spirent tester.

Meanwhile, for Rx CRC error checking, program the Spirent tester to send large volume
of CRC error with minimum IPG, and then verify the Rx CRC statistic counter is
matching with the # of CRC frames generated by the Spirent tester.

This stress test shall include following coverage:

- Speed: 1G, 2.5G (Spirent Tester port load need to set 25% or below) and 5G.
Randomize length from 64B-10000B to run overnight

7.10.2 Timing closure

7.10.3 SingalTap signaling

8 Functional description: 1G/2.5GbE MAC + PHY with IEEE 1588v2

(Note: Update for Stratix 10 are highlighted in yellow.)

This document describes the 1G/2.5GbE MAC + PHY with IEEE 1588v2 reference design for Arria
10/Stratix 10, the testbench, and its components.

8.1 Software and Hardware Requirements

Altera uses the following hardware and software to test the 1G/2.5GbE MAC + PHY with IEEE 1588v2
reference design and testbench:

■ Altera Complete Design Suite 15.1 Build 179

■ Arria 10 GX SI Development Board
■ ModelSim-SE 10.4d
■ Quartus Prime Pro (Partial Reconfiguration Ready)

For Stratix 10:

■ Intel Quartus Prime Pro Edition 17.0 Build 210

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■ Stratix 10 SI Development Board (device: 1SG280LU3F50E2VGS1)

■ ModelSim-SE 10.4d

8.2 Features

This reference design contains pre-generated RTL files which support 2-channels. You can use the
testbench and simulation script (ModelSim) provided to simulate the design in a simulator. This
reference design also support partial reconfiguration ready option.

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8.2.1 High Level Block Diagram

Figure 7 .1 in shows the block diagram of the design example.

alt_mge_rd

.
. .
alt_mge_rd_addrdec_mch alt_mge_channel

alt_mge_channel PTP
Packet Avalon-ST
Classifier
Pulse-
per-
1G/2.5G
Second
Pulse Per
Second
S LL MAC
S Local TOD
TOD Sync
.
..
…

TX/RX Serial
Avalon- Avalon-
S A10
S MM M PHY Data
MM Master
...

XCVR
S Reset
S AVMM Mux Controller
S XCVR
Reconfig

S Master
A10 TOD
A10 IO
ATX
FPLL PLL
XCVR PLL
S
Reconfig Pulse-
Master Pulse
per-
Second
Per Second

Reset Input Clock

Figure 8.5: 1G/2.5G IEEE 1588 Ethernet reference design block diagram

Gold blocks : Generated using Qsys from acds_ip folder.

Green blocks : Generated using Qsys from addr_decoder folder.

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altera_eth_top

alt_mge_rd

.
. .
alt_mge_rd_addrdec_mch alt_mge_channel

alt_mge_channel PTP
Packet Avalon-ST
Classifier
Pulse-
per-
1G/2.5G
Second
Pulse Per
Second
S LL MAC
S Local TOD
TOD Sync
.
..
…

TX/RX Serial
Avalon- Avalon-
S S10
S MM M PHY Data
MM Master
...

XCVR
S Reset
S AVMM Mux Controller
S XCVR
Reconfig

S Master
S10 TOD
S10 IO
ATX
FPLL PLL
XCVR PLL
S
Reconfig Pulse-
Master Pulse
per-
Second
Per Second

S10
FPLL

Reset Reference Clock

CSR Clock

Figure 8.2: S10 1G/2.5G IEEE 1588 Ethernet reference design block diagram

Generated with IP Catalog

Generated with Qsys

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8.3 Partial Reconfiguration Ready

When Partial Reconfiguration Ready option is enabled, the generated Design Example hierarchy will be
compliance to partial reconfiguration flow. There will be clear separation between hard IP and soft IP.
Hard IP such as Native PHY, JTAG, TXPLL, FPLL will be instantiated at the top wrapper. Certain soft IP
such as XCVR reset controller and TXPLL reset controller will also be instantiated at the same level of
wrapper as their function is tighly coupled with the hard IP and not protocol based IP. There will be a
wrapper called alt_eth_pr which will contain all soft IP logic, which customer can put it in their PR
region. There is no functionality change after this option is enabled. The following diagram shows the
hierarchy difference before and after this option is enabled.

Figure X: Example Design hierarchy before Partial Reconfiguration Ready option is enabled.

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Figure X: Example Design hierarchy after Partial Reconfiguration Ready option is enabled.

8.4 Clocking Scheme

The following diagram shows the clocking scheme of the reference design.

Figure 4.1: Clocking scheme of the reference design

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Figure 4.2: Clocking scheme of the reference design (for S10)

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8.5 Reset Scheme

Figure 8.6: Reset scheme of reference design

Figure 8.3: Reset scheme of reference design (for S10)

There is an active high asynchronous global reset signal at reference design top level ( alt_mge_rd).
Internal reset signals will be synchronized to respective clock domain internally, and generated by
Transceiver Reset Controller as shown in Figure 7 .3.

8.6 Generation Flow with parameter setting

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8.6.1 Using the design example

The design example package comes with pre-generated RTL files for 2 channels. To use the reference
design, perform the following steps:

1. Unzip the package at the project directory.

tar -zxvf Error! Unknown document property name..tar.gz
2. Change directory to alt_mge_rd.
3. Launch the Quartus II software and open the project file alt_mge_top.qpf
4. Click Start Compilation on the Processing menu to compile the design example.

For Stratix 10:

1. Launch the Quartus II software, and launch Low Latency Ethernet 10G MAC from IP Catalog.
This will launch in Qsys Pro.
2. Go to Example Design tab, select the preset 1G/2.5G Ethernet with 1588 Example Design from
the Presets windows, and click Apply.
3. Click Generate Example Design…. Once finished, exit Qsys Pro without saving.
4. Open the project file altera_eth_top.qpf from directory
alt_em10g32_0_EXAMPLE_DESIGN/LL10G_1G_2_5G_1588v2/.
5. Click Start Compilation on the Processing menu to compile the design example.

8.6.2 Changing the number of channels

In order to change the number of channels, modify the “NUM_OF_CHANNEL” parameter of

alt_mge_top for Quartus II compilation flow (or alt_mge_rd for simulation flow).

8.6.3 Regenerate IP files when upgrade to new version of ACDS

The following table shows the IP that need regeneration and the tools involved.

IP Tools IP File Location

1G/2.5GbE MAC Qsys acds_ip/alt_mge_mac.qsys
1G/2.5GbE PHY Qsys acds_ip/alt_mge_1g_2p5g_phy.qsys
Transceiver Reset Controller for Qsys acds_ip/alt_mge_xcvr_reset_ctrl_channel.qsys
Channel
Transceiver Reset Controller for Qsys acds_ip/alt_mge_xcvr_reset_ctrl_txpll.qsys
TX PLL
Transceiver TX PLL for 2.5 GbE Qsys acds_ip/alt_mge_xcvr_atx_pll_2p5g.qsys

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Transceiver TX PLL for 1 GbE Qsys acds_ip/alt_mge_xcvr_fpll_1g.qsys

PLL for MAC and User Logic Qsys acds_ip/alt_mge_core_pll.qsys
PLL for 1588 latency sampling Qsys acds_ip/alt_mge_1588_sampling_pll.qsys
Time of Day Master Qsys acds_ip/alt_mge_1588_tod_master.qsys
Time of Day for 2.5 GbE Qsys acds_ip/alt_mge_1588_tod_2p5g.qsys
Time of Day for 1 GbE Qsys acds_ip/alt_mge_1588_tod_1g.qsys
Time of Day Sync 64b for 2.5 GbE Qsys acds_ip/alt_mge_1588_tod_sync_64b_2p5g.qsys
Time of Day Sync 96b for 2.5 GbE Qsys acds_ip/alt_mge_1588_tod_sync_96b_2p5g.qsys
Time of Day Sync 64b for 1 GbE Qsys acds_ip/alt_mge_1588_tod_sync_64b_1g.qsys
Time of Day Sync 96b for 1 GbE Qsys acds_ip/alt_mge_1588_tod_sync_96b_1g.qsys
Packet Classifier Qsys acds_ip/alt_mge_core_pll.qsys
Avalon-MM JTAG Master Qsys acds_ip/alt_jtag_csr_master.qsys
Address Decoder Qsys addr_decoder/alt_mge_rd_addrdec_mch.qsys
Avalon-MM Mux for XCVR Qsys addr_decoder/alt_mge_rd_avmm_mux_xcvr_rcfg.qsys
Reconfig

S10 IP Tools IP File Location

Low Latency Ethernet 10G MAC IP Catalog rtl/mac/alt_mge_mac.ip
1G/2.5G/5G/10G Multi-rate IP Catalog rtl/phy/alt_mge_1g_2p5g_phy.ip
Ethernet PHY
Stratix 10 Transceiver PHY Reset IP Catalog rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel.ip
Controller
Stratix 10 L-Tile Transceiver ATX IP Catalog rtl/pll_atxpll/alt_mge_xcvr_atx_pll_2p5g.ip
PLL
Stratix 10 L-Tile fPLL IP Catalog rtl/pll_fpll/alt_mge_xcvr_fpll_1g.ip
Stratix 10 L-Tile fPLL IP Catalog rtl/pll_fpll/alt_mge_core_pll.qsys
Altera IOPLL IP Catalog rtl/pll_mpll/alt_mge_1588_sampling_pll.ip
Stratix 10 Clock Control IP Catalog rtl/pll_mpll/alt_mge_1588_latency_sclk_clkctrl.ip
Ethernet IEEE 1588 Time of Day IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_master.ip
Clock
Ethernet IEEE 1588 Time of Day IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_2p5g.ip
Clock
Ethernet IEEE 1588 Time of Day IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_1g.ip
Clock
Ethernet IEEE 1588 TOD IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_sync_64b_2p5g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_sync_96b_2p5g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_sync_64b_1g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/altera_eth_1588_tod/alt_mge_1588_tod_sync_96b_1g.ip
Synchronizer
Ethernet Packet Classifier IP Catalog rtl/altera_eth_packet_classifier/alt_mge_packet_classifier.ip
JTAG to Avalon Master Bridge IP Catalog rtl/jtag_avalon_master/alt_jtag_csr_master.ip
Address Decoder Qsys rtl/address_decoder/alt_mge_rd_addrdec_mch.qsys
Avalon-MM Mux for XCVR Qsys rtl/address_decoder/alt_mge_rd_avmm_mux_xcvr_rcfg.qsys
Reconfig

Launch the tool and open the IP file as shown in the above table to regenerate the IP.

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8.7 Interface Signals

This section describes the interface signals at design example level, which is alt_mge_rd.

N: This is the number of channels parameter (NUM_OF_CHANNEL) set by user.

Some of the signals bus width is determined by NUM_OF_CHANNEL parameter.

8.7.1 Clock and Reset Signals

Signal Direction Width Description

csr_clk Input 1 Configuration clock for Avalon-MM
interface. The clock runs at 125MHz. In S10,
it also provides clock for core logics.
mac_clk Input 1 Clock for the MAC and Avalon-ST
interfaces. Its frequency is 156.25 MHz, and
must have 0 ppm frequency difference with
refclk.
refclk Input 1 Reference clock for the TX PLLs. Its
frequency is 125 MHz.
rx_pma_clkout Output 1 Recovered clock from CDR
reset Input 1 To reset the whole reference design.
Asynchronous and active high signal.
tx_digitalreset Output [N] Asynchronous active high reset signal for
TX data path of user logic.
rx_digitalreset Output [N] Asynchronous active high reset signal for
RX data path of user logic.
rx_digitalreset_stat (Stratix 10 only) Output [N] Status signal for rx_digitalreset from PHY.

8.7.2 Avalon-MM Interface Signals

8.7.2.1 Ethernet MAC

Signal Direction Width Description

csr_mac_write Input [N] Assert this signal to request a write.
csr_mac_read Input [N] Assert this signal to request a read.
csr_mac_address Input [N][10] Use this bus to specify the register address
you want to read from or write to.
csr_mac_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_mac_readdata Output [N][32] Carries the data read from the specified
register.
csr_mac_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

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8.7.2.2 Ethernet PHY

Signal Direction Width Description

csr_phy_write Input [N] Assert this signal to request a write.
csr_phy_read Input [N] Assert this signal to request a read.
csr_phy_address Input [N][5] Use this bus to specify the register address
you want to read from or write to.
csr_phy_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_phy_readdata Output [N][32] Carries the data read from the specified
register.
csr_phy_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

8.7.2.3 1G/2.5G Ethernet Reconfiguration

Signal Direction Width Description

csr_rcfg_write Input 1 Assert this signal to request a write.
csr_rcfg_read Input 1 Assert this signal to request a read.
csr_rcfg_address Input 2 Use this bus to specify the register address
you want to read from or write to.
csr_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_rcfg_readdata Output 32 Carries the data read from the specified
register.

8.7.2.4 Direct Native PHY Reconfiguration (Arria 10/Stratix 10 only)

Signal Direction Width Description

csr_native _phy_rcfg_write Input 1 Assert this signal to request a write.
csr_native _phy_rcfg_read Input 1 Assert this signal to request a read.
csr_native _phy_rcfg_address Input 10 Use this bus to specify the register address
you want to read from or write to.
csr_native _phy_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_native _phy_rcfg_readdata Output 32 Carries the data read from the specified
register.
csr_native _phy_rcfg_waitrequest Output 1 When asserted, this signal indicates that
the Native PHY is busy and not ready to
accept any read or write requests.

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8.7.2.5 Time of Day Master

Signal Direction Width Description

csr_master_tod_write Input [N] Assert this signal to request a write.
csr_master_tod_read Input [N] Assert this signal to request a read.
csr_master_tod_address Input [N][4] Use this bus to specify the register address
you want to read from or write to.
csr_master_tod_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_master_tod_readdata Output [N][32] Carries the data read from the specified
register.
csr_master_tod_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

8.7.3 Avalon-ST Interface Signals

Signal Direction Width Description

avalon_st_tx_startofpacket Input [N]
avalon_st_tx_endofpacket Input [N]
avalon_st_tx_valid Input [N]
avalon_st_tx_ready Output [N]
avalon_st_tx_data Input [N][32]
avalon_st_tx_empty Input [N][2]
avalon_st_tx_error Input [N]
avalon_st_rx_startofpacket Output [N]
avalon_st_rx_endofpacket Output [N] Refer to Low Latency Ethernet
avalon_st_rx_valid Output [N] 10G MAC User Guide, in section
avalon_st_rx_ready Input [N] 5-5 and 5-9, under “Avalon-ST
avalon_st_rx_data Output [N][32] Data Interfaces” and “Avalon-ST
avalon_st_rx_empty Output [N][2] Status Interfaces”
avalon_st_rx_error Output [N][6]
avalon_st_tx_status_valid Output [N]
avalon_st_tx_status_data Output [N][40]
avalon_st_tx_status_error Output [N][7]
avalon_st_rx_status_valid Output [N]
avalon_st_rx_status_data Output [N][40]
avalon_st_rx_status_error Output [N][7]
avalon_st_pause_data Input [N][2]

8.7.4 IEEE 1588v2 Timestamp Interface Signals

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Signal Direction Width Description

tx_egress_timestamp_96b_valid Output [N]
tx_egress_timestamp_96b_data Output [N][96]
tx_egress_timestamp_96b_fingerprint Output [N][TSTAMP_FP_WIDTH]
tx_egress_timestamp_64b_valid Output [N] Refer to Low Latency Ethernet
tx_egress_timestamp_64b_data Output [N][64] 10G MAC User Guide, in section 5-
tx_egress_timestamp_64b_fingerprint Output [N][TSTAMP_FP_WIDTH] 18, under “IEEE 1588v2
rx_ingress_timestamp_96b_valid Output [N] Interfaces”
rx_ingress_timestamp_96b_data Output [N][96]
rx_ingress_timestamp_64b_valid Output [N]
rx_ingress_timestamp_64b_data Output [N][64]

8.7.5 Packet Classifier Interface Signals

Signal Direction Width Description

tx_egress_timestamp_request_in_valid Input [N] Assert this signal when timestamp is
required for the particular frame. This
signal must be aligned to the start of an
incoming packet.
tx_egress_timestamp_request_in_fingerprint Input [N][TSTAMP_FP_WIDTH] A width-configurable fingerprint that
correlates timestamps for incoming
packets.
clock_operation_mode_mode Input [N][2] Determines the clock mode.
00: Ordinary clock
01: Boundary clock
10: End to end transparent clock
11: Peer to peer transparent clock
pkt_with_crc_mode Input [N] Indicates whether or not a packet
contains CRC.
1: Packet contains CRC
0: Packet does not contain CRC
tx_ingress_timestamp_valid Input [N] Indicates the update for residence time.
1: Allows update for residence time based
on decoded results.
0: Prevents update for residence time.
When this signal is deasserted,
tx_etstamp_ins_ctrl_out_residence_ti
me_update also gets deasserted.
tx_ingress_timestamp_96b_data Input [N][96] 96-bit format of ingress timestamp that
holds data so that the output can align
with the start of an incoming packet.
tx_ingress_timestamp_64b_data Input [N][64] 64-bit format of ingress timestamp that
holds data so that the output can align
with the start of an incoming packet.
tx_ingress_timestamp_format Input [N] Format of the timestamp to be used for
calculating residence time. This signal
must be aligned to the start of an
incoming packet. A value of 0 indicates 96
bit timestamp format while 1 indicates 64
bit timestamp format.

8.7.6 PHY Interface Signals

Signal Direction Width Description

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rx_serial_data Input [N]

tx_serial_data Output [N]
led_link Output [N]
Refer to 10G Multi-rate Ethernet PHY
led_char_err Output [N] – Lineside User Guide
led_disp_err Output [N]
led_an Output [N]
channel_tx_ready Output [N] This signal is asserted when the channel
TX data path is ready for data
transmission.
channel_rx_ready Output [N] This signal is asserted when the channel
RX data path is ready for data
transmission.

8.7.7 TOD Interface Signals

Signal Direction Width Description

master_pulse_per_second Output 1 Pulse per second output from Master PPS
module. The pulse per second output will
be asserted for 10ms.
start_tod_sync Input [N] Start TOD synchronization process. As long
as this signal is asserted high, the
synchronization process will continue and
Time of Day from master TOD will be
repeatedly synchronized to local TOD.
pps Output [N] Pulse per second output from 1G or 2.5G
PPS module (depending on current speed
configuration) in channel-n. The pulse per
second output will be asserted for 10ms.

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8.8 Register Map

An address decoder module is provided in the reference design which is instantiated in simulation
testbench and hardware testing Quartus II project for demonstration purpose.

Table 1 .1 shows the address offsets in the 1G/2.5G Ethernet Reference Design.

Block/ Address
Sub-block Offset Comments
1G/2.5G Ethernet 0x00_0000
Reconfiguration
TOD Master 0x00_4000
Channel-0 0x01_0000
1G/2.5GbE MAC 0x0000
1G/2.5GbE PHY 0x8000
Native PHY Rcfg 0xA000 Available in Arria 10/Stratix
10 only
Channel-1 0x02_0000
1G/2.5GbE MAC 0x0000
1G/2.5GbE PHY 0x8000
Native PHY Rcfg 0xA000 Available in Arria 10/Stratix
10 only
Traffic Controller 0x10_0000
Table 2.7: Address Offset of Reference Design

8.8.1 1G/2.5G Ethernet Reconfiguration Controller

Table 1 .2, Table 1 .3, Table 1 .4 shows the register offset and bit offset of 1G/2.5G Ethernet
Reconfiguration Controller.

Word Offset Register Name Access Reset Value Descriptions

0x00 logical_channel_number RW 0x000 [9:0] Logical
number of the
reconfig
controller block

Write has no
effect when
reconfig is busy.
0x01 control RW Refer to table Control
below reconfiguration
process
0x02 status RO Refer to table Indicates status
below of
reconfiguration
process
0x03 Reserved - - -
Table 2.8: Register Offset of 1G/2.5G Ethernet Reconfiguration Controller

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Bit Register Name Access Reset Value Descriptions

[1:0] speed_select RW 0x00 Select the
operating speed
of the
transceiver to be
reconfigured to.

2’b00: 1GbE
2’b01: 2.5GbE
2’b10: Reserved
2’b11: Reserved

Write has no
effect when
reconfig is busy.
[15:2] Reserved - 0x0000 -
16 reconfig_start RWC 0x0 When its value is
0, write 1 to start
reconfiguration
process.

Self-cleared
when
reconfiguration
is completed.

Write has no
effect when
reconfig is busy.
[31:17] Reserved - 0x000000 -
Table 2.9: Bit Offset of Control Register

Bit Register Name Access Reset Value Descriptions

0 reconfig_busy RO 0x0 Indicates
reconfiguration
is in progress
and busy.
Table 2.10: Bit Offset of Status Register

8.8.2 TOD Master

For register map and detail explanation of the register usage, refer to 10-Gbps Ethernet MAC MegaCore
Function User Guide, in section B.6, under “ToD Clock Configuration Register Space.

8.8.3 1G/2.5G Ethernet MAC

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For register map and detail explanation of the register usage, refer to Low Latency Ethernet 10G MAC
User Guide, in section 4, under “Configuration Registers”.

8.8.4 PHY

For register map and detail explanation of the register usage, refer to 1G/2.5G/5G/10G Multi-rate
Ethernet PHY – Lineside User Guide.

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8.9 Simulating the example design

8.9.1 Simulation Collateral

Altera provides testbench for you to demonstrate the behavior of 1G/2.5G Ethernet Reference Design.
The following sections describe the testbench, its components, and use.

8.9.1.1 Testbench Block Diagram

The testbench operates in loopback mode. Figure 1 .4 shows the flow of the packets in the design
example.

Figure 2.7: Testbench Block Diagram

8.9.1.2 Testbench Components

The testbench comprise the following modules:

 Device under test (DUT)—the design example.
 Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit
and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-
MM interfaces of the design example components.
 Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the
simulator console.

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8.9.1.3 Testbench Files

The <project directory>/alt_mge_rd/testbench/ directory contains the testbench files.

Table 1 .5 describes the files that implement the reference design testbench.

File Name Description

avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
ptp_timestamp.sv A SystemVerilog HDL class that defines the timestamp in the
testbench.
gen_sim_script.sh A script to generate simulation scripts required for simulators.
Execute this script if IP cores are regenerated.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top.sv The top-level testbench file. This file includes the reference
design (alt_mge_rd), which is the device under test (DUT), a
client packet generator, and a client packet monitor along
with other logic blocks.
mentor/tb_run.tcl A Tcl script that starts a simulation session in the ModelSim
simulation software.
mentor/wave.do A signal tracing macro script for use with the ModelSim
simulation software to display testbench signals.
Table 2.11: Testbench Files

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8.9.1.4 Simulating Design Example Testbench

Simulation script uses QUARTUS_ROOTDIR environment variable to access Altera’s simulation model
libraries. QUARTUS_ROOTDIR should has been set and pointed to the Quartus II installation path after
proper installation. You need to set it manually if this environment variable is missing.

8.9.1.4.1 Using ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

1. Change directory to <project directory>/testbench/mentor/

2. Launch ModelSim, run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model with the
provided testbench:
 do tb_run.tcl

For Stratix 10:

1. Change directory to <project directory>/simulation/ed_sim/mentor/
2. Launch ModelSim, run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model with the
provided testbench:
 do tb_run.tcl

8.9.2 Test Cases

Test cases are included to show case how to change channel speed to 1G/2.5G and MAC configuration.

8.9.2.1 Reconfigure PHY Speed

By default, the 1G/2.5G PHY is operating in 2.5GbE mode. In order to switch the transceiver operating
speed from 2.5GbE to 1GbE or vice versa, user need to perform following steps to instruct 1G/2.5G
Ethernet Reconfiguration Controller to reconfigure the PHY.

7. Read from status register to ensure reconfig_busy bit is 0.

8. Write to logical_channel_number register to select the channel to be reconfigured.
9. Write the selected operating speed to speed_select and 1 to reconfig_start bit of control
register.
10. The reconfig_busy bit of status register will be read as 1 during reconfiguration process.
11. Then reconfiguration process is completed when the reconfig_busy bit is read as 0.
12. Transceiver reset sequence will be triggered automatically when the reconfiguration is
completed.

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8.9.2.2 MIF File

For Arria V device family, MIF file is not required for transceiver reconfiguration to switch operating
speed. The data required for the reconfiguration is embedded in the RTL of alt_mge_rcfg_28nm
module.

User should follow the read-modify-write reconfiguration data and sequence in their reconfiguration
logic.

For Arria 10 device family, MIF files for transceiver reconfiguration will be generated by 1G/2.5G PHY
according to Table 8.1.

Operating MIF Files

Mode
1GbE acds_ip/alt_mge_1g_2p5g_phy/altera_xcvr_native_a10_151/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG0.mif
2.5GbE acds_ip/alt_mge_1g_2p5g_phy/altera_xcvr_native_a10_151/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG1.mif
Table 8.1: Transceiver Reconfiguration MIF Files for Arria 10

For Stratix 10 device family, MIF files for transceiver reconfiguration will be generated by 1G/2.5G PHY
according to Table 8.2.

Operating Mode MIF Files

1GbE rtl/reconfig/alt_mge_rcfg_xcvr_1g.mif
2.5GbE rtl/reconfig/alt_mge_rcfg_xcvr_2p5g.mif
Table 8.2: Transceiver Reconfiguration MIF Files for Stratix 10

8.9.2.3 Testcase 1

Configuration:

3. 2 channels
4. Circular loopback (as shown in diagram in Figure 1 .4)

Test Scenario:

6. Design start up with channel configured to 2.5G Ethernet mode.

7. Do basic MAC configuration and PHY speed configuration for all 2 channels.
8. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.
9. Send 7 different types of packets:
a. Non-PTP
b. No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
c. VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
d. Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
e. No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
f. VLAN, PTP over UDP/IPv4, PTP Delay Request Message, 2-step PTP
g. Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP

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10. Repeat step 2 to 4 for 1G Ethernet mode.

After the simulation stop, user can refer to the transcript window for channel 0 MAC TX and RX Statistic
counter result.

For each operating speed, if all the total 7 packets have been received successfully to channel 0 Avalon-
ST RX interface, the transcript will print out “Simulation PASSED”.

8.10 Testing the ED in hardware

Refer to the section 7.9 for the details.

8.11 Known Issues

IP: 10G Multi-rate Ethernet PHY - Lineside

Release: ACDS 15.1
Device Family: Arria 10
Variant: All (2.5G, 1G/2.5G, 1G/2.5G/10G)

Issue:

 User might observe hold time violation in "10G Multi-rate Ethernet PHY  - Lineside" IP in the
data transfer from alt_mge16_phy_xcvr_term module to Transceiver Native PHY on TX data
path.

Workaround:

 User need to over-constraint the hold time failing path by adding following timing constraints
into user SDC file.
 if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } {
    set_min_delay -from [get_registers *alt_mge16_phy_xcvr_term:*|*] -to [get_registers
*twentynm_xcvr_native:*|twentynm_pcs_*] 0.3ns
}
 Note: This constraint has been included in the top level SDC (alt_mge_top.sdc) of this
reference design.

Resolution:

 The issue will be fixed in future release.

 The issue has been fixed in Stratix 10.

9 Functional Description: 1G/2.5/5/10GbE (USXGMII) MAC + PHY

Example Design

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This document describes the 1G/2.5/5/10GbE (USXGMII) MAC + PHY reference design for Arria
10/Stratix 10, the testbench, and its components.

9.1 Software and Hardware Requirements

Altera uses the following hardware and software to test the 1G/2.5/5/10GbE (USXGMII) MAC + PHY
reference design and testbench:

For Arria 10:

 Software
o Altera Complete Design Suite 16.0
 Simulators
o ModelSim-AE
o ModelSim-SE
o NCSim
o VCS
 Hardware
o Arria 10 GX SI Development Board (10AX115S4F45I3SG)

For Stratix 10:

 Software
o Intel Quartus Prime Pro Edition 17.1 Build 143
 Simulators
o ModelSim-AE
o ModelSim-SE
o NCSim
o VCS
 Hardware
o Stratix 10 GX SI Development Board (1SG280LU3F50E3VGS1)

9.2 Features

The Example Design offers the following features:

• Support multi speed operation of 1 Gigabits per second (Gbps) to 10 Gigabits per second (Gbps) with
1G/2.5G/5G/10G Multi-rate Ethernet PHY.
• Support 2 channels Ethernet MAC and PHY.
• Provide packet monitoring system on transmit and receive data paths and report Ethernet MAC
statistics counters for transmit and receive datapath.
• Support testing using different types of Ethernet packet transfer without IEEE 1588v2 features.

Example Design Components

ED Component Descriptions
Low latency Ethernet 10G Ethernet MAC IP core

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MAC
1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core
Ethernet PHY
Address decoder channel Address decoder module for each component within the channel,
for example, MAC and PHY.
Address decoder multichannel Address decoder module for all channels and components within
multichannel level, for example Master TOD.
Address decoder top Address decoder module for top level components, for example
Traffic Controller.
Reset controller Reset modules which handle reset synchronization for all ED
components.
Core PLL Generates clocks for all the components in the Example Design.
Arria 10/Stratix 10 ATX PLL Generates a TX serial clock for Arria 10/Stratix 10 10G transceiver.

9.2.1 High Level Block Diagram

Figure 9 .8 shows the block diagram of the design example.

Figure 9.8: 1G/2.5G/5G/10G (USXGMII) Ethernet reference design block diagram

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9.3 Clocking Scheme

The following diagram shows the clocking scheme of the reference design.

Figure 9.9: Clocking scheme of the reference design

9.4 Reset Scheme

Figure 9.10 Reset scheme of the reference design (Arria 10)

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Figure 9.4 Reset scheme of the reference design (Stratix 10)

There is an active high asynchronous global reset signal at reference design top level
(alt_mge_multi_channel). Internal reset signals will be synchronized to respective clock domain
internally, and generated by Transceiver Reset Controller as shown in Figure 9 .10 and 9.4.

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9.5 Interface Signals

This section describes the interface signals at design example level, which is alt_mge_multi_channel.

N: This is the number of channels parameter (NUM_OF_CHANNEL) set by user.

Some of the signals bus width is determined by NUM_OF_CHANNEL parameter.

9.5.1 Clock and Reset Signals

Signal Direction Width Description

refclk_10g Input 1 Reference clock for the TX PLLs. Its
frequency is 644.53125 MHz.
csr_clk Input 1 Configuration clock for Avalon-MM
interface. The clock runs at 125MHz.
mac32b_clk Output 1 Clock for the MAC internal logic running at
32-bit interfaces. Its frequency is 312.5
MHz, and must have 0 ppm frequency
difference with refclk.
mac64b_clk Output 1 Clock for the MAC and Avalon-ST logic
running at 64-bit interfaces. Its frequency is
156.25 MHz, and must have 0 ppm
frequency difference with refclk.
rx_pma_clkout Output [N] Recovered clock from CDR
reset Input 1 To reset the whole reference design.
Asynchronous and active high signal.
tx_digitalreset Output [N] Asynchronous active high reset signal for
TX data path of user logic.
rx_digitalreset Output [N] Asynchronous active high reset signal for
RX data path of user logic.

9.5.2 Avalon-MM Interface Signals

Signal Direction Width Description

csr_mch_write Input [N] Assert this signal to request a write.
csr_mch_read Input [N] Assert this signal to request a read.
csr_mch_address Input [N][20] Use this bus to specify the register address
you want to read from or write to.
csr_mch_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_mch_readdata Output [N][32] Carries the data read from the specified
register.
csr_mch_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

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9.5.3 Avalon-ST Interface Signals

Signal Direction Width Description

avalon_st_tx_startofpacket Input [N]
avalon_st_tx_endofpacket Input [N]
avalon_st_tx_valid Input [N]
avalon_st_tx_ready Output [N]
avalon_st_tx_data Input [N][64]
avalon_st_tx_empty Input [N][3]
avalon_st_tx_error Input [N]
avalon_st_rx_startofpacket Output [N]
avalon_st_rx_endofpacket Output [N] Refer to Low Latency Ethernet
avalon_st_rx_valid Output [N] 10G MAC User Guide, in section
avalon_st_rx_ready Input [N] 5-5 and 5-9, under “Avalon-ST
avalon_st_rx_data Output [N][64] Data Interfaces” and “Avalon-ST
avalon_st_rx_empty Output [N][3] Status Interfaces”
avalon_st_rx_error Output [N][6]
avalon_st_tx_status_valid Output [N]
avalon_st_tx_status_data Output [N][40]
avalon_st_tx_status_error Output [N][7]
avalon_st_rx_status_valid Output [N]
avalon_st_rx_status_data Output [N][40]
avalon_st_rx_status_error Output [N][7]
avalon_st_pause_data Input [N][2]

9.5.4 PHY Interface Signals

Signal Direction Width Description

rx_serial_data Input [N]
tx_serial_data Output [N] Refer to 1G/2.5G/5G/10G Multi-rate
led_an Output [N] Ethernet PHY User Guide
rx_block_lock Output [N]

9.5.5 PHY Interface Signals

Signal Direction Width Description
channel_tx_ready Output [N] This signal is asserted when the channel TX
data path is ready for data transmission.
channel_rx_ready Output [N] This signal is asserted when the channel RX
data path is ready for data transmission.

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9.6 Register Map

The following table shows the address offset for the Example Design and client logic at the Example
Design level.
Byte Offset Block
0x00_0000 - 0x00_EFFF Client Logic
0x00_F000 - 0x00_FFFF Reserved for Altera
0x01_0000 Reserved for Altera
0x02_0000 Port 0
0x03_0000 Port 1
0x04_0000 Port 2
0x05_0000 Port 3
0x06_0000 Port 4
0x07_0000 Port 5
0x08_0000 Port 6
0x09_0000 Port 7
0x0A_0000 Port 8
0x0B_0000 Port 9
0x0C_0000 Port 10
0x0D_0000 Port 11
0x0E_0000 onwards Client Logic

The following table shows per-port address offset for Example Design and client logic.

Byte Offset Sub-Block

0x0000 – 0x3FFF Reserved for Altera
0x4000 1G/2.5G/5G/10G Multi-rate Ethernet PHY
0x8000 Low Latency 10GbE MAC

9.7 Simulating the example design Testbench

9.7.1 Simulation Collateral

9.7.1.1 Testbench Block Diagram

The testbench operates in loopback mode. Figure 3 .11 shows the flow of the packets in the design
example.

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Figure 3.11: Testbench Block Diagram

9.7.1.2 Testbench Components

The testbench comprise the following modules:

 Device under test (DUT)—the design example.
 Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit
and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-
MM interfaces of the design example components.
 Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the
simulator console.

9.7.1.3 Testbench Files

The following table describes files that implement the Example Design testbench. The collateral can be
found under <Example Design>/simulation/ed_sim/models.

File Name Description

avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.

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default_test_params_pkg.sv A SystemVerilog HDL package that contains the default

parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
gen_sim_script.sh A script to generate simulation scripts required for simulators.
Execute this script if IP cores are regenerated.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top.sv The top-level testbench file. This file includes the reference
design (alt_mge_rdmulti_channel), which is the device under
test (DUT), a
client packet generator, and a client packet monitor along
with other logic blocks.

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9.7.1.4 Simulating Design Example Testbench

Simulation script uses QUARTUS_ROOTDIR environment variable to access Altera’s simulation model
libraries. QUARTUS_ROOTDIR should has been set and pointed to the Quartus II installation path after
proper installation. You need to set it manually if this environment variable is missing.

9.7.1.4.1 Using ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

1. Change directory to <Example Design>/simulation/ed_sim/mentor

2. Launch ModelSim, run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model with the
provided testbench:
 do tb_run.tcl

9.7.2 Test Cases

Test cases are included to show case how to change channel speed to 1G/2.5G/5G/10G and MAC
configuration.

9.7.2.1 Testcase 1

Configuration:

1. 2 channels
2. Circular loopback (as shown in diagram in Figure 3 .11)

Test Scenario:

1. Design start up with channel configured to 10G Ethernet mode.

2. Do basic MAC configuration and PHY speed configuration for all 2 channels.
3. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.
4. Send 3 different type of packets:
a. 64-byte packet
b. 1518-byte packet
c. 100-byte packet
5. Repeat step 2 to 4 for 1G/2.5G/5G Ethernet mode.

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After the simulation stop, user can refer to the transcript window for channel 0 MAC TX and RX Statistic
counter result.

For each operating speed, if all the total 3 packets have been received successfully to channel 0 Avalon-
ST RX interface, the transcript will print out “Simulation PASSED”.

9.8 Testing the ED in hardware

9.8.1 Hardware setup

9.8.1.1 Hardware Testing: 1G/2.5G/5G/10G (USXGMII)

Hardware testing will be carryout in reference design level with the following
environment setting in Arria 10 family. The following equipment/tools are needed to carry
out hardware testing:
o FPGA Dev. Kit:
 Arria 10 Si Dev Kit for Arria 10 testing
o Cables:
 SMA cable
 SFP+
 Fiber Optic cable
o 3rd Party Tester:
 Spirent Test Center for 10G testing
 SmartBit for 1G testing
 TBD: NBASE-T tester

9.8.1.2 Hardware Testing: Dynamic Speed Switching Test

TBD

9.8.2 Timing closure

9.8.3 SingalTap signaling

10 Functional Description: 1G/2.5G/10GbE MAC + PHY example design

(Note: Update for Stratix 10 are highlighted in yellow.)

This document describes the 1G/2.5G/10GbE MAC + PHY reference design for Arria 10/Stratix 10,, the
testbench, and its components.

10.1 Software and Hardware Requirements

Altera uses the following hardware and software to test the 1G/2.5G/10GbE MAC + PHY reference
design and testbench:

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■ Altera Complete Design Suite 15.1

■ Arria 10 GX SI Development Board (10AX115S4F45I3SG)
■ ModelSim-SE 10.3d
■ Quartus Prime Pro (Partial Reconfiguration Ready)

For Stratix 10:

■ Intel Quartus Prime Pro Edition 17.0 Build 210
■ Stratix 10 SI Development Board (device: 1SG280LU3F50E3VGS1)
■ ModelSim-SE 10.4d

10.2 Features

This reference design contains pre-generated RTL files which support 2-channels. You can use the
testbench and simulation script provided to simulate the design in a simulator. This reference design
also support partial reconfiguration ready option.

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10.2.1 High Level Block Diagram

Figure 7 .1 in shows the block diagram of the design example.

alt_mge_rd_addrdec_mch

.
. .
alt_mge_channel

alt_mge_channel

S LL MAC
Avalon-ST
.
..
…

PHY
A10
Avalon- Avalon-
S /S10 Interface
S MM M PHY
Master
MM
...

XCVR
S Reset
S AVMM Mux Controller
S XCVR
Reconfig

10G 2.5G
1G
ATX ATX
FPLL
XCVR PLL PLL
S
Reconfig

Reset 10G Input 1G Input

Clock Clock

Figure 10.12: 1G/2.5G/10G Ethernet reference design block diagram

10.3 Partial Reconfiguration Ready

When Partial Reconfiguration Ready option is enabled, the generated Design Example hierarchy will be
compliance to partial reconfiguration flow. There will be clear separation between hard IP and soft IP.
Hard IP such as Native PHY, JTAG, TXPLL, FPLL will be instantiated at the top wrapper. Certain soft IP
such as XCVR reset controller and TXPLL reset controller will also be instantiated at the same level of
wrapper as their function is tighly coupled with the hard IP and not protocol based IP. There will be a
wrapper called alt_eth_pr which will contain all soft IP logic, which customer can put it in their PR
region. There is no functionality change after this option is enabled. The following diagram shows the
hierarchy difference before and after this option is enabled.

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Figure X: Example Design hierarchy before Partial Reconfiguration Ready option is enabled.

Figure X: Example Design hierarchy after Partial Reconfiguration Ready option is enabled.

10.4 Clocking Scheme

The following diagram shows the clocking scheme of the reference design.

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Figure 10.13: Clocking scheme of the reference design

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Figure 10.14: Clocking scheme of the reference design (S10)

10.5 Reset Scheme

Figure 10.15 Reset scheme of reference design

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Figure 10.16 Reset scheme of reference design (S10)

There is an active high asynchronous global reset signal at reference design top level (alt_mge_rd).
Internal reset signals will be synchronized to respective clock domain internally, and generated by
Transceiver Reset Controller as shown in Figure 7 .34 or 10.5.

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10.6 Generation Flow with parameter setting

10.6.1 Using the design example

The design example package comes with pre-generated RTL files for 2 channels. To use the reference
design, perform the following steps:
…

6. Unzip the package at the project directory.

7. Change directory to alt_mge_rd.
8. Launch the Quartus II software and open the project file alt_mge_top.qpf
9. Click Start Compilation on the Processing menu to compile the design example.

For Stratix 10:

1. Launch the Quartus II software, and launch Low Latency Ethernet 10G MAC from IP Catalog.
This will launch in Qsys Pro.
2. Go to Example Design tab, select the preset 1G/2.5G/10G Ethernet Example Design from the
Presets windows, and click Apply.
3. Click Generate Example Design…. Once finished, exit Qsys Pro without saving.
4. Open the project file altera_eth_top.qpf from directory

alt_em10g32_0_EXAMPLE_DESIGN/ LL10G_1G_2_5G_10G/.

5. Click Start Compilation on the Processing menu to compile the design example.

10.6.2 Changing the number of channels

In order to change the number of channels, modify the “NUM_OF_CHANNEL” parameter of

alt_mge_top for Quartus II compilation flow (or alt_mge_rd for simulation flow).

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10.6.3 Regenerate IP files when upgrade to new version of ACDS

The following table shows the IP that need regeneration and the tools involved.

IP Tools IP File Location

1G/2.5/10GbE MAC Qsys rtl/mac/alt_mgbaset_mac.qsys
1G/2.5/10GbE PHY Qsys rtl/phy/alt_mgbaset_phy.qsys
Transceiver Reset Controller Qsys rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel.qsys
for Channel
Transceiver Reset Controller Qsys rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_txpll.qsys
for TX PLL (Arria 10 only)
Transceiver TX PLL for 10 Qsys rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g.qsys
GbE
Transceiver TX PLL for 2.5 Qsys rtl/pll_atxpll /alt_mge_xcvr_atx_pll_2p5g.qsys
GbE
Transceiver TX PLL for 1 Qsys rtl/pll_fpll/alt_mge_xcvr_fpll_1g.qsys
GbE
PLL for MAC and User Logic Qsys rtl/pll_fpll/alt_mge_core_pll.qsys
Avalon-MM JTAG Master Qsys rtl/jtag_avalon_master/alt_jtag_csr_master.qsys
Address Decoder Qsys rtl/address_decoder/alt_mge_rd_addrdec_mch.qsys

Launch the tool and open the IP file as shown in the above table to regenerate the IP.

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10.7 Interface Signals

This section describes the interface signals at design example level, which is alt_mge_rd.

N: This is the number of channels parameter (NUM_OF_CHANNEL) set by user.

Some of the signals bus width is determined by NUM_OF_CHANNEL parameter.

10.7.1 Clock and Reset Signals

Signal Direction Width Description

csr_clk Input 1 Configuration clock for Avalon-MM
interface. The clock runs at 125MHz. In S10,
it also provides clock for transceiver reset
controller.
mac_clk Input 1 Clock for the MAC and Avalon-ST
interfaces. Its frequency is 156.25 MHz, and
must have 0 ppm frequency difference with
refclk.
Refclk Input 1 Reference clock for the TX PLLs. Its
frequency is 125 MHz.
rx_pma_clkout Output 1 Recovered clock from CDR
Reset Input 1 To reset the whole reference design.
Asynchronous and active high signal.
tx_digitalreset Output [N] Asynchronous active high reset signal for
TX data path of user logic.
rx_digitalreset Output [N] Asynchronous active high reset signal for
RX data path of user logic.

10.7.2 Avalon-MM Interface Signals

10.7.2.1 Ethernet MAC

Signal Direction Width Description

csr_mac_write Input [N] Assert this signal to request a write.
csr_mac_read Input [N] Assert this signal to request a read.
csr_mac_address Input [N][10] Use this bus to specify the register address
you want to read from or write to.
csr_mac_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_mac_readdata Output [N][32] Carries the data read from the specified
register.
csr_mac_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

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10.7.2.2 Ethernet PHY

Signal Direction Width Description

csr_phy_write Input [N] Assert this signal to request a write.
csr_phy_read Input [N] Assert this signal to request a read.
csr_phy_address Input [N][5] Use this bus to specify the register address
you want to read from or write to.
csr_phy_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_phy_readdata Output [N][32] Carries the data read from the specified
register.
csr_phy_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

10.7.2.3 1G/2.5G Ethernet Reconfiguration

Signal Direction Width Description

csr_rcfg_write Input 1 Assert this signal to request a write.
csr_rcfg_read Input 1 Assert this signal to request a read.
csr_rcfg_address Input 2 Use this bus to specify the register address
you want to read from or write to.
csr_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_rcfg_readdata Output 32 Carries the data read from the specified
register.

10.7.2.4 Direct Native PHY Reconfiguration (Arria 10 only)

Signal Direction Width Description

csr_native _phy_rcfg_write Input 1 Assert this signal to request a write.
csr_native _phy_rcfg_read Input 1 Assert this signal to request a read.
csr_native _phy_rcfg_address Input 10 Use this bus to specify the register address
you want to read from or write to.
csr_native _phy_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_native _phy_rcfg_readdata Output 32 Carries the data read from the specified
register.
csr_native _phy_rcfg_waitrequest Output 1 When asserted, this signal indicates that
the Native PHY is busy and not ready to
accept any read or write requests.

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10.7.3 Avalon-ST Interface Signals

Signal Direction Width Description

avalon_st_tx_startofpacket Input [N]
avalon_st_tx_endofpacket Input [N]
avalon_st_tx_valid Input [N]
avalon_st_tx_ready Output [N]
avalon_st_tx_data Input [N][32]
avalon_st_tx_empty Input [N][2]
avalon_st_tx_error Input [N]
avalon_st_rx_startofpacket Output [N]
avalon_st_rx_endofpacket Output [N] Refer to Low Latency Ethernet
avalon_st_rx_valid Output [N] 10G MAC User Guide, in section
avalon_st_rx_ready Input [N] 5-5 and 5-9, under “Avalon-ST
avalon_st_rx_data Output [N][32] Data Interfaces” and “Avalon-ST
avalon_st_rx_empty Output [N][2] Status Interfaces”
avalon_st_rx_error Output [N][6]
avalon_st_tx_status_valid Output [N]
avalon_st_tx_status_data Output [N][40]
avalon_st_tx_status_error Output [N][7]
avalon_st_rx_status_valid Output [N]
avalon_st_rx_status_data Output [N][40]
avalon_st_rx_status_error Output [N][7]
avalon_st_pause_data Input [N][2]

10.7.4 PHY Interface Signals

Signal Direction Width Description

rx_serial_data Input [N]
tx_serial_data Output [N] Refer to 1G/2.5G Ethernet PHY User
led_link Output [N] Guide, in section 3, under “1G/2.5G
led_char_err Output [N] Ethernet PHY Interface Signals”
led_disp_err Output [N]
led_an Output [N]
channel_tx_ready Output [N] This signal is asserted when the channel TX
data path is ready for data transmission.
channel_rx_ready Output [N] This signal is asserted when the channel RX
data path is ready for data transmission.

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10.8 Register Map

An address decoder module is provided in the reference design which is instantiated in simulation
testbench and hardware testing Quartus II project for demonstration purpose.

Table 1 .1 shows the address offsets in the 1G/2.5/10G Ethernet Reference Design.

Block/
Sub-block Address Offset Comments

1G/2.5/10G 0x00_0000
Ethernet
Reconfiguration

Channel-0 0x01_0000

1G/2.5/10GbE 0x0000
MAC

1G/2.5/10GbE 0x8000
PHY

Native PHY Rcfg 0xA000 Available in Arria 10 / Stratix

10 only

Channel-1 0x02_0000

1G/2.5/10GbE 0x0000
MAC

1G/2.5/10GbE 0x8000
PHY

Native PHY Rcfg 0xA000 Available in Arria 10 / Stratix

10 only

Traffic Controller 0x10_0000

Table 10.4.12: Address Offset of Reference Design

10.8.1 1G/2.5/10G Ethernet Reconfiguration Controller

Table 1 .2, Table 1 .3, Table 1 .4 shows the register offset and bit offset of 1G/2.5/10G Ethernet
Reconfiguration Controller.

Word Offset Register Name Access Reset Value Descriptions

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0x00 logical_channel_number RW 0x000 [9:0] Logical

number of the
reconfig
controller block

Write has no
effect when
reconfig is busy.
0x01 control RW Refer to table Control
below reconfiguration
process
0x02 status RO Refer to table Indicates status
below of
reconfiguration
process
0x03 Reserved - - -
Table 10.4.13: Register Offset of 1G/2.5/10G Ethernet Reconfiguration Controller

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Bit Register Name Access Reset Value Descriptions

[1:0] speed_select RW 0x00 Select the
operating speed
of the
transceiver to be
reconfigured to.

2’b00: 1GbE
2’b01: 2.5GbE
2’b10: Reserved
2’b11: 10GbE

Write has no
effect when
reconfig is busy.
[15:2] Reserved - 0x0000 -
16 reconfig_start RWC 0x0 When its value is
0, write 1 to start
reconfiguration
process.

Self-cleared
when
reconfiguration
is completed.

Write has no
effect when
reconfig is busy.
[31:17] Reserved - 0x000000 -
Table 10.4.14: Bit Offset of Control Register

Bit Register Name Access Reset Value Descriptions

0 reconfig_busy RO 0x0 Indicates
reconfiguration
is in progress
and busy.
Table 10.4.15: Bit Offset of Status Register

10.8.2 1G/2.5/10G Ethernet MAC

For register map and detail explanation of the register usage, refer to Low Latency Ethernet 10G MAC
User Guide, in section 4, under “Configuration Registers”.

10.8.3 PHY

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For register map and detail explanation of the register usage, refer to 1G/2.5/10G Ethernet PHY User
Guide, in section 4, under “1G/2.5/10G Ethernet PHY Configuration Registers”.

10.9 Simulating the example design Testbench

Altera provides testbench for you to demonstrate the behavior of 1G/2.5/10G Ethernet Reference
Design. The following sections describe the testbench, its components, and use.

10.9.1 Simulation Collateral

10.9.1.1 Testbench Block Diagram

The testbench operates in loopback mode. Figure 1 .4 shows the flow of the packets in the design
example.

Figure 10.4: Testbench Block Diagram

10.9.1.2 Testbench Components

The testbench comprise the following modules:

 Device under test (DUT)—the design example.

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 Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit
and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-
MM interfaces of the design example components.
 Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the
simulator console.

10.9.1.3 Testbench Files

The <project directory>/LL10G_Ethernet_A10_1G_2_5G_10G/simulation/ed_sim/models directory

contains the testbench files.

Table 1 .5 describes the files that implement the reference design testbench.

File Name Description

avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
gen_sim_script.sh A script to generate simulation scripts required for simulators.
Execute this script if IP cores are regenerated.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top.sv The top-level testbench file. This file includes the reference
design (alt_mge_rd), which is the device under test (DUT), a
client packet generator, and a client packet monitor along
with other logic blocks.
../<simulator >/tb_run.tcl A Tcl script that starts a simulation session in the Simulator
software.
../<simulator>/wave.do A signal tracing macro script for use with the Simulator software
to display testbench signals.
Table 10.4.16: Testbench Files

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10.9.2 Test Cases

Test cases are included to show case how to change channel speed to 1G/2.5G/10G and MAC
configuration.

10.9.2.1 Reconfigure PHY Speed

By default, the 1G/2.5G/10G PHY is operating in 2.5GbE mode. In order to switch the transceiver
operating speed from 2.5GbE to 1GbE and 10G or vice versa, user need to perform following steps to
instruct 1G/2.5G/10G Ethernet Reconfiguration Controller to reconfigure the PHY.

1. Read from status register to ensure reconfig_busy bit is 0.

2. Write to logical_channel_number register to select the channel to be reconfigured.
3. Write the selected operating speed to speed_select and 1 to reconfig_start bit of control
register.
4. The reconfig_busy bit of status register will be read as 1 during reconfiguration process.
5. Then reconfiguration process is completed when the reconfig_busy bit is read as 0.
6. Transceiver reset sequence will be triggered automatically when the reconfiguration is
completed.

10.9.2.2 MIF File

MIF files for transceiver reconfiguration will be generated by 1G/2.5G/10G PHY according to

Error: Reference source not found.

Operating MIF Files

Mode
1GbE rtl/phy/alt_mgbaset_phy/altera_xcvr_native_<family>_<acds_version>/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG0.mif
2.5GbE rtl/phy/alt_mgbaset_phy/altera_xcvr_native_<family>_<acds_version>/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG1.mif
10GbE rtl/phy/alt_mgbaset_phy/altera_xcvr_native_<family>_<acds_version>/synth/reconfig/alt_mge_phy_reconfig_parameters_CFG2.mif

Table 10.4.17: Transceiver Reconfiguration MIF Files

10.9.2.3 Testcase 1

Configuration:

1. 2 channels
2. Circular loopback (as shown in diagram in Figure 1 .4)

Test Scenario:

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1. Design start up with channel configured to 10G Ethernet mode.

2. Do basic MAC configuration and PHY speed configuration for all 2 channels.
3. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.
4. Send 3 different type of packets:
a. 64-byte packet
b. 1518-byte packet
c. 100-byte packet
5. Repeat step 2 to 4 for 2.5G and 1G Ethernet mode.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window.
The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all
packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal
to the TX MAC statistics counters.

10.10 Testing the ED in hardware

10.10.1 Hardware setup

10.10.1.1 Hardware Testing: Multi Gigabit Ethernet (MGE) 1G/2.5G/10G

Hardware testing will be carryout in reference design level with the following
environment setting in Arria 10 /Stratix 10 family. The following equipment/tools are
needed to carry out hardware testing:
o FPGA Dev. Kit:
 Arria 10 Si Dev Kit for Arria 10 testing
 Stratix 10 Si Dev Kit for Stratix 10 testing
o Cables:
 SMA cable
 SFP+
 Fiber Optic cable
o 3rd Party Tester:
 Spirent Test Center and LSI mission board for 2.5G testing
 SmartBit for 1G testing

10.10.1.2 DUT Implementation with LSI Mission Board

The DUT is represented by LSI Mission board together with a development board shown
in Figure with 2.5G system image programmed into a development board. The framework
is illustrated in Figure . The board is a universal development board, but none of the other
components is used. The test flow is stimulus will be pumped into the DUT by the Spirent
Testcenter and later will return back to the testcenter.

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Avalon-MM
Control Interface

DUT 2.5G SYSTEM

Pipeline Bridge

Spirent Testcenter LSI 2.5-Gbps 2.5-Gbps

Avalon-ST Dual-Clock FIFOs
Mission Board Ethernet PHY Ethernet MAC

Figure 10.5: DUT Implementation with LSI Mission Board

10.10.1.3 Hardware Testing: Test Procedure

Follow these steps to test the design examples in hardware:

1. Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 10G 80000000

Parameter Valid Values Description

channel 0, 1 The channel number to test.
speed 1G, 2.5G, 10G The PHY speed.
burst_size An integer value The number of packets to generate for the test

2. When the test is completed, observe the output displayed. The following diagrams
show excerpts of the output, which shows that the packet monitor block receives
the same number of packets generated without error, and the TX and RX statistics
counters.

TEST_INFO: 10G board trace Loopback Test

CONFIGURE CHANNEL 1
Configure to 10G
Setting up mac with a basic working config
Setting 0xC5C4 into rxmac primary address Reg-1
Setting 0xC3C2C1C0 into rxmac primary address Reg-0
Enabling: crc insertion in tx mac
Enabling: pad and crc stripping in rx mac
Setting 1518 into rxmac max frame length
Setting 1518 into txmac max frame length
Clearing mac stats registers
Select std ethernet traffic controller

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Disable Avalon ST Loopback

====================================================================================
B E G I N C O N F I G U R A T I O N

====================================================================================
payload length = variable (random) ....
payload bytes = random bytes ....
burst size = 80000000 ....
payload length = 1518 ....
frame source addres field = F0F1F2F3F4F5 ....
frame destination addres field = C5C4C3C2C1C0 ....
reseting monitor Packet Counters
number of Packets Expected By Monitor = 0x4c4b400
burst being injected into device ....
-- MONITOR processing frames received .....

-- MONITOR Received Packet# 16449027]

-- MONITOR Received Packet# 32852616]

-- MONITOR Received Packet# 49623544]

-- MONITOR Received Packet# 65916989]

-- MONITOR Received Packet# 80000000]

-- DONE! - monitor received all expected sum of packets .....

_______________________________________________________________________________________

-- (MONITOR) GOOD PKTS RECEIVED = 80000000

-- (MONITOR) BAD PKTS RECEIVED = 0
-- (MONITOR) BYTES RECEIVED = 51127220644
-- (MONITOR) CYCLES USED = 6638745226
-- (MONITOR) THROUGHPUT CALCULATED = 9.63 Gbps
-- (MONITOR) RXBYTECNT_LO32 = 3882580399
-- (MONITOR) RXBYTECNT_HI32 = 11
-- (MONITOR) RXCYCLCNT_LO32 = 2343777931
-- (MONITOR) RXCYCLCNT_HI32 = 1

_______________________________________________________________________________________

======================================================================
| MAC TX STATS REGISTER CHECK
======================================================================
|# FRAMES_RECEIVED_WITH_ERROR = 0
|# UNICAST_FRAMES_WITH_ERROR = 0
|# MULTICAST_FRAMES_RECEIVED_WITH_ERROR = 0
|# BRDCAST_FRAMES_WITH_ERROR = 0
|# FRAMES_RECEIVED_WITH_ONLY_CRCERROR = 0
|# VALID_LENGTH_FRAMES_WITH_CRC_ERROR = 0
|# JABBER_FRAMES = 0
|# FRAGMENTED_FRAMES = 0
|# INVALID_FRAMES_RECEIVED = 0
|# FRAMES_RECEIVED_GOOD = 80000000
|# PAUSE_FRAMES_RECEIVED = 0
|# UNICAST_CONTROL_FRAMES = 0
|# MULTICAST_CONTROL_FRAMES = 0
|# UNICAST_FRAMES_RECEIVED_GOOD = 0
|# MULTICAST_FRAMES_RECEIVED_GOOD = 80000000
|# BRDCAST_FRAMES_GOOD = 0
|# DATA_AND_PADDING_OCTETS_RECEIVED_GOOD = 2825321541
|# COMPREHENSICE_OCTETS_RECEIVED = 4265321541
|# FRAMES_WITH_SIZE_64_BYTES = 3190250
|# FRAMES_BETWEEN_SIZE_64AND127_BYTES = 4966646
|# FRAMES_BETWEEN_SIZE_128AND255_BYTES = 10106109
|# FRAMES_BETWEEN_SIZE_256AND511_BYTES = 19843321

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|# FRAMES_BETWEEN_SIZE_512AND1K_BYTES = 22624769
|# FRAMES_BETWEEN_SIZE_1KND1518_BYTES = 19268905
======================================================================
| MAC RX STATS REGISTER CHECK
======================================================================
|# FRAMES_RECEIVED_WITH_ERROR = 0
|# UNICAST_FRAMES_WITH_ERROR = 0
|# MULTICAST_FRAMES_RECEIVED_WITH_ERROR = 0
|# BRDCAST_FRAMES_WITH_ERROR = 0
|# FRAMES_RECEIVED_WITH_ONLY_CRCERROR = 0
|# VALID_LENGTH_FRAMES_WITH_CRC_ERROR = 0
|# JABBER_FRAMES = 0
|# FRAGMENTED_FRAMES = 0
|# INVALID_FRAMES_RECEIVED = 0
|# FRAMES_RECEIVED_GOOD = 80000000
|# PAUSE_FRAMES_RECEIVED = 0
|# UNICAST_CONTROL_FRAMES = 0
|# MULTICAST_CONTROL_FRAMES = 0
|# UNICAST_FRAMES_RECEIVED_GOOD = 0
|# MULTICAST_FRAMES_RECEIVED_GOOD = 80000000
|# BRDCAST_FRAMES_GOOD = 0
|# DATA_AND_PADDING_OCTETS_RECEIVED_GOOD = 2825321541
|# COMPREHENSICE_OCTETS_RECEIVED = 4265321541
|# FRAMES_WITH_SIZE_64_BYTES = 3190250
|# FRAMES_BETWEEN_SIZE_64AND127_BYTES = 4966646
|# FRAMES_BETWEEN_SIZE_128AND255_BYTES = 10106109
|# FRAMES_BETWEEN_SIZE_256AND511_BYTES = 19843321
|# FRAMES_BETWEEN_SIZE_512AND1K_BYTES = 22624769
|# FRAMES_BETWEEN_SIZE_1KND1518_BYTES = 19268905
|# FRAMES_BETWEEN_SIZE_ABOVE1519_BYTES = 0

10.10.2 Timing closure

10.10.3 SingalTap signaling

11 Functional description: 1G/2.5G/10GbE MAC + PHY with IEEE 1588v2

This document describes the 1G/2.5G/10GbE MAC + PHY with IEEE 1588v2 reference design for Stratix
10, the testbench, and its components.

11.1 Software and Hardware Requirements

Intel uses the following hardware and software to test the 1G/2.5G/10GbE MAC + PHY with IEEE 1588v2
reference design and testbench:

■ Intel Quartus Prime Pro Edition 17.1 Build 143

■ Stratix 10 SI Development Board (device: 1SG280LU3F50E2VGS1)
■ ModelSim-SE 10.5c

11.2 Features

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This reference design contains pre-generated RTL files which support 2-channels. You can use the
testbench and simulation script (ModelSim) provided to simulate the design in a simulator. This
reference design also support partial reconfiguration ready option.

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11.2.1 High Level Block Diagram

Figure 7 .1 in shows the block diagram of the design example.

altera_eth_top

alt_mge_rd

.
. .
alt_mge_rd_addrdec_mch alt_mge_channel

alt_mge_channel PTP
Packet Avalon-ST
Classifier
Pulse-
per- 1G/2.5G/10G
Second
Pulse Per
Second
S LL MAC
Local TOD
S
TOD Sync
.
..
…

Avalon-
Avalon-
TX/RX Serial
Avalon- MM
S S10
S MasterMM M PHY Data
MM Master
...

XCVR
S Reset
S AVMM Mux Controller
S XCVR
Reconfig

S Master
TOD
S S S
S S 1 1 1
1 1 0 0 0

S XCVR 0 0
A
A
T
A
T
A
T

Reconfig
A
Pulse-
Master Pulse
per- Per Second
Second

CoreF
PLL

Reset 1G_2.5G/10G/Core
CSR Clock Reference Clocks

Figure 11.1: S10 1G/2.5G/10G IEEE 1588 Ethernet reference design block diagram

Generated with IP Catalog StaticXRTL

Generated with Qsys

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11.3 Clocking Scheme

The following diagram shows the clocking scheme of the reference design.

Figure 4.211.2: Clocking scheme of the reference design (for S10)

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11.4 Reset Scheme

Figure 11.3: Reset scheme of reference design

There is an active high asynchronous global reset signal at reference design top level (alt_mge_rd).
Internal reset signals will be synchronized to respective clock domain internally, and generated by
Transceiver Reset Controller as shown in Figure 7 .3.

11.5 Generation Flow with parameter setting

11.5.1 Using the design example

The design example package comes with pre-generated RTL files for 2 channels. To use the reference
design, perform the following steps:
…

1. Launch the Quartus II software, and launch Low Latency Ethernet 10G MAC from IP Catalog.
This will launch in Qsys Pro.
2. Go to Example Design tab, select the preset 1G/2.5G/10G Ethernet with 1588 Example Design
from the Presets windows, and click Apply.
3. Click Generate Example Design…. Once finished, exit Qsys Pro without saving.
4. Open the project file altera_eth_top.qpf from directory
alt_em10g32_0_EXAMPLE_DESIGN/LL10G_1G_2_5G_10G_1588v2/.
5. Click Start Compilation on the Processing menu to compile the design example.

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11.5.2 Changing the number of channels

In order to change the number of channels, modify the “NUM_OF_CHANNEL” parameter of

altera_eth_top.v for Quartus II compilation flow (or alt_mge_rd.v for simulation flow).

11.5.3 Regenerate IP files when upgrade to new version of ACDS

The following table shows the IP that need regeneration and the tools involved.

IP Tools IP File Location

Low Latency Ethernet 10G MAC IP Catalog rtl/mac/alt_mgbaset_mac.ip
1G/2.5G/5G/10G Multi-rate IP Catalog rtl/phy/alt_mgbaset_phy.ip
Ethernet PHY
Stratix 10 Transceiver PHY Reset IP Catalog rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel.ip
Controller
Stratix 10 L-Tile/H-Tile IP Catalog rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g.ip
Transceiver ATX PLL (10G TX PLL)
Stratix 10 L-Tile/H-Tile IP Catalog rtl/pll_atxpll/alt_mge_xcvr_atx_pll_2p5g.ip
Transceiver ATX PLL (2.5G TX PLL)
Stratix 10 L-Tile/H-Tile fPLL (1G IP Catalog rtl/pll_fpll/alt_mge_xcvr_fpll_1g.ip
TX PLL)
Stratix 10 L-Tile/H-Tile fPLL (PLL IP Catalog rtl/pll_fpll/alt_mge_core_pll.ip
for MAC and User Logic)
Stratix 10 L-Tile/H-Tile fPLL (PLL IP Catalog rtl/pll_fpll/pll_sampling_clk.ip
for PHY latency_sclk)
Stratix 10 L-Tile/H-Tile fPLL (PLL IP Catalog rtl/pll_fpll/pll_tod_sync_sampling_clk.ip
for sampling clock for TOD sync)
Ethernet IEEE 1588 Time of Day IP Catalog rtl/tod/alt_mge_1588_tod_master.ip
Clock
Ethernet IEEE 1588 Time of Day IP Catalog rtl/tod/alt_mge_1588_tod_10g.ip
Clock
Ethernet IEEE 1588 Time of Day IP Catalog rtl/tod/alt_mge_1588_tod_2p5g.ip
Clock
Ethernet IEEE 1588 Time of Day IP Catalog rtl/tod/alt_mge_1588_tod_1g.ip
Clock
Ethernet IEEE 1588 TOD IP Catalog rtl/tod_sync/alt_mge_1588_tod_sync_64b_10g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/tod_sync /alt_mge_1588_tod_sync_96b_10g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/tod_sync/alt_mge_1588_tod_sync_64b_2p5g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/tod_sync /alt_mge_1588_tod_sync_96b_2p5g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/tod_sync /alt_mge_1588_tod_sync_64b_1g.ip
Synchronizer
Ethernet IEEE 1588 TOD IP Catalog rtl/tod_sync /alt_mge_1588_tod_sync_96b_1g.ip
Synchronizer

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Ethernet Packet Classifier IP Catalog rtl/pkt_classifier/alt_mge_packet_classifier.ip

JTAG to Avalon Master Bridge IP Catalog rtl/jtag_avalon_master/alt_jtag_csr_master.ip
Address Decoder Qsys rtl/address_decoder/alt_mge_rd_addrdec_mch.qsys
Avalon-MM Mux for XCVR Qsys rtl/address_decoder/alt_mge_rd_avmm_mux_xcvr_rcfg.qsys
Reconfig

Launch the tool and open the IP file as shown in the above table to regenerate the IP.

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11.6 Interface Signals

This section describes the interface signals at design example level, which is alt_mge_rd.

N: This is the number of channels parameter (NUM_OF_CHANNEL) set by user.

Some of the signals bus width is determined by NUM_OF_CHANNEL parameter.

11.6.1 Clock and Reset Signals

Signal Direction Width Description

csr_clk Input 1 Configuration clock for Avalon-MM
interface. The clock runs at 125MHz.
mac_clk Input 1 Clock for the MAC internal logic running at
32-bit interfaces. Its frequency is 312.5
MHz, and must have 0 ppm frequency
difference with refclk.
mac6b_clk Input 1 Clock for the MAC and Avalon-ST logic
running at 64-bit interfaces. Its frequency is
156.25 MHz, and must have 0 ppm
frequency difference with refclk.
refclk_1g2p5g Input 1 Reference clock for the 1G, 2.5G TX PLLs,
and TOD sampling_clk PLLs. Its frequency is
125 MHz.
refclk_core Input 1 Reference clock for Transceiver PHY Reset
Controller and TOD core logics. Its
frequency is 125 MHz.
refclk_10g Input 1 Reference clock for the 10G TX PLLs. Its
frequency is 644.63125 MHz.
reset Input 1 To reset the whole reference design.
Asynchronous and active high signal.
tx_digitalreset Output [N] Asynchronous active high reset signal for
TX data path of user logic.
rx_digitalreset Output [N] Asynchronous active high reset signal for
RX data path of user logic.
rx_digitalreset_stat Output [N] Status signal for rx_digitalreset from PHY.

11.6.2 Avalon-MM Interface Signals

11.6.2.1 Low Latency Ethernet MAC

Signal Direction Width Description

csr_mac_write Input [N] Assert this signal to request a write.
csr_mac_read Input [N] Assert this signal to request a read.
csr_mac_address Input [N][10] Use this bus to specify the register address
you want to read from or write to.
csr_mac_writedata Input [N][32] Carries the data to be written to the

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specified register.
csr_mac_readdata Output [N][32] Carries the data read from the specified
register.
csr_mac_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

11.6.2.2 1G/2.5G/5G/10G Multi-rate Ethernet PHY

Signal Direction Width Description

csr_phy_write Input [N] Assert this signal to request a write.
csr_phy_read Input [N] Assert this signal to request a read.
csr_phy_address Input [N][5] Use this bus to specify the register address
you want to read from or write to.
csr_phy_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_phy_readdata Output [N][32] Carries the data read from the specified
register.
csr_phy_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

11.6.2.3 1G/2.5G/10G Ethernet Reconfiguration

Signal Direction Width Description

csr_rcfg_write Input 1 Assert this signal to request a write.
csr_rcfg_read Input 1 Assert this signal to request a read.
csr_rcfg_address Input 2 Use this bus to specify the register address
you want to read from or write to.
csr_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_rcfg_readdata Output 32 Carries the data read from the specified
register.

11.6.2.4 Direct Native PHY Reconfiguration

Signal Direction Width Description

csr_native _phy_rcfg_write Input 1 Assert this signal to request a write.
csr_native _phy_rcfg_read Input 1 Assert this signal to request a read.
csr_native _phy_rcfg_address Input 11 Use this bus to specify the register address
you want to read from or write to.
csr_native _phy_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_native _phy_rcfg_readdata Output 32 Carries the data read from the specified
register.
csr_native _phy_rcfg_waitrequest Output 1 When asserted, this signal indicates that

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the Native PHY is busy and not ready to

accept any read or write requests.

11.6.2.5 Time of Day Master

Signal Direction Width Description

csr_master_tod_write Input [N] Assert this signal to request a write.
csr_master_tod_read Input [N] Assert this signal to request a read.
csr_master_tod_address Input [N][4] Use this bus to specify the register address
you want to read from or write to.
csr_master_tod_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_master_tod_readdata Output [N][32] Carries the data read from the specified
register.
csr_master_tod_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

11.6.3 Avalon-ST Interface Signals

Signal Direction Width Description

avalon_st_tx_startofpacket Input [N]
avalon_st_tx_endofpacket Input [N]
avalon_st_tx_valid Input [N]
avalon_st_tx_ready Output [N]
avalon_st_tx_data Input [N][64]
avalon_st_tx_empty Input [N][3]
avalon_st_tx_error Input [N]
avalon_st_rx_startofpacket Output [N]
avalon_st_rx_endofpacket Output [N] Refer to Low Latency Ethernet
avalon_st_rx_valid Output [N] 10G MAC User Guide, in section
avalon_st_rx_ready Input [N] 5-5 and 5-9, under “Avalon-ST
avalon_st_rx_data Output [N][64] Data Interfaces” and “Avalon-ST
avalon_st_rx_empty Output [N][3] Status Interfaces”
avalon_st_rx_error Output [N][6]
avalon_st_tx_status_valid Output [N]
avalon_st_tx_status_data Output [N][40]
avalon_st_tx_status_error Output [N][7]
avalon_st_rx_status_valid Output [N]
avalon_st_rx_status_data Output [N][40]
avalon_st_rx_status_error Output [N][7]
avalon_st_pause_data Input [N][2]

11.6.4 IEEE 1588v2 Timestamp Interface Signals

Signal Direction Width Description

tx_egress_timestamp_96b_valid Output [N] Refer to Low Latency Ethernet
tx_egress_timestamp_96b_data Output [N][96] 10G MAC User Guide, in section 5-
tx_egress_timestamp_96b_fingerprint Output [N][TSTAMP_FP_WIDTH]

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tx_egress_timestamp_64b_valid Output [N] 18, under “IEEE 1588v2

tx_egress_timestamp_64b_data Output [N][64] Interfaces”
tx_egress_timestamp_64b_fingerprint Output [N][TSTAMP_FP_WIDTH]
rx_ingress_timestamp_96b_valid Output [N]
rx_ingress_timestamp_96b_data Output [N][96]
rx_ingress_timestamp_64b_valid Output [N]
rx_ingress_timestamp_64b_data Output [N][64]

11.6.5 Packet Classifier Interface Signals

Signal Direction Width Description

tx_egress_timestamp_request_in_valid Input [N] Assert this signal when timestamp is
required for the particular frame. This
signal must be aligned to the start of an
incoming packet.
tx_egress_timestamp_request_in_fingerprint Input [N][TSTAMP_FP_WIDTH] A width-configurable fingerprint that
correlates timestamps for incoming
packets.
clock_operation_mode_mode Input [N][2] Determines the clock mode.
00: Ordinary clock
01: Boundary clock
10: End to end transparent clock
11: Peer to peer transparent clock
pkt_with_crc_mode Input [N] Indicates whether or not a packet
contains CRC.
1: Packet contains CRC
0: Packet does not contain CRC
tx_ingress_timestamp_valid Input [N] Indicates the update for residence time.
1: Allows update for residence time based
on decoded results.
0: Prevents update for residence time.
When this signal is deasserted,
tx_etstamp_ins_ctrl_out_residence_ti
me_update also gets deasserted.
tx_ingress_timestamp_96b_data Input [N][96] 96-bit format of ingress timestamp that
holds data so that the output can align
with the start of an incoming packet.
tx_ingress_timestamp_64b_data Input [N][64] 64-bit format of ingress timestamp that
holds data so that the output can align
with the start of an incoming packet.
tx_ingress_timestamp_format Input [N] Format of the timestamp to be used for
calculating residence time. This signal
must be aligned to the start of an
incoming packet. A value of 0 indicates 96
bit timestamp format while 1 indicates 64
bit timestamp format.

11.6.6 PHY Interface Signals

Signal Direction Width Description

rx_serial_data Input [N] Refer to 1G/2.5G/5G/10G Multi-rate
tx_serial_data Output [N] Ethernet PHY User Guide
led_link Output [N]
led_char_err Output [N]

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led_disp_err Output [N]

led_an Output [N]
channel_tx_ready Output [N] This signal is asserted when the channel
TX data path is ready for data
transmission.
channel_rx_ready Output [N] This signal is asserted when the channel
RX data path is ready for data
transmission.

11.6.7 TOD Interface Signals

Signal Direction Width Description

master_pulse_per_second Output 1 Pulse per second output from Master PPS
module. The pulse per second output will
be asserted for 10ms.
start_tod_sync Input [N] Start TOD synchronization process. As long
as this signal is asserted high, the
synchronization process will continue and
Time of Day from master TOD will be
repeatedly synchronized to local TOD.
pps Output [N] Pulse per second output from 1G or 2.5G
PPS module (depending on current speed
configuration) in channel-n. The pulse per
second output will be asserted for 10ms.

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11.7 Register Map

An address decoder module is provided in the reference design which is instantiated in simulation
testbench and hardware testing Quartus II project for demonstration purpose.

Table 1 .1 shows the address offsets in the 1G/2.5G/10G with 1588 Ethernet Reference Design.

Block/ Address
Sub-block Offset Comments
1G/2.5G/10G 0x00_0000
Ethernet
Reconfiguration
TOD Master 0x00_4000
Channel-0 0x01_0000
MAC 0x0000
PHY 0x8000
Native PHY Rcfg 0xA000
Channel-1 0x02_0000
MAC 0x0000
PHY 0x8000
Native PHY Rcfg 0xA000
Traffic Controller 0x10_0000
Table 11.18: Address Offset of Reference Design

11.7.1 1G/2.5/10G Ethernet Reconfiguration Controller

Table 1 .2, Table 1 .3, Table 1 .4 shows the register offset and bit offset of 1G/2.5G/10G Ethernet
Reconfiguration Controller.

Word Offset Register Name Access Reset Value Descriptions

0x00 logical_channel_number RW 0x000 [9:0] Logical
number of the
reconfig
controller block

Write has no
effect when
reconfig is busy.
0x01 control RW Refer to table Control
below reconfiguration
process
0x02 status RO Refer to table Indicates status
below of
reconfiguration
process
0x03 Reserved - - -
Table 11.19: Register Offset of 1G/2.5G/10G Ethernet Reconfiguration Controller

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Bit Register Name Access Reset Value Descriptions

[1:0] speed_select RW 0x00 Select the
operating speed
of the
transceiver to be
reconfigured to.

2’b00: 1GbE
2’b01: 2.5GbE
2’b10: Reserved
2’b11: 10G

Write has no
effect when
reconfig is busy.
[15:2] Reserved - 0x0000 -
16 reconfig_start RWC 0x0 When its value is
0, write 1 to start
reconfiguration
process.

Self-cleared
when
reconfiguration
is completed.

Write has no
effect when
reconfig is busy.
[31:17] Reserved - 0x000000 -
Table 11.20: Bit Offset of Control Register

Bit Register Name Access Reset Value Descriptions

0 reconfig_busy RO 0x0 Indicates
reconfiguration
is in progress
and busy.
Table 11.21: Bit Offset of Status Register

11.7.2 TOD Master

For register map and detail explanation of the register usage, refer to 10-Gbps Ethernet MAC MegaCore
Function User Guide, in section B.6, under “ToD Clock Configuration Register Space.

11.7.3 Low Latency Ethernet MAC

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For register map and detail explanation of the register usage, refer to Low Latency Ethernet 10G MAC
User Guide, in section 4, under “Configuration Registers”.

11.7.4 1G/2.5G/5G/10G Multi-rate Ethernet PHY

For register map and detail explanation of the register usage, refer to 1G/2.5G/5G/10G Multi-rate
Ethernet PHY User Guide.

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11.8 Simulating the example design

11.8.1.1 Simulation Collateral

Altera provides testbench for you to demonstrate the behavior of 1G/2.5G/10G with 1588 Ethernet
Reference Design. The following sections describe the testbench, its components, and use.

11.8.1.2 Testbench Block Diagram

The testbench operates in loopback mode. Figure 1 .4 shows the flow of the packets in the design
example.

Figure 11.4: Testbench Block Diagram

11.8.1.3 Testbench Components

The testbench comprise the following modules:

 Device under test (DUT)—the design example.
 Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit
and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-
MM interfaces of the design example components.

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 Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the
simulator console.

11.8.1.4 Testbench Files

The <project directory>/simulation/ed_sim/models directory contains the testbench files.

Table 1 .5 describes the files that implement the reference design testbench.

File Name Description

avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
ptp_timestamp.sv A SystemVerilog HDL class that defines the timestamp in the
testbench.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top.sv The top-level testbench file. This file includes the reference
design (alt_mge_rd), which is the device under test (DUT), a
client packet generator, and a client packet monitor along
with other logic blocks.
Table 11.22: Testbench Files

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11.8.1.5 Simulating Design Example Testbench

Simulation script uses QUARTUS_ROOTDIR environment variable to access Altera’s simulation model
libraries. QUARTUS_ROOTDIR should has been set and pointed to the Quartus II installation path after
proper installation. You need to set it manually if this environment variable is missing.

11.8.1.6 Using ModelSim Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

1. Change directory to <project directory>/simulation/ed_sim/mentor/

2. Launch ModelSim, run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model with the
provided testbench:
 do tb_run.tcl

11.8.1.7 Using VCS Simulator

To use the VCS simulator to simulate the testbench design, follow these steps:

3. Change directory to <project directory>/simulation/ed_sim/synopsys/vcs/

4. Run the following command to set up the required libraries, to compile the generated IP
Functional simulation model, and to exercise the simulation model with the provided testbench:
 sh tb_run.sh

11.8.1.8 Using NCSim Simulator

To use the NCSim simulator to simulate the testbench design, follow these steps:

5. Change directory to <project directory>/simulation/ed_sim/cadence/

6. Run the following command to set up the required libraries, to compile the generated IP
Functional simulation model, and to exercise the simulation model with the provided testbench:
 sh tb_run.sh

11.8.1.9 Test Cases

Test cases are included to show case how to change channel speed to 1G/2.5G/10G and MAC
configuration.

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11.8.1.10 Reconfigure PHY Speed

By default, the PHY is operating in 10GbE mode. In order to switch the transceiver operating speed from
10GbE to 2.5GbE and 1GbE or vice versa, user needs to perform the following steps to instruct
1G/2.5G/10G Ethernet Reconfiguration Controller to reconfigure the PHY.

13. Read from status register to ensure reconfig_busy bit is 0.

14. Write to logical_channel_number register to select the channel to be reconfigured.
15. Write the selected operating speed to speed_select and 1 to reconfig_start bit of control
register.
16. The reconfig_busy bit of status register will be read as 1 during reconfiguration process.
17. Then reconfiguration process is completed when the reconfig_busy bit is read as 0.
18. Transceiver reset sequence will be triggered automatically when the reconfiguration is
completed.

11.8.1.11 MIF File

For Stratix 10 device family, MIF files for transceiver reconfiguration will be generated by
1G/2.5G/5G/10G Multi-rate Ethernet PHY according to Table 11.6.

Operating MIF Files

Mode
1GbE rtl/reconfig/alt_mge_rcfg_xcvr_1g.mif
2.5GbE rtl/reconfig/alt_mge_rcfg_xcvr_2p5g.mif
10GbE rtl/reconfig/alt_mge_rcfg_xcvr_10g.mif
Table 11.6: Transceiver Reconfiguration MIF Files for Stratix 10

11.8.1.12 Testcase 1

Configuration:

1. 2 channels
2. Circular loopback (as shown in diagram in Figure 1 .4)

Test Scenario:

1. Design start up with channel configured to 10G Ethernet mode.

2. Do basic MAC configuration and PHY speed configuration for all 2 channels.
3. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.
4. Send 7 different types of packets:

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a. Non-PTP
b. No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
c. VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
d. Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
e. No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
f. VLAN, PTP over UDP/IPv4, PTP Delay Request Message, 2-step PTP
g. Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
5. Repeat step 2 to 4 for 2.5G and 1G Ethernet mode.

After the simulation stop, user can refer to the transcript window for channel 0 MAC TX and RX Statistic
counter result.

For each operating speed, if all the total 7 packets have been received successfully to channel 0 Avalon-
ST RX interface, the transcript will print out “Simulation PASSED”.

11.9 Testing the ED in hardware

<To be updated by Validation Team>

11.10 Known Issues

N/A

12 Functional Description: 10G Base-R Example Design

(Note: This section is derived from Chapter 6: 10G Base-R Register Mode Example Design. The different
is highlighted in yellow.)

This Example Design demonstrates Low Latency 10G Ethernet IP solution for Arria 10/Stratix 10 using
Low Latency 10G Ethernet MAC and Native PHY IP cores with small form factor pluggable plus (SFP+). It
supports packet monitoring system on transmit and receive paths and report Ethernet MAC statistics
counter for transmit and receive data paths.

The key differences between 10G Base-R and 10G Base-R register mode (detailed in Chapter 6 &
replicated here, except for the following table) are captured below.

Item 10GBase-R Regmode 10GBase-R (Arria 10) 10GBase-R (Stratix 10)

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ED Clock domain 322MHz 156.25MHz/312.5MH 156.25MHz/312.5 MHz

freq

ED Clock domain PHY rx/tx_clkout new PLL that generate The PLL that generates
source 156.25MHz & 312.5MHz 156.25MHz & 312.5MHz

Adapter instantiated AVMM interface XGMII interface XGMII interface

in MAC

12.1 Software and Hardware Requirement

Altera uses the following software and hardware to test the Example Design and testbench in Linux
platform.

 Quartus Prime.
 System Console. The user guide can be found at link:
http://www.altera.com/literature/ug/ug_system_console.pdf
 Simulators: Modelsim-AE, Modelsim-SE, NCsim or VCS (for complete simulators revision please refer
to link-TBD).
 Hardware:
o Arria 10 FPGA Development Kit (device: 10AX115S4F45I3SGE2).
o Stratix 10 FPGA Development Kit (device: TBD)
 Clock control

12.2 Feature

The Example Design offers the following features:

• Support
o single channel 10 Gigabits per second (Gbps) with Arria 10 Native PHY.
o Dual channel 10 Gbps with Stratix 10 Native Phy
• Provide packet monitoring system on transmit and receive paths and report Ethernet MAC statistics
counter for transmit and receive data paths.
• Support testing using different types of Ethernet packet transfer.

The top level diagram of the ED is as shown below.

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Figure: Arria 10 ED

The figures 4.2 is modified as follows to arrive at the above figure.

 Keep only one channel removing ‘address_decoder_multi_channel’.
 Replace the name ‘altera_eth_multi_channel’ with the top name ‘altera_eth_top’ and the
related connections.
 Remove MDIO and the related connections.
 The fpll is removed as it is meant for 1G operation.

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Figure: S10 ED

To Do (Done): Provide a top level diagram of the Example Design.

Example Design Components

Component Description
Low Latency Ethernet 10G MAC Ethernet MAC IP core
Native PHY Native PHY IP with 10G BASE-R
Address Decoder Address decoder module for each components
Reset Controller Reset module which handle reset sequence for
the native PHY
Arria 10/Stratix 10 ATX PLL Generates a TX serial clock for Arria 10/Stratix
10G transceiver
Adapter Convert 32-bit Avalon ST interface to 64-bit and
vice versa
FIFO Avalon Streaming (Avalon ST) single clock & dual
clock FIFO that buffers the receive & transmit
data between the MAC and client

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12.3 Clocking
The following diagram in the section 11.4 captures the clocks and their frequencies in the example
design.

12.4 Reset

The following diagram shows the clocking and reset scheme for the Example Design. At the top-level of
the design, there are two external clock sources, ref_clk_clk (322.265625MHz for Arria 10 and for Stratix
10) and csr_clk (100MHz125MHz) and one master reset, master_reset_n. The master reset is
asynchronous and active low reset signal. This reset signal is then synced to different clock domain
internally. When the master_reset_n is asserted, it brings down all modules in the Example Design.

Figure 11.1 : Arria 10 Clock and Reset Scheme Diagram

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Figure 11.2 : Stratix 10 Clock and Reset Scheme Diagram

12.5 Parameter Setting

12.5.1 Example Design Parameters

Parameter 10GBase-R Register Mode

IP Parameters
Speed 10G
Datapath options Tx & Rx
Enable ECC on memory blocks uncheck
Enable preamble pass-through mode uncheck
Enable priority-based flow control (PFC) uncheck
Number of PFC queues Don’t care
Enable unidirectional feature uncheck
Enable 10GBASE-R register mode unchecked
Enable supplementary address User input
Enable statistics collection checked
Statistics counters User input
Enable time stamping uncheck
Enable PTP one-step clock support Don’t care
Timestamp fingerprint width Don’t care
Time Of Day Format Don’t care

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Use legacy XGMII interface checked

Use legacy Avalon Memory-Mapped interface uncheck
Use legacy Avalon Streaming interface uncheck
Example Design Parameters
Specific Number of Channels 1 (Arria 10)
2 (Stratix 10)

12.5.2 PHY Pre-Set Parameters

The Example Design is using Arria 10/Stratix 10 Native PHY with a pre-set PHY parameter setting that
matches the pairing with LL10GE-MAC IP.

Phy Parameter 10GBase-R

Expanded name Abbreviated name
base_device NIGHTFURY5ES3
(Arria 10)
Nadder (Stratix
10)
TX channel bonding mode bonded_mode not_bonded
Number of CDR reference cdr_refclk_cnt 1
clocks
Selected CDR reference cdr_refclk_select 0
clock
Number of data channels channels 1 (Arria 10)/2 (Stratix 10)
design_environment NATIVE
device 10AX115S3F45E2SGE3
(Arria 10)
ND_MINIDEV_40_PART1
(Stratix 10)
device_family Arria 10/ Stratix
10
Tranceiver mode duplex_mode duplex
enable_hard_reset 0
enable_hip 0
enable_parallel_loopbac 0
k
Enable enable_port_krfec_rx_en 0
krfec_rx_enh_frame port h_frame
Enable enable_port_krfec_rx_en 0
krfec_rx_enh_frame_diag h_frame_diag_status
_status port
Enable enable_port_krfec_tx_en 0
krfec_tx_enh_frame port h_frame
Enable pipe_rx_polarity enable_port_pipe_rx_pol 0
port arity
Enable rx_enh_bitslip enable_port_rx_enh_bits 0
port lip
Enable rx_enh_blk_lock enable_port_rx_enh_blk_ 1
port lock
Enable enable_port_rx_enh_clr_ 0

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rx_enh_clr_errblk_count errblk_count
port
Enable enable_port_rx_enh_crc3 0
port_rx_enh_crc32_err 2_err
port
Enable enable_port_rx_enh_data 1
rx_enh_data_valid port _valid
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_align_clr _align_clr
port (Interlaken)
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_align_val _align_val
port (Interlaken)
Enable rx_enh_fifo_cnt enable_port_rx_enh_fifo 0
port _cnt
Enable rx_enh_fifo_del enable_port_rx_enh_fifo 1
port(10GBASE-R) _del
Enable enable_port_rx_enh_fifo 1
rx_enh_fifo_empty port _empty
Enable rx_enh_fifo_full enable_port_rx_enh_fifo 1
port _full
Enable enable_port_rx_enh_fifo 1
rx_enh_fifo_insert _insert
port(10GBASE-R)
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_pempty port _pempty
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_pfull port _pfull
Enable enable_port_rx_enh_fifo 0
rx_enh_fifo_rd_en port _rd_en
Enable rx_enh_frame enable_port_rx_enh_fram 0
port e
Enable enable_port_rx_enh_fram 0
rx_enh_frame_diag_statu e_diag_status
s port
Enable enable_port_rx_enh_fram 0
rx_enh_frame_lock port e_lock
Enable rx_enh_highber enable_port_rx_enh_high 1
port ber
Enable enable_port_rx_enh_high 0
rx_enh_highber_clr_cnt ber_clr_cnt
port
Enable enable_port_rx_is_locke 1
rx_is_lockedtodata port dtodata
Enable enable_port_rx_is_locke 1
rx_is_lockedtoref port dtoref
Enable rx_pma_clkout enable_port_rx_pma_clko 0
port ut
Enable rx_pma_clkslip enable_port_rx_pma_clks 0
port lip
Enable enable_port_rx_pma_div_ 1
rx_pma_div_clkout port clkout

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Enable enable_port_rx_pma_iqtx 0
rx_pma_iqtxrx_clkout rx_clkout
port
Enable enable_port_rx_pma_qpen 0
rx_pma_qpenable_port_rx able_port_rx_polinv
_polinv port
Enable rx_pma_qpipulldn enable_port_rx_pma_qpip 0
port (QPI) ulldn
lpbken 0
Enable rx_seriallpbken port enable_port_rx_seriallp 0
bken_tx
Enable rx_signaldetect enable_port_rx_signalde 0
port tect
Enable enable_port_rx_std_bitr 0
rx_std_bitrev_ena port ev_ena
Enable rx_std_bitslip enable_port_rx_std_bits 0
port lip
Enable enable_port_rx_std_bits 0
rx_std_bitslipboundarys lipboundarysel
el port
Enable enable_port_rx_std_byte 0
rx_std_byterev_ena port rev_ena
Enable rx_std_pcfifo_empty port enable_port_rx_std_pcfi 0
fo_empty
Enable rx_std_pcfifo_full port enable_port_rx_std_pcfi 0
fo_full
Enable enable_port_rx_std_rmfi 0
rx_std_rmfifo_empty fo_empty
port
Enable enable_port_rx_std_rmfi 0
rx_std_rmfifo_full port fo_full
Enable enable_port_rx_std_sign 0
rx_std_signaldetect aldetect
port
Enable enable_port_rx_std_wa_a 0
rx_std_wa_a1a2size port 1a2size
Enable enable_port_rx_std_wa_p 0
rx_std_wa_patternalign atternalign
port
Enable tx_enh_bitslip enable_port_tx_enh_bits 0
port lip
Enable tx_enh_fifo_cnt enable_port_tx_enh_fifo 0
port _cnt
Enable enable_port_tx_enh_fifo 1
tx_enh_fifo_empty port _empty
Enable tx_enh_fifo_full enable_port_tx_enh_fifo 1
port _full
Enable enable_port_tx_enh_fifo 1
tx_enh_fifo_pempty port _pempty
Enable enable_port_tx_enh_fifo 1
tx_enh_fifo_pfull port _pfull
Enable tx_enh_frame enable_port_tx_enh_fram 0

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port e
Enable enable_port_tx_enh_fram 0
tx_enh_frame_burst_en e_burst_en
port
Enable enable_port_tx_enh_fram 0
tx_enh_frame_diag_statu e_diag_status
s port
Enable tx_pma_clkout port enable_port_tx_pma_clko 0
ut
Enable tx_pma_div_clkout port enable_port_tx_pma_div_ 1
clkout
Enable tx_pma_elecidle port enable_port_tx_pma_elec 0
idle
Enable enable_port_tx_pma_iqtx 0
tx_pma_iqtxrx_clkout rx_clkout
port
Enable tx_pma_qpipulldn port enable_port_tx_pma_qpip 0
(QPI) ulldn
Enable tx_pma_qpipullup port enable_port_tx_pma_qpip 0
(QPI) ullup
Enable tx_pma_rxfound port (QPI) enable_port_tx_pma_rxfo 0
und
Enable tx_pma_txdetectrx port enable_port_tx_pma_txde 0
(QPI) tectrx
Enable tx_polinv port enable_port_tx_polinv 0
Enable enable_port_tx_std_bits 0
tx_std_bitslipboundarys lipboundarysel
el port
Enable tx_std_pcfifo_empty port enable_port_tx_std_pcfi 0
fo_empty
Enable tx_std_pcfifo_full port enable_port_tx_std_pcfi 0
fo_full
Enable enable_ports_adaptation 0
enable_ports_pipe_g3_an 0
alog
enable_ports_pipe_hclk 0
enable_ports_pipe_rx_el 0
ecidle
enable_ports_pipe_sw 0
Enable enable_ports_rx_manual_ 0
rx_set_locktodata and cdr_mode
rx_set_locktoref ports
enable_ports_rx_manual_ 0
ppm
Enable PRBS verifier enable_ports_rx_prbs 0
control and status
ports
enable_rx_pma_floatingt 0
ap
Enable simplified data enable_simple_interface 1
interface

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enable_split_interface 0
enable_transparent_pcs 0
Enable ‘Enhanced PCS’ enh_low_latency_enable 0
low latency mode
Enhanced PCS/PMA enh_pcs_pma_width 32
interface width
FPGA fabric/ Enhanced enh_pld_pcs_width 66
PCS interface width
Enable Rx 64b/66b enh_rx_64b66b_enable 1
decoder
Enable Rx data bitslip enh_rx_bitslip_enable 0
Enable Rx block enh_rx_blksync_enable 1
synchronizer
Enable Interlaken RX enh_rx_crcchk_enable 0
CRC-32 checker
Enable Rx descrambler enh_rx_descram_enable 1
(10Gbase-R/Interlaken)
Enable Interlaken Rx enh_rx_dispchk_enable 0
disparity checker
Enable Interlaken frame enh_rx_frmsync_enable 0
synchronizer
Frame Synchronizer meta enh_rx_frmsync_mfrm_len 2048
frame length gth
Enable Rx KR-FEC error enh_rx_krfec_err_mark_e 0
marking nable
Error marking type enh_rx_krfec_err_mark_t 10G
ype
Enable Rx data polarity enh_rx_polinv_enable 0
inversion
Enable RX FIFO enh_rxfifo_align_del 0
alignment word deletion
(Interlaken)
Enable RX FIFO control enh_rxfifo_control_del 0
word deletion
(Interlaken)
Rx FIFO mode enh_rxfifo_mode 10GBase-R
Rx FIFO partially empty enh_rxfifo_pempty 2
threshold
Rx FIFO partially full enh_rxfifo_pfull 23
threshold
Enable Rx/Tx FIFO enh_rxtxfifo_double_wid 0
double width mode th
Enable Tx 64b/66b enh_tx_64b66b_enable 1
encoder
Enable Tx data bitslip enh_tx_bitslip_enable 0
Enable Interlaken Tx enh_tx_crcerr_enable 0
CRC-32 generator error
insertion
Enable Interlaken Tx enh_tx_crcgen_enable 0
CRC-32 generator
Enable Interlaken Tx enh_tx_dispgen_enable 0
disparity generator

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Enable frame generator enh_tx_frmgen_burst_ena 0

burst control ble
Enable Interlaken frame enh_tx_frmgen_enable 0
generator
Frame generator meta enh_tx_frmgen_mfrm_leng 2048
frame length th
Enable KR-FEC Tx error enh_tx_krfec_burst_err_ 0
insertion enable
KR-FEC Tx error enh_tx_krfec_burst_err_ 1
insertion spacing len
Enable Tx data polarity enh_tx_polinv_enable 0
inversion
Enable Interlaken Tx enh_tx_randomdispbit_en 0
Random disparity bit able
Enable Tx-scrambler enh_tx_scram_enable 1
(10Gbase-R, Interlaken)
Tx-scrambler enh_tx_scram_seed 288230376151711743
seed(10Gbase-R,
Interlaken)
Enable Tx Sync header enh_tx_sh_err 0
error insertion
Tx FIFO mode enh_txfifo_mode Phase compensation
Tx FIFO partially empty enh_txfifo_pempty 2
threshold
Tx FIFO partially full enh_txfifo_pfull 11
threshold
generate_add_hdl_instan 0
ce_example
Generate parameter generate_docs 1
documentation file
Message level for rule message_level error
violations
number_physical_bonding 1
_clocks
pcie_rate_match Bypass
Actual PCS Tx Channel pcs_bonding_master 0
bonding master
pcs_direct_width 8
Initial Tx PLL clock pll_select 0
input selection
Number of Tx PLL clock plls 1
inputs per channel
PMA configuration rules pma_mode basic
Tranceiver protocol_mode teng_baser_mode
configuration rules
rapid_validate 0
Enable dynamic rcfg_enable 1
reconfiguration
Configuration file rcfg_file_prefix
prefix
Generate C header file rcfg_h_file_enable 0
Enable datapath and rcfg_iface_enable 0

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interface
reconfiguration
Enable Altera Debug rcfg_jtag_enable 0
master endpoint
Generate MIF (Memory rcfg_mif_file_enable 0
Initialization File)
Enable multiple rcfg_multi_enable 0
reconfiguration files
Number of rcfg_profile_cnt 2
reconfiguration
profiles
Reconfiguration Profile rcfg_profile_data0
0
Reconfiguration Profile rcfg_profile_data1
1
Reconfiguration Profile rcfg_profile_data2
2
Reconfiguration Profile rcfg_profile_data3
3
Reconfiguration Profile rcfg_profile_data4
4
Reconfiguration Profile rcfg_profile_data5
5
Reconfiguration Profile rcfg_profile_data6
6
Reconfiguration Profile rcfg_profile_data7
7
Selected rcfg_profile_select 1
reconfiguration profile
Generate reduced rcfg_reduced_files_enab 0
reconfiguration files le
Share reconfiguration rcfg_shared 0
interface
Generate SystemVerilog rcfg_sv_file_enable 0
package file
CTLE adaptation mode rx_pma_ctle_adaptation_ manual
mode
DFE adaptation mode rx_pma_dfe_adaptation_m disabled
ode
Number of fixed dfe rx_pma_dfe_fixed_taps 3
taps
Rx_pma_div_clkout rx_pma_div_clkout_divid 2
division factor er
PPM detector threshold rx_ppm_detect_threshold 1000
Enable capability set_capability_reg_enab 0
registers le
Selected CDR reference set_cdr_refclk_freq 322.265625MHz
clock frequency (Arria 10)/
644.53125MHz
(Stratix 10)
Enable control and set_csr_soft_logic_enab 0
status registers le

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Data rate set_data_rate 10312.5

set_embedded_debug_enab 0
le
set_enable_calibration 0
Enable ODI acceleration set_odi_soft_logic_enab 0
logic le
set_hip_cal_en 0
PCS Tx channel bonding set_pcs_bonding_master Auto
master
Enable PRBS soft set_prbs_soft_logic_ena 0
accumulators ble
Enable embedded Set_rcfg_emb_strm_enabl 0
reconfiguration e
streamer
Set user-defined IP set_user_identifier 0
identifier
std_low_latency_bypass_ 0
enable
Standard PCS / PMA interface std_pcs_pma_width 10
width
Enable RX 8B/10B decoder std_rx_8b10b_enable 0
std_rx_bitrev_enable 0
RX byte deserializer mode std_rx_byte_deser_mode Disabled
std_rx_byterev_enable 0
RX FIFO mode std_rx_pcfifo_mode low_latency
std_rx_polinv_enable 0
RX rate match FIFO mode std_rx_rmfifo_mode disabled
RX rate match insert / delete -ve std_rx_rmfifo_pattern_n 0
pattern (hex)
RX rate match insert / delete +ve std_rx_rmfifo_pattern_p 0
pattern (hex)
std_rx_word_aligner_fas 0
t_sync_status_enable
RX word aligner mode std_rx_word_aligner_mod bitslip
e
RX word aligner pattern (hex) std_rx_word_aligner_pat 0
tern
RX word aligner pattern length std_rx_word_aligner_pat 7
tern_len
std_rx_word_aligner_ren 3
umber
std_rx_word_aligner_rgn 3
umber
std_rx_word_aligner_rkn 3
umber
std_rx_word_aligner_rvn 0
umber
Enable TX 8B/10B disparity control std_tx_8b10b_disp_ctrl_ 0
enable
Enable TX 8B/10B encoder std_tx_8b10b_enable 0
std_tx_bitrev_enable 0

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std_tx_bitslip_enable 0
TX byte serializer mode std_tx_byte_ser_mode Disabled mode
std_tx_byterev_enable 0
TX FIFO mode std_tx_pcfifo_mode low_latency
std_tx_polinv_enable 0
support_mode user_mode
TX local clock division factor tx_pma_clk_div 1
tx_pma_div_clkout division factor tx_pma_div_clkout_divid 2
er
validation_rule_select

12.6 Interface Signaling

Signal Direction Width Description

csr_clk input 1 Configuration clock for Avalon-MM
interface. Frequency is 100Mhz125Mhz
csr_rst_n input 1 Reset Avalon-MM interface
core_clk_312 output 1 Clock for fast domain. Frequency is
312.265625MHz
tx_serial_data Output 1 (Arria Serial data transmitted out
10)
2
(Stratix
10)
tx_rst_n input 1 Reset Tx interface
rx_xcvr_clk output 1 Clock for the Rx path. Frequency is
322.265625MHz
rx_serial_data Input 1 (Arria Serial data received.
10)
2
(Stratix
10)
rx_rst_n input 1 Reset Rx interface
core_clk_156 output 1 Clock for slower domain. Frequency is
156.25Mhz
tx_xcvr_half_clk output 1 Synchronous clock derived from
tx_xcvr_clk. Frequency is 161.133Mhz
ref_clk_clk input 1 Referejce clock for Tx PLL. Frequency is
322.265625MHz (Arria 10)/
644.53125MHz (Stratix 10)
csr_write input 1 Assert this signal to request a write
csr_read input 1 Assert this signal to request a read
csr_address input 16 Use this bus to specify the register
address you want to read from or write
to
csr_writedata input 32 Carries the data to be written to the
specified register

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csr_readdata output 32 Carries the data read from the specified

register
csr_waitrequest output 1 Asserted when IP core is busy and not
ready to accept any read or write request
tx_ready_export output 1 Asserted when the native PHY Tx path is
ready to transmit data
rx_ready_export output 1 Asserted when the native PHY Rx path
reset is complete
block_lock output 1 Asserted to indicate that the block
synchronizer has established
synchronization
atx_pll_locked output 1 Asserted when Tx PLL is locked

12.7 Register Mapping

All register space for this example design is 32 bit. The following tables show the address offset for the
Example Design and client logic at the top-level of the design.

Example Design Block Register Map

Byte Offset Block
0x0000_d000 – 0xFFFF_FFFF Client Logic
0x0000_0000 – 0x0000_CFFF Reserved for Altera

Example Design Sub Block Register Map

Byte Offset Block
0x0000_0000 MAC
0x0000_8000 Native PHY
0x0000_9600d600 Tx SC FIFO
0x0000_9400d400 Rx SC FIFO
0x0000_c000 Packet Generator & Checker

Fig: Address map for Arria 10

Example Design Block Register Map

Byte Offset Block
0x0001_d000 – 0xFFFF_FFFF Client Logic
0x0000_0000 – 0x0001_CFFF Reserved for Altera

Example Design Sub Block Register Map – Channel 0

Byte Offset Block
0x0000_0000 MAC
0x0000_8000 Native PHY
0x0000_9600d600 Tx SC FIFO
0x0000_9400d400 Rx SC FIFO
0x0000_c000 Packet Generator & Checker

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Example Design Sub Block Register Map – Channel 1

Byte Offset Block
0x0001_0000 MAC
0x0001_8000 Native PHY
0x0001_9600d600 Tx SC FIFO
0x0001_9400d400 Rx SC FIFO
0x0001_c000 Packet Generator & Checker

Fig: Address map for Stratix 10

12.8 Simulating the Example Design

12.8.1 Simulation Collateral

The following table describes files that implement the Example Design testbench. The collateral can be
found under <Example Design>/simulation/ed_sim/models.

File Description
avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that uses the BFMs to form the
transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to the
DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
tb.sv The top level testbench file of which consists of the Device
Under Test (DUT) and other logic blocks.

12.8.2 Simulation Test Cases

The test cases are included to demonstrate how to change MAC & PHY configuration at 10Gbps
throughput. The test cases are meant for single channel usage of the example design.

Testbench is included in the design example package for simulation verification. Below are the steps to
run the simulation:
1. Download and restore the design example: LL_Ethernet_10G_A10_phy_10GBaser_Register_mode.
2. Launch Modelsim-SE 10.3c and change the directory to
LL_Ethernet_10G_A10_phy_10GBaser_Register_mode\testbench.
3. In the TCL console window, type the below command: tb_run.tcl

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4. At the end of the simulation, Modelsim simulator will generate statistics of transmitted packets and
received packets in the Transcript window. While in the Wave window, the roundtrip latency for serial
loopback is indicated by the measurement cursors that show the time taken to transmit the first data
from Avalon-ST TX interface to be available at Avalon-ST RX interface.

To Do (Done): Details to be added.

12.9 Testing the Example Design in Hardware

12.9.1 Hardware Setup

The following hardware boards are supported for the sample Example Design. For each hardware board,
we provide a predefined pin assignment. The Example Design recommendations require that System
console must be used for controlling the hardware platform and providing User Interface.

Arria 10 TBD Development Board (10AX115S4F45I3SGE2) is used for hardware testing the Arria 10 ED.
Stratix 10 TBD development board is used for hardware testing the Stratix 10 ED.

The following procedure illustrates the board setup for hardware test. (Diagram: To Do)

The design example package comes with pre-generated RTL files that implement a single Ethernet
channel uses the on-board small form factor pluggable plus (SFP+). Below are the steps to perform
hardware test:
1. Download and restore the design example: (refer to the project link above).
2. Launch the Quartus II software and then open the project file, “altera_eth_top.qpf”.
3. Run full compilation for the design example. A “.sof” file will be generated once the compilation is
complete.
4. Configure the FPGA on Arria 10 GX SI Development Board using the generated, “altera_eth_top.sof”
file.
5. After configuration is done, open the Clock Control tool, “ClockControl.exe”. The Clock Control tool is
shipped with the “Installation Kit” for Arria 10 GX SI Development Board.
6. Set the new frequency for Y5 and Y6 as following: Y5= 322.265625 MHz; Y6= 100MHz125MHz

7. Press User Push Button S1 to reset the system.

Note: System must be hard reset after configuration done.
8. On Quartus II Tools menu, click on System Debugging Tools and then launch System
Console.
9. In the System Console command shell, change the directory to
“LL_Ethernet_10G_A10_phy_10GBaser_Register_mode/script”.
10. Perform the following test by running the command in the System Console command shell:

a. SFP+ loopback
Command:
i. source gen_conf.tcl (Generate and send 0xffff2000 packets)

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ii. source monitor_conf.tcl (To check the number of good and bad packets received)
iii. source show_stats.tcl (To show the statistics counter values)
b. Avalon-ST loopback
Command: source loopback_conf.tcl (enable Avalon-ST loopback)

12.9.2 Timing Closure

Example Design component’s timing constraints will be automatically loaded during Quartus
compilation. Example Design level timing constraints can be found at <Example
Design>/altera_eth_top.sdc.

12.9.3 SignalTap Signaling

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13 Functional Description: 10M/100M/1G/2.5G/10GbE MAC + PHY

example design

This document describes the 10M/100M/1G/2.5G/10GbE MAC + PHY reference design for Stratix 10, the
testbench, and its components.

13.1 Software and Hardware Requirements

Altera uses the following hardware and software to test the 10M/100M/1G/2.5G/10GbE MAC + PHY
reference design and testbench:

■ Intel Quartus Prime Pro Edition 17.1 Build 143

■ Stratix 10 SI Development Board (device: 1SG280LU3F50E3VGS1)
■ ModelSim-SE 10.5c

13.2 Features

This reference design contains pre-generated RTL files which support 2-channels. You can use the
testbench and simulation script provided to simulate the design in a simulator.

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13.2.1 High Level Block Diagram

Figure 7 .1 in shows the block diagram of the design example.

alt_mge_rd_addrdec_mch

.
. .
alt_mge_channel

alt_mge_channel

S LL MAC
Avalon-ST
.
..
…

PHY
Avalon- Avalon- S10 Interface
S PHY
S MM M
Master
MM
...

XCVR
S Reset
S AVMM Mux Controller
S XCVR
Reconfig

10G 2.5G
1G
ATX ATX
FPLL
XCVR PLL PLL
S
Reconfig

Reset 10G Input 1G Input

Clock Clock

Figure 13.17: 10M/100M/1G/2.5G/10G Ethernet reference design block diagram

13.3 Clocking Scheme

The following diagram shows the clocking scheme of the reference design.

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Figure 13.2: Clocking scheme of the reference design

13.4 Reset Scheme

Figure 13.3 Reset scheme of reference design

There is an active high asynchronous global reset signal at reference design top level (alt_mge_rd).
Internal reset signals will be synchronized to respective clock domain internally, and generated by
Transceiver Reset Controller as shown in Figure 7 .33.

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13.5 Generation Flow with parameter setting

13.5.1 Using the design example

The design example package comes with pre-generated RTL files for 2 channels. To use the reference
design, perform the following steps:
…

1. Launch the Quartus II software, and launch Low Latency Ethernet 10G MAC from IP Catalog.
This will launch in Qsys Pro.
2. Go to Example Design tab, select the preset 10M/100M/1G/2.5G/10G Ethernet Example
Design from the Presets windows, and click Apply.
3. Click Generate Example Design…. Once finished, exit Qsys Pro without saving.
4. Open the project file altera_eth_top.qpf from directory

alt_em10g32_0_EXAMPLE_DESIGN/LL10G_1G_2_5G_10G/.

5. Click Start Compilation on the Processing menu to compile the design example.

13.5.2 Changing the number of channels

In order to change the number of channels, modify the “NUM_OF_CHANNEL” parameter of

alt_mge_top for Quartus II compilation flow (or alt_mge_rd for simulation flow).

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13.5.3 Regenerate IP files when upgrade to new version of ACDS

The following table shows the IP that need regeneration and the tools involved.

IP Tools IP File Location

1G/2.5/10GbE MAC IP Catalog rtl/mac/alt_mgbaset_mac.ip
1G/2.5/10GbE PHY with IP Catalog rtl/phy/alt_mgbaset_phy.ip
SGMII enabled
Transceiver Reset Controller IP Catalog rtl/xcvr_reset_controller/alt_mge_xcvr_reset_ctrl_channel.ip
for Channel
Transceiver TX PLL for 10 IP Catalog rtl/pll_atxpll/alt_mge_xcvr_atx_pll_10g.ip
GbE
Transceiver TX PLL for 2.5 IP Catalog rtl/pll_atxpll /alt_mge_xcvr_atx_pll_2p5g.ip
GbE
Transceiver TX PLL for 1 IP Catalog rtl/pll_fpll/alt_mge_xcvr_fpll_1g.ip
GbE
PLL for MAC and User Logic IP Catalog rtl/pll_fpll/alt_mge_core_pll.ip
Avalon-MM JTAG Master IP Catalog rtl/jtag_avalon_master/alt_jtag_csr_master.ip
Address Decoder IP Catalog rtl/address_decoder/alt_mge_rd_addrdec_mch.ip

Launch the tool and open the IP file as shown in the above table to regenerate the IP.

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13.6 Interface Signals

This section describes the interface signals at design example level, which is alt_mge_rd.

N: This is the number of channels parameter (NUM_OF_CHANNEL) set by user.

Some of the signals bus width is determined by NUM_OF_CHANNEL parameter.

13.6.1 Clock and Reset Signals

Signal Direction Width Description

csr_clk Input 1 Configuration clock for Avalon-MM
interface and transceiver reset controller.
The clock runs at 125MHz.
mac_clk Input 1 Clock for the MAC internal logic running at
32-bit interfaces. Its frequency is 312.5
MHz, and must have 0 ppm frequency
difference with refclk.
mac64b_clk Input 1 Clock for the MAC and Avalon-ST logic
running at 64-bit interfaces. Its frequency is
156.25 MHz, and must have 0 ppm
frequency difference with refclk.
refclk_10g Input 1 Reference clock for the 10G TX PLLs. Its
frequency is 644.53125 MHz.
refclk_1g2p5g Input 1 Reference clock for the 1G and 2.5G TX
PLLs. Its frequency is 125 MHz.
rx_pma_clkout Output 1 Recovered clock from CDR
reset Input 1 To reset the whole reference design.
Asynchronous and active high signal.
tx_digitalreset Output [N] Asynchronous active high reset signal for
TX data path of user logic.
rx_digitalreset Output [N] Asynchronous active high reset signal for
RX data path of user logic.

13.6.2 Avalon-MM Interface Signals

13.6.2.1 Ethernet MAC

Signal Direction Width Description

csr_mac_write Input [N] Assert this signal to request a write.
csr_mac_read Input [N] Assert this signal to request a read.
csr_mac_address Input [N][10] Use this bus to specify the register address
you want to read from or write to.
csr_mac_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_mac_readdata Output [N][32] Carries the data read from the specified
register.

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csr_mac_waitrequest Output [N] When asserted, this signal indicates that

the IP core is busy and not ready to accept
any read or write requests.

13.6.2.2 Ethernet PHY

Signal Direction Width Description

csr_phy_write Input [N] Assert this signal to request a write.
csr_phy_read Input [N] Assert this signal to request a read.
csr_phy_address Input [N][11] Use this bus to specify the register address
you want to read from or write to.
csr_phy_writedata Input [N][32] Carries the data to be written to the
specified register.
csr_phy_readdata Output [N][32] Carries the data read from the specified
register.
csr_phy_waitrequest Output [N] When asserted, this signal indicates that
the IP core is busy and not ready to accept
any read or write requests.

13.6.2.3 1G/2.5G/10G Ethernet Reconfiguration

Signal Direction Width Description

csr_rcfg_write Input 1 Assert this signal to request a write.
csr_rcfg_read Input 1 Assert this signal to request a read.
csr_rcfg_address Input 2 Use this bus to specify the register address
you want to read from or write to.
csr_rcfg_writedata Input 32 Carries the data to be written to the
specified register.
csr_rcfg_readdata Output 32 Carries the data read from the specified
register.

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13.6.3 Avalon-ST Interface Signals

Signal Direction Width Description

avalon_st_tx_startofpacket Input [N]
avalon_st_tx_endofpacket Input [N]
avalon_st_tx_valid Input [N]
avalon_st_tx_ready Output [N]
avalon_st_tx_data Input [N][64]
avalon_st_tx_empty Input [N][3]
avalon_st_tx_error Input [N]
avalon_st_rx_startofpacket Output [N]
avalon_st_rx_endofpacket Output [N] Refer to Low Latency Ethernet
avalon_st_rx_valid Output [N] 10G MAC User Guide, in section
avalon_st_rx_ready Input [N] 5-5 and 5-9, under “Avalon-ST
avalon_st_rx_data Output [N][64] Data Interfaces” and “Avalon-ST
avalon_st_rx_empty Output [N][3] Status Interfaces”
avalon_st_rx_error Output [N][6]
avalon_st_tx_status_valid Output [N]
avalon_st_tx_status_data Output [N][40]
avalon_st_tx_status_error Output [N][7]
avalon_st_rx_status_valid Output [N]
avalon_st_rx_status_data Output [N][40]
avalon_st_rx_status_error Output [N][7]
avalon_st_pause_data Input [N][2]

13.6.4 PHY Interface Signals

Signal Direction Width Description

rx_serial_data Input [N]
tx_serial_data Output [N]
Refer to 1G/2.5G/5G/10G Multi-rate
led_link Output [N]
led_panel_link
Ethernet PHY User Guide, in section 3,
Output [N]
led_char_err Output [N] under “1G/2.5G/10G Ethernet PHY
led_disp_err Output [N] Interface Signals”
led_an Output [N]
rx_block_lock Output [N]
channel_tx_ready Output [N] This signal is asserted when the channel TX
data path is ready for data transmission.
channel_rx_ready Output [N] This signal is asserted when the channel RX
data path is ready for data transmission.

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13.7 Register Map

An address decoder module is provided in the reference design which is instantiated in simulation
testbench and hardware testing Quartus II project for demonstration purpose.

Table 1 .1 shows the address offsets in the 1G/2.5/10G Ethernet Reference Design.

Block/
Sub-block Address Offset Comments

1G/2.5/10G 0x00_0000
Ethernet
Reconfiguration

Channel-0 0x01_0000

1G/2.5/10GbE 0x0000
MAC

1G/2.5/10GbE 0x8000
PHY

Native PHY Rcfg 0xA000

Channel-1 0x02_0000

1G/2.5/10GbE 0x0000
MAC

1G/2.5/10GbE 0x8000
PHY

Native PHY Rcfg 0xA000

Traffic Controller 0x10_0000

Table 13.23: Address Offset of Reference Design

13.7.1 1G/2.5/10G Ethernet Reconfiguration Controller

Table 1 .2, Table 1 .3, Table 1 .4 shows the register offset and bit offset of 1G/2.5/10G Ethernet
Reconfiguration Controller.

Word Offset Register Name Access Reset Value Descriptions

0x00 logical_channel_number RW 0x000 [9:0] Logical
number of the

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reconfig
controller block

Write has no
effect when
reconfig is busy.
0x01 control RW Refer to table Control
below reconfiguration
process
0x02 status RO Refer to table Indicates status
below of
reconfiguration
process
0x03 Reserved - - -
Table 13.24: Register Offset of 1G/2.5/10G Ethernet Reconfiguration Controller

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Bit Register Name Access Reset Value Descriptions

[1:0] speed_select RW 0x00 Select the
operating speed
of the transceiver
to be
reconfigured to.

2’b00:
10M/100M/1GbE
2’b01: 2.5GbE
2’b10: Reserved
2’b11: 10GbE

Write has no
effect when
reconfig is busy.
[15:2] Reserved - 0x0000 -
16 reconfig_start RWC 0x0 When its value is
0, write 1 to start
reconfiguration
process.

Self-cleared
when
reconfiguration is
completed.

Write has no
effect when
reconfig is busy.
[31:17] Reserved - 0x000000 -
Table 13.25: Bit Offset of Control Register

Bit Register Name Access Reset Value Descriptions

0 reconfig_busy RO 0x0 Indicates
reconfiguration
is in progress
and busy.
Table 13.26: Bit Offset of Status Register

13.7.2 MAC

For register map and detail explanation of the register usage, refer to Low Latency Ethernet 10G MAC
User Guide, in section 4, under “Configuration Registers”.

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13.7.3 PHY

For register map and detail explanation of the register usage, refer to 1G/2.5G/5G/10G Multi-rate
Ethernet PHY User Guide, in section 4, under “1G/2.5/10G Ethernet PHY Configuration Registers”.

13.8 Simulating the example design Testbench

Altera provides testbench for you to demonstrate the behavior of 10M/100M/1G/2.5/10G Ethernet
Reference Design. The following sections describe the testbench, its components, and use.

13.8.1 Simulation Collateral

13.8.1.1 Testbench Block Diagram

The testbench operates in loopback mode. Figure 1 .4 shows the flow of the packets in the design
example.

Figure 13.5: Testbench Block Diagram

13.8.1.2 Testbench Components

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The testbench comprise the following modules:

 Device under test (DUT)—the design example.
 Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit
and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-
MM interfaces of the design example components.
 Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the
simulator console.

13.8.1.3 Testbench Files

The <project directory>/simulation/ed_sim/models directory contains the testbench files.

Table 1 .5 describes the files that implement the reference design testbench.

File Name Description

avalon_bfm_wrapper.sv A wrapper for the Avalon BFMs that the avalon_driver.sv file
uses.
avalon_driver.sv A SystemVerilog HDL driver that utilizes the BFMs to exercise
the transmit and receive path, and access the Avalon-MM
interface.
avalon_if_params_pkg.sv A SystemVerilog HDL testbench that contains parameters to
configure the BFMs. Because the configuration is specific to
the DUT, you must not change the contents of this file.
avalon_st_eth_packet_monitor.sv A SystemVerilog HDL testbench that monitors the Avalon-ST
transmit and receive interfaces.
default_test_params_pkg.sv A SystemVerilog HDL package that contains the default
parameter settings of the testbench.
eth_mac_frame.sv A SystemVerilog HDL class that defines the Ethernet frames.
The avalon_driver.sv file uses this class.
eth_register_map_params_pkg.sv A SystemVerilog HDL package that maps addresses to the
Avalon-MM control registers.
gen_sim_script.sh A script to generate simulation scripts required for simulators.
Execute this script if IP cores are regenerated.
tb_testcase.sv A SystemVerilog HDL testbench file that controls the flow of
the testbench.
tb_top.sv The top-level testbench file. This file includes the reference
design (alt_mge_rd), which is the device under test (DUT), a
client packet generator, and a client packet monitor along
with other logic blocks.
Table 13.27: Testbench Files

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13.8.2 Test Cases

Test cases are included to show case how to change channel speed to 10M/100M/1G/2.5G/10G and
MAC configuration.

13.8.2.1 Reconfigure PHY Speed

By default, the 1G/2.5G/10G PHY with SGMII enabled is operating in 10GbE mode. In order to switch the
transceiver operating speed from 10GbE to 10M/100M/1GbE and 2.5G or vice versa, user need to
perform following steps to instruct 1G/2.5G/10G Ethernet Reconfiguration Controller to reconfigure the
PHY.

1. Read from status register to ensure reconfig_busy bit is 0.

2. Write to logical_channel_number register to select the channel to be reconfigured.
3. Write the selected operating speed to speed_select and 1 to reconfig_start bit of control
register.
4. The reconfig_busy bit of status register will be read as 1 during reconfiguration process.
5. Then reconfiguration process is completed when the reconfig_busy bit is read as 0.
6. Transceiver reset sequence will be triggered automatically when the reconfiguration is
completed.

To swith speed to 10M or 100M, user need to switch transceiver operating speed to 1G mode first using
reconfiguration controller. Then, by using CSR reconfiguration, user configure PHY_IF_MODE register of
the PHY to the desired speed.

13.8.2.2 MIF File

MIF files for transceiver reconfiguration will be generated by 1G/2.5G/10G PHY according to Error:
Reference source not found.

Operating MIF Files

Mode
1GbE rtl/reconfig/alt_mge_rcfg_xcvr_1g.mif
2.5GbE rtl/reconfig/alt_mge_rcfg_xcvr_2p5g.mif
10GbE rtl/reconfig/alt_mge_rcfg_xcvr_10g.mif

Table 13.28: Transceiver Reconfiguration MIF Files

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13.8.2.3 Testcase 1

Configuration:

1. 2 channels
2. Circular loopback (as shown in diagram in Figure 1 .4)

Test Scenario:

1. Design start up with channel configured to 10G Ethernet mode.

2. Do basic MAC configuration and PHY speed configuration for all 2 channels.
3. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.
4. Send 3 different type of packets:
a. 64-byte packet
b. 1518-byte packet
c. 100-byte packet
5. Repeat step 2 to 4 for 2.5G, 1G, 100M and 10M Ethernet mode.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window.
The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all
packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal
to the TX MAC statistics counters.

13.9 Testing the ED in hardware

<To be updated by Validation Team>

13.9.1 Hardware setup

13.9.1.1 Hardware Testing: Multi Gigabit Ethernet (MGE) 1G/2.5G/10G with SGMII Enabled
Hardware testing will be carryout in reference design level with the following
environment setting in Stratix 10 family. The following equipment/tools are needed to
carry out hardware testing:
o FPGA Dev. Kit:
 Stratix 10 Si Dev Kit for Stratix 10 testing
o Cables:
 SMA cable
 SFP+
 Fiber Optic cable
o 3rd Party Tester:
 Spirent Test Center and LSI mission board for 2.5G testing
 SmartBit for 1G testing

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13.9.1.2 DUT Implementation with LSI Mission Board

The DUT is represented by LSI Mission board together with a development board shown
in Figure with 2.5G system image programmed into a development board. The framework
is illustrated in Figure . The board is a universal development board, but none of the other
components is used. The test flow is stimulus will be pumped into the DUT by the Spirent
Testcenter and later will return back to the testcenter.

Avalon-MM
Control Interface

DUT 2.5G SYSTEM

Pipeline Bridge

Spirent Testcenter LSI 2.5-Gbps 2.5-Gbps

Avalon-ST Dual-Clock FIFOs
Mission Board Ethernet PHY Ethernet MAC

Figure 10.5: DUT Implementation with LSI Mission Board

13.9.1.3 Hardware Testing: Test Procedure

Follow these steps to test the design examples in hardware:

3. Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 10G 80000000

Parameter Valid Values Description

channel 0, 1 The channel number to test.
speed 10M, 100M, 1G, The PHY speed.
2.5G, 10G
burst_size An integer value The number of packets to generate for the test

4. When the test is completed, observe the output displayed. The following diagrams
show excerpts of the output, which shows that the packet monitor block receives
the same number of packets generated without error, and the TX and RX statistics
counters.

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TEST_INFO: 10G board trace Loopback Test

CONFIGURE CHANNEL 1
Configure to 10G
Setting up mac with a basic working config
Setting 0xC5C4 into rxmac primary address Reg-1
Setting 0xC3C2C1C0 into rxmac primary address Reg-0
Enabling: crc insertion in tx mac
Enabling: pad and crc stripping in rx mac
Setting 1518 into rxmac max frame length
Setting 1518 into txmac max frame length
Clearing mac stats registers
Select std ethernet traffic controller
Disable Avalon ST Loopback

====================================================================================
B E G I N C O N F I G U R A T I O N

====================================================================================
payload length = variable (random) ....
payload bytes = random bytes ....
burst size = 80000000 ....
payload length = 1518 ....
frame source addres field = F0F1F2F3F4F5 ....
frame destination addres field = C5C4C3C2C1C0 ....
reseting monitor Packet Counters
number of Packets Expected By Monitor = 0x4c4b400
burst being injected into device ....
-- MONITOR processing frames received .....

-- MONITOR Received Packet# 16449027]

-- MONITOR Received Packet# 32852616]

-- MONITOR Received Packet# 49623544]

-- MONITOR Received Packet# 65916989]

-- MONITOR Received Packet# 80000000]

-- DONE! - monitor received all expected sum of packets .....

_______________________________________________________________________________________

-- (MONITOR) GOOD PKTS RECEIVED = 80000000

-- (MONITOR) BAD PKTS RECEIVED = 0
-- (MONITOR) BYTES RECEIVED = 51127220644
-- (MONITOR) CYCLES USED = 6638745226
-- (MONITOR) THROUGHPUT CALCULATED = 9.63 Gbps
-- (MONITOR) RXBYTECNT_LO32 = 3882580399
-- (MONITOR) RXBYTECNT_HI32 = 11
-- (MONITOR) RXCYCLCNT_LO32 = 2343777931
-- (MONITOR) RXCYCLCNT_HI32 = 1

_______________________________________________________________________________________

======================================================================
| MAC TX STATS REGISTER CHECK
======================================================================
|# FRAMES_RECEIVED_WITH_ERROR = 0
|# UNICAST_FRAMES_WITH_ERROR = 0
|# MULTICAST_FRAMES_RECEIVED_WITH_ERROR = 0
|# BRDCAST_FRAMES_WITH_ERROR = 0
|# FRAMES_RECEIVED_WITH_ONLY_CRCERROR = 0
|# VALID_LENGTH_FRAMES_WITH_CRC_ERROR = 0
|# JABBER_FRAMES = 0

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|# FRAGMENTED_FRAMES = 0
|# INVALID_FRAMES_RECEIVED = 0
|# FRAMES_RECEIVED_GOOD = 80000000
|# PAUSE_FRAMES_RECEIVED = 0
|# UNICAST_CONTROL_FRAMES = 0
|# MULTICAST_CONTROL_FRAMES = 0
|# UNICAST_FRAMES_RECEIVED_GOOD = 0
|# MULTICAST_FRAMES_RECEIVED_GOOD = 80000000
|# BRDCAST_FRAMES_GOOD = 0
|# DATA_AND_PADDING_OCTETS_RECEIVED_GOOD = 2825321541
|# COMPREHENSICE_OCTETS_RECEIVED = 4265321541
|# FRAMES_WITH_SIZE_64_BYTES = 3190250
|# FRAMES_BETWEEN_SIZE_64AND127_BYTES = 4966646
|# FRAMES_BETWEEN_SIZE_128AND255_BYTES = 10106109
|# FRAMES_BETWEEN_SIZE_256AND511_BYTES = 19843321
|# FRAMES_BETWEEN_SIZE_512AND1K_BYTES = 22624769
|# FRAMES_BETWEEN_SIZE_1KND1518_BYTES = 19268905
======================================================================
| MAC RX STATS REGISTER CHECK
======================================================================
|# FRAMES_RECEIVED_WITH_ERROR = 0
|# UNICAST_FRAMES_WITH_ERROR = 0
|# MULTICAST_FRAMES_RECEIVED_WITH_ERROR = 0
|# BRDCAST_FRAMES_WITH_ERROR = 0
|# FRAMES_RECEIVED_WITH_ONLY_CRCERROR = 0
|# VALID_LENGTH_FRAMES_WITH_CRC_ERROR = 0
|# JABBER_FRAMES = 0
|# FRAGMENTED_FRAMES = 0
|# INVALID_FRAMES_RECEIVED = 0
|# FRAMES_RECEIVED_GOOD = 80000000
|# PAUSE_FRAMES_RECEIVED = 0
|# UNICAST_CONTROL_FRAMES = 0
|# MULTICAST_CONTROL_FRAMES = 0
|# UNICAST_FRAMES_RECEIVED_GOOD = 0
|# MULTICAST_FRAMES_RECEIVED_GOOD = 80000000
|# BRDCAST_FRAMES_GOOD = 0
|# DATA_AND_PADDING_OCTETS_RECEIVED_GOOD = 2825321541
|# COMPREHENSICE_OCTETS_RECEIVED = 4265321541
|# FRAMES_WITH_SIZE_64_BYTES = 3190250
|# FRAMES_BETWEEN_SIZE_64AND127_BYTES = 4966646
|# FRAMES_BETWEEN_SIZE_128AND255_BYTES = 10106109
|# FRAMES_BETWEEN_SIZE_256AND511_BYTES = 19843321
|# FRAMES_BETWEEN_SIZE_512AND1K_BYTES = 22624769
|# FRAMES_BETWEEN_SIZE_1KND1518_BYTES = 19268905
|# FRAMES_BETWEEN_SIZE_ABOVE1519_BYTES = 0

13.9.2 Timing closure

13.9.3 SingalTap signaling

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14 Example Design Components

14.1 Mac IP

14.2 Phy IP

14.3 Xcvr Reset Controller

14.4 PLLs

14.5 Pattern Generator & Checker

14.6 Avn-MM Address Decoder

14.7 FIFO

14.8 32-64 Bit Adaptor

14.9 Jtag to Avn-MM Block

14.10 Reset Synchronizer

14.11 MIDO

14.12 1588 Components

15 Example Design HW.TCL Packaging

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15.1 HW.TCL Approach

Current ED HW.TCL packaging is taking the left side approach considering resource/schedule constraint
towards ACDS-15.1 delivery. The 5 Example Design variants are maintained independently with no
centralization of common blocks.

For long run efficient maintenance with increasing Example Design variants along the path, collateral
consolidation is a must. Advisable effort as soon as @ ACDS-16.0.

15.2 Internal ED Packaging Collaterals Organization

Perforce directory structure:

 alt_em1032
o 1588
o example_design
 LL10G_Ethernet_A10_10GBASER_RedMode
 LL10G_Ethernet_A10_1G_10G_LINESIDE
 LL10G_Ethernet_A10_1G_10G_LINESIDE_1588v2
 LL10G_Ethernet_A10_1G_2_5G
 LL10G_Ethernet_A10_1G_2_5G_10G
 LL10G_Ethernet_A10_1G_2_5G_1588v2
 LL10G_Ethernet_A10_LINESIDE
 LL10G_Ethernet_A10_LINESIDE_1588v2
o MAC

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 adapters
 altera_eth_avalon_mm_adapter
 altera_eth_avalon_st_adapter
 altera_eth_xgmii_data_format_adapter
 altera_eth_xgmii_width_adaptor
 csr
 presets (store example design presets here)
 rtl
 example design hw_tcl files

All the example design source files will be resided in example design folder. Each example design will
have their own folder to store all the source codes.

Generally the folder structure will be split to 4 big sections:

 top level related files(.qpf,.qsf,sdc)
 rtl (all the rtl related files will keep in here. Either qsys file or Verilog files)
o address_decoder
o eth_traffic_controller
o fifo
o jtag_avalon_master
o mac
o phy
o pll
o and misc
 simulation
o ed_sim
 cadence
 mentor
 models
 synopsys
 hwtesting
o system_console

From here it showed that each example design will contain a set of testbench files, a set of rtl and
hardware tests tcl scripts. Arrangement like this will is easier to see clearly which file is belong to which
design, and if we want to do customization. But this is troublesome in term of maintenances. Certain
files that under simulation folder and hwtesting folder are the same. if happen those files need to be
change, then we need to change in every example design. Hence the potential improvement in 16.0 is to
merge those file in common directory.

15.2.1.1 Simulating Design Example Testbench

Simulation script uses QUARTUS_ROOTDIR environment variable to access Altera’s simulation model
libraries. QUARTUS_ROOTDIR should has been set and pointed to the Quartus II installation path after
proper installation. You need to set it manually if this environment variable is missing.

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15.2.1.1.1 Using Simulator

To use the ModelSim simulator to simulate the testbench design, follow these steps:

7. Change directory to <project directory>/testbench/mentor/

8. Launch ModelSim, run the following command to set up the required libraries, to compile the
generated IP Functional simulation model, and to exercise the simulation model with the
provided testbench:
 do tb_run.tcl

15.3 Future improvement for ED packaging

One way to improve maintenance effort is to merge the simulation and hwtesting files.

 example_design
o hwtesting
o simulation
o LL10G_Ethernet_A10_10GBASER_RegMode
o LL10G_Ethernet_A10_1G_10G_LINESIDE
o …

Under hwtesting, few project are actually sharing the same system console script, just maybe few files
are differences, hence we can consolidate them. While for those files that are difference, we can
consolidate all the top level of testbench in single file, then using terp to put different contents based on
the variant selected. Or we append the top level tetbench file like this
LL10G_Ethernet_A10_10GBASER_RegMode_tb_top_n_1588.sv then during generation process, we
modify the file name to become tb_top_n_1588.sv.

Summary:

 Same file of content put in to the common folder

 Different content either using terp to select content of generated files based on variant
 Or append the variant name on the file, then during generation process, modify the file name

Same ideas are apply for simulation as well.

I do not think having the options to configure PHY is a good idea. It makes the example design selection
become more complex and less benefit for customer. Because MAC and PHY and depend on each other.
Changing PHY will change MAC as well. Hence we might just let MAC as entrance point, change MAC and
we will automatic select proper PHY options that are proven working.

I also do not think that using compose hw_tcl is suitable in this case. This is because our example design
is far more complex compare with last time. For example, last time we connect MAC + PHY + FIFO and
generate that to customer. But then now the design we need to generate MAC + PHY + FIFO + reset

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controller + PLL + generator and checker + address decoder. Hence the effort to maintain compose
hw_tcl in this case becoming more difficult compare with existing example design.

Hence I think the focus to 16.0 project should be focus more on how to make the example design more
easy to maintain instead of more rich features.

16 Example Design Timing Closure

16.1 Example Design Timing Closure Approach

7/10 seeds passing with 80% resource utilization.

Timing closure up to 12 channels for ACDS-15.1.
Device speed grade = 3

16.2 Example Design Constraints

Example Design component’s timing constraints will be automatically loaded during Quartus
compilation. Only Example Design constraints are maintained by Example Design engineering team.

Provide description/explanation on timing constraints at Example Design level.

Provide any key note that users should pay attention on closing timing at Example Design level.

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17 Appendix
17.1 Example Design Quick Start Sample

17.2 Engineering Development Contact

Rep Name Email

IPD Penang Director King Seng Hu kshu@altera.com
IP Manager Arul Paniandi apaniand@altera.com
IPSVA Manager Jin Keat Lim jklim@altera.com
Validation Lead Hung Chiew Khor HCKHOR@altera.com
IP Functional Specification Jien Hau Ng jhng@altera.com
IP Verification Testplan Hung Chiew Khor HCKHOR@altera.com
ED Functional Specification Chandra Mallela smallela@altera.com
Kean Harn Lim kehlim@altera.com
ED Testplan Kean Harn Lim kehlim@altera.com
HW.TCL Packaging Chee Keat Kee ckkee@altera.com
Engineers Si Xing Saw sxsaw@altera.com
Soon Chye Chan SCCHAN@altera.com

17.3 Opens & Assumptions

Item Opens Status

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18 Change Log

Release Scope Category Date Item # Description

Example Device
Design Supported
IP Config.
Supported
Known
Limitations
Misc.

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