Department of Electrical Engineering

Integrated Electronics

Fall 2022

Complex Engineering Problem

Submitted by

i) Riyan Ali Alvi | bsee2067@pieas

ii) Abdul Rehman Al Nasir | bsee2084@pieas

Submitted To: Dr. Haroon ur Rashid

Due: 1/2/2022
 1

Design and Implementation of efficient CMOS

Amplifier
Riyan Ali Alvi
Abdul Rehman Al Nasir

Abstract—This report explains the procedure and consider- 4) Input Common-Mode Signal (VICM ): Vicm is the max-
ations for an attempt to design an efficient op-amp based on imum value of input signal that can be applied when the
CMOS technology. Since the problem statement was an open- inverting and non-inverting terminals of op-amp are shorted.
ended one, the goal was to tend to all major performance
parameters of op-omp and achieve optimization. This report In differential-mode operation it is assumed that both the
highlights the trade-offs between different performance param- transistors are operating in saturation even when only one
eters, and the corresponding design parameters. The design side of the differential pair is conducting the entirety of bias
procedure illustrates how different performance parameters are current.
exchangeable with one another and how a reasonable trade-off 5) Output Voltage Swing (Vo ): The extent of the signal
can be achieved for optimum performance of the circuit.
swing allowed at the output of the op-amp determines the
output voltage swing,
6) Slew Rate: The name refers to the fact that there is a
I. I NTRODUCTION
specific maximum rate of change possible at the output of a
The demand for smaller, high performance and low power real op-amp. This maximum is known as the slew rate (SR)
consumption portable devices is now more than ever. To of the op-amp and is defined as
achieve tighter integration and low power density, the current 
dvo 
design trend is towards low supply voltages, higher operating SR =
dt 
max
speeds and optimized area. CMOS is the dominant technology
for implementation of Very Large Scale Integrated circuits 7) Unity Gain Bandwidth (ft ): The frequency of input
(VLSI) and System on Chip(SoC) applications. The opera- signal at which Avo becomes 1 is called unity gain frequency
tional amplifier is an important circuit building block that (ft ), and the op-amp acts as a unity gain amplifier or a voltage
mainly finds its applications in analog and mixed signal VLSI follower.
circuits. Unlike general purpose op-amps, CMOS op-amps 8) Common Mode Rejection Ratio: The efficacy of a dif-
are designed with specific application in mind and hence ferential amplifier is measured by the degree of its rejection
their performance parameters are designed accordingly. For of common-mode signals in preference to differential signals.
instance, since the op-amps are integrated within the larger IC, This is usually quantified by a measure known as the common-
they usually do not have an interface with the off-chip circuitry mode rejection ratio (CMRR), defined as[1]
via output terminals of the chip. Therefore, they are usually |Ad |
designed to drive small capacitive loads within the IC and CM RR = 20 log10
|ACM |
an output stage is hardly designed. A high-impedance input
stage is also not required due to near infinite input resistance Where Ad is differential gain and ACM is common-mode gain.
of MOSFETs. 9) PSRR: The PSRR is defined as the ratio of the amplifier
It is assumed that the reader has a good understanding of differential gain to the gain experienced by a change in the
CMOS technology and working of operational amplifiers. power-supply voltage (VDD and VSS ). For circuits utilizing
two power supplies, we define[2]
vo
A. Performance Parameters A+ ≡
vdd
A brief introduction to performance parameters of op-amps vo
A− =
is given below. vss
1) DC Voltage Gain (A): The DC voltage gain is the open- Mixed signal IC chips combine analog and digital circuits. In
loop voltage gain of op-amp for differential signals, at low such circuits, the switching activity in the digital portion usu-
frequencies. ally results in increased ripple on the power supplies. A portion
2) Input Resistance (Rin ): It is the input resistance as seen of the supply ripple can make its way to the op-amp output
by the signal at input terminals of op-amp. It is infinite in case and thus corrupt the output signal. The traditional approach
of MOS implementation. for reducing supply ripple by connecting large capacitances
3) Output Resistance (Ro ): Rout is the series Thevenin between the supply rails and ground is not viable in IC design,
resistance of op-amp. Since a CMOS op-amp is not used as such capacitances would consume most of the chip area.
to drive heavy resistive loads, this characteristic is not much Instead, the analog IC designer has to pay attention to another
desirable. op-amp specification ,the power-supply rejection ratio (PSRR).
 2

B. Choice of Circuit Configurations[3] voltage −VSS or to a more precise negative voltage reference
op-amps are mostly intended to be used in negative feedback if one is available in the same integrated circuit.
configurations. The second gain stage consists of the common-source tran-
If op-amp introduces an additional phase shift of 180 at sistor Q6 and its current-source load Q7 . The second stage
some frequency, the op-may become unstable. The negative also provides a voltage gain, in addition, it takes part in the
feedback that was intended becomes positive at that fre- process of frequency compensating the op-amp. Capacitor Cc
quency. If the phase shift is 180 deg at unity gain frequency, is included to ensure stability when the op-amp is used with
Barkhausen’s criterion for sustained oscillations gets satisfied feedback. Because Cc is between the input and the output
and the op-amp does not act as an amplifier but as a latch of the high-gain second stage, it is often called a Miller
or oscillator. Therefore, op-amps are usually designed with capacitance since its effective capacitive load on the first stage
at most two gain stages since each stage contains a high is larger than its physical value.[3]
impedance node and contributes a significant pole to op-amp
transfer function. Since phase shift from one pole approaches 2) Telescopic Cascoded Topology: The voltage gain ob-
−90 deg asymptotically, an op-amp with a maximum of two tained from the two-stage op-amp may not provide suffi-
poles cannot introduce a phase shift of 180 deg that is required cient accuracy for many applications in closed-loop gain. To
to convert the negative feedback into positive feedback. increase the voltage, gain without adding another common-
Because of capacitances associated with devices in op-amp, source stage, common-gate transistors can be added. Figure 2
the voltage gain decreases at high frequencies. To obtain a illustrates the use of cascodes to increase the overall voltage
linear fall-off of -6dB/octave, extra capacitance is introduced gain.
called compensation capacitance. This ensures that there is a
significant phase margin at 0dB frequency so that the op-amp
does not oscillate when connected in negative feedback.
Some popular MOS op-amp configurations are briefly intro-
duced below. Some even more advanced configurations include
the active-cascoded op-amps and wide swing current mirrors,
which have not been discussed.

Fig. 2. Telescopic Cascoded op-amp

Fig. 1. Two Stage CMOS op-amp

1) Basic two stage topology: This is the basic two-stage

CMOS topology. The circuit consists of two gain stages: Another potential advantage of telescopic cascode op-amps
The first stage is formed by the differential pair Q1 –Q2 is that they can be designed so that the signal variations are
together with its current-mirror load Q3 –Q4 . This differential- entirely handled by the fastest-polarity transistors in a given
amplifier circuit provides a high voltage gain, as well as process.
performing conversion from differential to single-ended form In addition to the poor common-mode input range, another
while providing a reasonably high common-mode rejection disadvantage is that the output swing in small.
ratio (CMRR).
The differential pair is biased by current source Q5 , which is
one of the two output transistors of the current mirror formed 3) Folded Cascoded Topology: An improvement over tele-
by Q8 , Q5 , and Q7 . The current mirror is fed by a reference scopic configuration is the folded-cascode configuration. The
current IREF , which can be generated by simply connecting a cascodes in Figure 3 are said to folded in the sense that it
precision resistor (external to the chip) to the negative supply reverses the direction of the signal flow back toward ground.[4]
 3

B. Circuit Configuration
The basic two stage circuit configuration for op-amp has
been used in our design. Due to it’s simple and elegant
design it can provide good performance features and easily
be implemented with low area consumption.
The telescopic and folded configurations, although superior
to the basic two stage configuration, are considerably more
complex to design and require more active area on chip.
For instance, in folded configuration, each of the cascoded
transistors require a DC bias voltage at their gate and a bias
current as well. The design of bias circuitry that provides
stable DC bias voltages and current is a separate design issue
that is not the concern of this CEP.

Input Common mode range can be expressed as

Fig. 3. Folded Cascoded op-amp
− VSS + VOV 3 + Vtn − Vtp ≤ VICM
This reversal has two main advantages when used with a ≤ VDD − Vtp − |VOV 1 | − |VOV 5 | (1)
differential pair. First, it increases the output swing. Second,
it increases the common-mode input range. The extent of signal swing allowed at output of op-amp is
given as
C. SPICE Simulation Models −VSS + VOV 6 ≤ vO ≤ VDD − |VOV 7 | (2)
LTspice has possibilities for specifying MOS models of dif-
ferent complexity, including the most basic Shichman-Hodges The input resistance is practically infinite
model (Shichman & Hodges 1968) and several advanced Rin = ∞ (3)
models such as the BSIM models (Sheu et al. 1987) and the
EKV model (Enz & Vittoz 2006). The ‘Help’ function in The first-stage transconductance
LTspice provides an overview of the models.[5] Shichman-
Hodges model has been used for this CEP, since it is very Gm1
simple model that is approximately equal to the model used is equal to the transconductance of each of Q1 and Q2
for hand calculations. The parameters used in these models
have been listed in appendix A. Gm1 = gm1 = gm2 (4)
A model was created for each channel length L, because
The dc gain of the first stage is
the channel length parameter,Lambda, changes with channel
length. 2
−
For n-channel MOSFET |VOV |
For VGS ≥ VT and VDS ≥ VGS − VT A1 =   (5)
1 1
  +
1 W |VA2 | VA4
ID = kn′ (VGS − Vtn )2 (1 + λVDS )
2 L and for second stage is,
For VGS ≥ VT and VDS < VGS − VT −2
 
W VOV 6
ID = kn′ 2
[2 · (VGS − Vtn )VD − VDS ] A2 =  (6)
L

1 1
+
For p-channel MOSFET VA6 VA7
For VGS ≤ VT and VDS ≤ VGS − VT
  second-stage transconductance Gm2 is given by
1 W
ID = kp′ (VGS − Vtp )2 (1 + λVDS ) Gm2 = gm6 (7)
2 L
For VGS ≤ VT and VDS > VGS − VT Unless properly designed, the CMOS op-amp circuit of 1 can
exhibit a Systematic Output DC Offset Voltage.The systematic
 
W
ID = kp′ 2
[2 · (VGS − Vtp )VD − VDS ] dc offset can be eliminated by sizing the transistors so as to
L
satisfy the following constraint:
II. D ESIGN C ONSIDERATIONS W

W


L 6 L 7
A. Process Node W

=2 W

(8)
Since we used LEVEL-1(SH) models, the fabrication tech- L 4 L 5

nology we selected was 0.5 µm because the accuracy of The CMRR of the two-stage op-amp of Fig.1 is determined
LEVEL-1 SPICE models is very low for channels in nm scale. by the first stage.
 4

Where RSS is the output resistance of the bias current source A. High Frequency Response
Q5 , to satisfy inequality (17,)
CM RR = [gm1 (ro2 ||ro4 )][2gm3 RSS ] (9)
I = ID6 (18)
Capacitance C2 represents the total capacitance between the
output node of the op-amp and Cc is compensation capacitance and setting I, while keeping maximum power dissipation in
view
C2 = Cdb6 + Cdb7 + Cgd7 + CL (10)
I = 100µA
Gm1 Gm2
< (11) Setting ft
CC C2
fT = 25M Hz
Gm1 < Gm2 (12)
by equ.(13) SR comes out as,
A simple relationship exists between the unity-gain bandwidth
ft and the slew rate SR. SR = 62.5V /µs
I
SR = = 2πfT VOV 1 (13) equ.(13) gives compensating capacitor,
Cc
For op-amp in Fig.1 PSSR is given as Cc = 1.6pF

Ad
P SRR− ≡ = gm1 (ro2 ||ro4 )gm6 ro6 (14) B. Aspect Ratios
A−
Since equ.(18) implies that currents in Q5 and Q7 are the
C. NMOS or PMOS for input stage? same.  
1 W
A higher slew rate is obtained by operating Q1 and Q2 at 100 = × 68 × 0.22 ×
2 L 5,7
a larger VOV . Now, for a given bias current I, a larger VOV
is obtained if Q1 and Q2 are p-channel devices. This is an  
W
important reason for using p-channel rather than n-channel = 73.5
L 5,7
devices in the first stage of the CMOS op-amp. Another
reason is that it allows the second stage to employ an n- For Q5 and Q1,2 ,
channel device. Now, since n-channel devices have greater
transconductances than corresponding p-channel devices, Gm2 ID5 = 2ID1,2
will be high, resulting in a higher second-pole frequency and a    
W W
correspondingly higher ωt . However, the price paid for these Kp‘ V 2
= 2Kp‘
V2
improvements is a lower Gm 1 and hence a lower dc gain. L 5 OV 5 L 1,2 OV 1,2
[6][7] W


L 5
W

=8
III. D ESIGN P RODCEDURE L 1,2

Setting Range of VOV for operation of all transistors in this

 
W
design = 9.2
L 1,2
0.2 < VOV < 0.4 (15) For Q5 and Q3,4 ,
equ.(12) implies that, ID5 = 2ID3,4
I ID6
   
W W
<2 Kp‘ 2 ‘
VOV 5 = 2Kp V2
|VOV 1 | |VOV 6 | L 5 L 3,4 OV 3,4
which implies that W


L 5
I < 2ID6 (16) W

= 5.6
L 3,4
VOV 1 > VOV 6 (17)  
W
Satisfying the above inequality (17) as , = 13.1
L 3,4
VOV 1,2 = 0.4, VOV 6 = 0.3
by equ.(8)
W


L 6
W

=2
according to equ.(1),VICM will be maximum for minimum L 4
values of VOV 5 and VOV 3,4 . Therefore,  
W
VOV 5 = 0.2, VOV 3 4 = 0.2 = 26.2
L 4
 5

C. Low Frequency Response F. Power Dissipation

Setting overall DC gain as,
A = 5000V /V PD = 2I × 2VDD
Q6 and Q7 have the largest aspect ratios calculated. To
PD = 0.6mW
minimize device width ,setting channel lengths as,
L6 = L7 = 0.5µm
G. MOSFET Dimensions and Gate-Capacitance Parameters
calculating gain for 2nd stage from equ.(6)
The areas AD and AS and the perimeters PD and PS
−2 need to be specified for SPICE to model the body-junction
A2 =  0.3  capacitances (otherwise, zero capacitances would be assumed).
1 1 The exact values of these geometry parameters depend on
+
20L6 10L7 the actual layout of the device. However, to estimate these
A2 = −22V /V dimensions, we will assume that a metal contact is to be
made to each of the source and drain regions of the MOSFET.
calculating required gain for 1st stage to make total gain of For this purpose, typically, these diffusion regions must be
5000. extended past the end of the channel by at least 2.75 Lmin .
A
A1 = = −230V /V Thus, the minimum area and perimeter of a drain/source
A2
diffusion region with a contact are, respectively[8],
for equ.(5)
AD = AS = 2.75Lmin W (19)
VA = VA2 = VA4 (ro2 = ro4 )
−2 × VA and,
VA = = 96V
0.4 × 2 P D = P S = 2 × 2.75Lmin + W (20)
VA = VAn L1 = VAp L4 = 96
equ.(19) and equ.(20) were used to estimate dimensions of the
96
L4 = = 4.8µm drain/ source regions in our design
20
96
L2 = = 9.6µm IV. R ESULTS OF H AND C ALCULATIONS
10

D. CMRR L(µm) W(µm) W

L
gm ( mA
V
)
Q1 9.6 88.3 9.2 0.25
‘
VAp L5 Q2 9.6 88.3 9.2 0.25
Rss = ro5 = = 50L5 Q3 4.8 62.8 13.1 0.5
VOV 5 Q4 4.8 62.8 13.1 0.5
Q5 0.5 36.75 13.1 1
I Q6 0.5 13.25 26.2 0.67
gm 1 =
VOV 1 Q7 0.5 37.25 74.5 0.4

I
gm 3 =
VOV 3
VA 192 CM RR = 81.6dB
Rss = ro5 = I =
2
I
P SRR = 124.7dB
by equ.(9)
       
I I 10L5 192 PD = 0.6mW
CM RR = · · ·
VOV 1 VOV 3 I I
CM RR = 24000L5 V. SPICE A NALYSIS
Setting CMRR as, Results of SPICE analysis are attached in Appendix B.
CM RR = 81.6dB Small-signal parameters were verified. Equation (11) holds,
therefore there is a phase margin at the output at ft which
L5 = 0.5µm can be observed in fig.(7). The phase at 0dB frequency is
almost −120 deg, lagging behind 180 deg by a phase margin
E. PSRR of 60 deg. The common mode and differential mode gain have
been plotted separately. Slew Rate was estimated by applying
Computing value of PSRR from equ.(14),
a step signal at the input and observing the slope of the output
P SRR = 124.7dB impulse.
 6

VI. D ISCUSSION AND S UMMARY

From the design procedure, it can be concluded that the
performance parameters of two-stage CMOS ampliifer are
determined by following design parameters.
1) Overdrive Voltage at which each transistor is operated
Lower VOV values correspond to larger VICM and Vo .
The DC gain obtained is also high for low VOV values.
However, higher VOV value corresponds to a higher slew
rate and consequently, a larger value of the transition
frequency ft.
2) Channel Length L of each transisor
Larger channel lengths mean larger early voltages which
increases the DC gain, CMRR and PSRR. Larger chan-
nel lenghts also correspond to larger device sizes which
leads to higher MOSFET capacitances and hinders per-
formance at higher frequencies of operation.
3) Bias current I
Power dissipation in op-amp is directly proportional to
the bias current. Slew rate obtained is also higher for
larger values of bias currents and therefore the transition
frequency is also larger correspondingly. As is evident
from above discussions, a designer is presented with
many trade-offs. In particular, selection of VOV and L
decides the trade-off between low-frequency and high-
frequency response of op-amp.
A reasonable trade-off has been tried to achieve betweeen
all parameters for optimum performance. The values of DC
gain and the transition frequency are a clear indication of this
balance in trade-off. An increase in value of one paramter
will come at the cost of reduction in value of the other
paramter. One of major aspects of design was to minimize
the chip area without sacrificing much of the performance
and it was achieved. This was a simple design with it’s
limitations. For improvements in performance paramteters,
more complicated designs are required, some of which have
been briefly discussed in the introduction section.

R EFERENCES
[1] A. S. Sedra, “2.4 difference amplifier,” in Microelectronic
circuits, 7th ed. Oxford University Press, 2021, p. 77.
[2] A. S. Sedra, “13.1.7 power-supply rejection ration,” in
Microelectronic circuits, 7th ed. Oxford University Press,
2021, p. 1008.
[3] A. S. Sedra, “13.1.1 the circuit,” in Microelectronic
circuits, 7th ed. Oxford University Press, 2021, p. 997.
[4] A. S. Sedra, “13.2 the folded cascode cmos op-amp,” in
Microelectronic circuits, 5th ed. Oxford University Press,
2021, p. 1016.
[5] E. Bruun, “Tutorial-3 mos transistors,” in CMOS Inte-
grated Circuit Simulation with LTspice. Bookboon, p. 75.
[6] T. C. Carusone, “6.1.4 n-channel or p-channel,” in Ana-
logue Integrated Circuit Design. Wiley, 1997, p. 252.
[7] P. R. Gray, “6.4 two stage mos op-amps with cascodes,”
in Analysis and design of analog integrated circuits.
Wiley, 2011, p. 438.
[8] A. S. Sedra, “B.1.4 mosfet models,” in Microelectronic
circuits, 7th ed. Oxford University Press, 2021.
 7

A PPENDIX A
VALUES OF MOSFET M ODEL PARAMETERS

TABLE I
VALUES OF THE L EVEL -1 MOSFET M ODEL PARAMETERS FOR 0.5µm CMOS T ECHNOLOGY [8]

0.5µm CMOS Process

NMOS PMOS
LEVEL 1 1
Kp 190e-06 68e-06
LAMBDA 0.1 0.2
GAMMA 0.5 0.45
VTO 0.7 -0.8
PHI 0.8 0.75
TOX 9.50e-09 9.50e-0.9
CJ 5.70e-04 9.30e-04
CJSW 1.20e-10 1.70e-10
MJSW 0.4 0.35
PB 0.9 0.9
CGBO 3.80e-10 3.80e-10
CGDO 4.00e-10 3.50e-10
CGSO 4.00e-10 3.50e-10
 8

A PPENDIX B
C OMPUTER -A IDED A NALYSIS

A. SPICE Schematic

Fig. 4. LTspice Schematic

B. DC Operating Point Analysis

Semiconductor Device Operating Points:

--- MOSFET Transistors ---
Name: m1 m2 m3 m4
Model: pmos-sh-9.6 pmos-sh-9.6 nmos-sh-4.8
Id: 5.06e-05 4.96e-05 5.06e-05 4.96e-05
Vgs: -1.68e+00 7.51e-01 8.99e-01 8.99e-01
Vds: 9.57e-02 2.03e+00 2.83e+00 8.99e-01
Vbs: 4.68e-01 2.40e+00 0.00e+00 0.00e+00
Vth: -8.87e-01 -8.87e-01 7.00e-01 7.00e-01
Vdsat: -8.90e-01 -3.90e-01 1.99e-01 1.99e-01
Gm: 6.00e-05 2.54e-04 5.08e-04 4.99e-04
Gds: 4.99e-04 9.53e-07 4.92e-07 4.92e-07
Gmb: 1.27e-05 5.40e-05 1.42e-04 1.39e-04
Cbd: 1.09e-13 1.09e-13 2.86e-14 4.08e-14
Cbs: 1.05e-13 6.88e-14 5.71e-14 5.71e-14
Cgsov: 3.09e-14 3.09e-14 2.51e-14 2.51e-14
Cgdov: 3.09e-14 3.09e-14 2.51e-14 2.51e-14
Cgbov: 3.65e-15 3.65e-15 1.82e-15 1.82e-15
Cgs: 1.48e-12 0.00e+00 7.30e-13 7.30e-13
Cgd: 1.60e-12 2.05e-12 0.00e+00 0.00e+00
Cgb: 0.00e+00 0.00e+00 0.00e+00 0.00e+00
Fig. 5. Values of the parameters of the MOSFET small signal models based on the DC operating point (bias point)
 9

Name: m5 m6 m7
Model: pmos-sh-0.5 nmos-sh-0.5 pmos-sh-0.5
Id: 1.00e-04 1.00e-04 1.00e-04
Vgs: -6.21e-01 2.83e+00 2.29e+00
Vds: 3.73e-01 1.44e-02 3.29e+00
Vbs: 3.73e-01 0.00e+00 3.29e+00
Vth: -8.00e-01 7.00e-01 -8.00e-01
Vdsat: -1.93e-01 2.13e+00 -1.93e-01
Gm: 1.04e-03 6.77e-05 3.99e-04
Gds: 1.86e-05 1.07e-02 1.86e-05
Gmb: 2.69e-04 2.03e-05 4.16e-04
Cbd: 5.37e-14 1.22e-14 5.37e-14
Cbs: 4.55e-14 1.23e-14 2.57e-14
Cgsov: 1.29e-14 5.30e-15 1.29e-14
Cgdov: 1.29e-14 5.30e-15 1.29e-14
Cgbov: 1.90e-16 1.90e-16 1.90e-16
Cgs: 0.00e+00 1.21e-14 0.00e+00
Cgd: 4.45e-14 1.20e-14 4.45e-14
Cgb: 0.00e+00 0.00e+00 0.00e+00
Fig. 6. Values of the parameters of the MOSFET small signal models based on the DC operating point (bias point)

C. Differential Response

Fig. 7. Differential Input Frequency Response

D. Common Mode Response

Fig. 8. Common Mode Input Frequency Response

 10

E. SlewRate

Fig. 9. Output At high speed Edge

Fig. 10. Slope Measurement