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DLD Lab Report 08

This lab report discusses the design and implementation of an n-bit binary multiplier on an FPGA. It begins with background on binary multiplication and the shift-and-add algorithm. It then demonstrates multiplier circuits using ICs and FPGA for 2x2, 4x2, and 4x3 bit sizes. Verilog code and test benches are provided. The report concludes that the student learned how to design n-cycle double multipliers and analyze/write Verilog code for parallel multipliers to implement on an FPGA.

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Muneeb ahmad
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471 views9 pages

DLD Lab Report 08

This lab report discusses the design and implementation of an n-bit binary multiplier on an FPGA. It begins with background on binary multiplication and the shift-and-add algorithm. It then demonstrates multiplier circuits using ICs and FPGA for 2x2, 4x2, and 4x3 bit sizes. Verilog code and test benches are provided. The report concludes that the student learned how to design n-cycle double multipliers and analyze/write Verilog code for parallel multipliers to implement on an FPGA.

Uploaded by

Muneeb ahmad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Lab report 08
Design and Implementation of 𝒏 − 𝒃𝒊𝒕 Binary Multiplier on
FPGA
1.1-Objective:
In this lab, we will seek how to design 𝑛 − 𝑏𝑖𝑡 binary multiplier and its implementation on
FPGA.
1.2Pre-Lab:
Background Theory:
Binary Multiplier:
Binary multiplier is used to multiply two binary numbers. Multiplication of binary numbers is
performed in the same way as multiplication of decimal numbers. It is build using binary
adders. The common multiplication method is “add and shift” algorithm. If the multiplicand
is 𝑁 − 𝑏𝑖𝑡𝑠 and the Multiplier is 𝑀 − 𝑏𝑖𝑡𝑠 then there is 𝑁 × 𝑀 partial product. AND gates
are used to generate the Partial Products. Note that in binary multiplication, the processes
involve shifting the multiplicand and adding the shifted multiplicand or zero. Each bit of the
multiplier determines whether a 0 is added or a shifter version of the multiplicand (0 implies
zero added, 1 implies shifted multiplicand added). Thus, we can infer a basic shift-and-add
algorithm to implement unsigned binary multiplication.

1.2.1-General Rules for 𝑨 × 𝑩:


• 𝐵:
Multiplicand (𝐾 number of bits)
• 𝐴:
Multiplier ( 𝐽 number of bits)
• Number of AND gates required = 𝐽 × 𝐾
• Number of 𝐾 − 𝑏𝑖𝑡𝑠 Adder(s) required = ( 𝐽 − 1 )
• Number of bits required for product result = 𝐽 + 𝐾

Figure :1.2.2: 2 by 2 Multiplier


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1.2.3-Code for Multiplier 2 by 2:

Figure :1.2.4: - Gate Level code for 2- by -2 Multiplier

1.2.5-Test bench:

Figure :1.2.6: Test Bench for Figure: 1.2.4


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1.2.7-Output:

Figure :1.2.8: Output of Figure:1.2.4

1.3-In lab task 01:


1.3.1-Implement 𝟒 − 𝒃𝒊𝒕 by 𝟐 − 𝒃𝒊𝒕 binary multiplier using ICs
1. Implement 4 − 𝑏𝑖𝑡 by 2 − 𝑏𝑖𝑡 binary multiplier using ICs as shown in Figure 8.2.
2. Use 4 − 𝑏𝑖𝑡 Full Adder IC (7483) and AND gate ICs.
3. Observe the behaviour of a binary Multiplier by choosing different binary numbers
4. and verify the results.
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Figure: 1.3.2: Circuit Diagram of 4 by 2 Multiplier

1.3.3-Implementation on Hardware:
1. Take ICs and fix it in bread board.
2. Connect it with the help of figure :1.3.2.
3. Connect the output of 7483 ICs with lights.
4. Press the start button and run the circuit.
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Figure :1.3.4: Circuit Implementation of 4 by 2 Multiplier on Hardware


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1.4-In-Lab Task 2:
1.4.1-Implement 𝟒 − 𝒃𝒊𝒕 by 𝟑 − 𝒃𝒊𝒕 binary multiplier on FPGA
1. Using Structural model, write a Verilog description of 4 − 𝑏𝑖𝑡 by 3 − 𝑏𝑖𝑡 multiplier.
a. Use 4 − 𝑏𝑖𝑡 Adder module made in Lab7.
2. Site all the inputs 𝐴 and 𝐵 on slide switches and the outputs are observed on LEDs of
Nexys2 board.
3. Implement the design on FPGA and test the behaviour of designed binary Multiplier by
choosing different binary numbers.

Answer:
Code for multiplier 4 by 3: -

Figure: 1.4.2: Gate Level Code for 4 by 3 Multiplier


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1.4.3-Test bench:

Figure: 1.4.4: Test Bench for 4 by 3 Multiplier

1.4.5-Output:

Figure:1.4.6: Output of Figure:1.4.4


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1.5-Post lab tasks


Using Behavioral model, write a Verilog description of parameterized Multiplier:
Make one stimulus for two different parameter values and show the wave forms
results.
Code:

Figure:1.5.1: Behavourial Modeling for 4 by 4 Multiplier

1.5.2: Test Bench:

Figure:1.5.3: Output of Figure: 1.5.1


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Conclusion and discussion: -


Discussion: -

1. From the above discussion we learn.


2. How to apply a multiplier on hardware using ICs.
3. How to code a multiplier in Xilinx.
Proof of the discussion: -
Figure:
Conclusion: -
1. In this lab, I have learned how to plan n-cycle double multiplier and how to analyse a
code for multiplier.
2. Similarly, I have also learned how to compose Verilog code of various parallel multiplier.

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