Syllabus Content: 15.2 Boolean algebra show understanding of Boolean algebra Notes and guidance © understanding of De Morgan's Laws perform Boolean algebra using De Morgan’s Laws © _ simplify a logic circuit/expression using Boolean algebra 15.2 Logic circuits design © produce truth tables for common logic circuits including half adders and full adders © show understanding of flip-flop (SR and JK) Notes and guidance ‘© may include logic gates with more than two inputs 3.3.2 Boolean algebra We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the symbols, below is a quick reminder Bitwise Operator NOT(4) AND(.) OR(+) XOR(®) NanoCtB) NORA + B) Description inver input where exactly two 1s | where one or more 1s where exactly one 1 where less than two 1s. where exactly two 0s Boolean Operations and Expressions “Variable”,"Complement”, and “Literal” are terms used in Boolean Algebra. A variable is a symbol used to represent a logical quantity. Any single variable can have a ”1” or a "0" value The complement is the inverse of a variable and is indicated by a bar over the variable. The complement of a variable is not considered as a different variable. www.majidtahir.com Contact: +923004003666 Email: mafidtahir61@gmail.comEvery occurrence of a variable or its complement is called a Literal. It could be its true form or its complement, both of them are called Literals SUM TERM is the SUM of literals (A+B+C+D) A sum term is equal to 1 if one or all of its inputs are 1, and is equal to 0 only if all of its inputs are zero. A PRODUCT TERM is the PRODUCT of literals (A.B.C.D) A product term is equal to 1 if all of its inputs are 1. And is equal to 0 if any one (or all) of its inputs are zero. Describing Logic Circuits Algebraically: Any logic circuit, no matter how complex, may be completely described using the Boolean operations previously defined. Because the OR gate, AND gate, and NOT gate are the basic building blocks of digital circuits. Boolean algebra provides a concise way to express the operation "NOT" 4. of a logic circuit formed by a combination of logic gates so that the output can be determined for various combinations of input values. : To derive the Boolean expression for a given logic circuit, begin “AND” qT X=AeB=AB at the left most inputs and work towards the final output, writing the expression for each gate. "oR" Laws and Rules of Boolean Algebra: Equivalent and Complement of Boolean Expressions ‘Two given Boolean expressions are said to be equivalent if one of them equals "1” only when the other also equals “1” and same case with “0” They are said to be complement of each other if one expression equals “1” only when the other equals “0” and vice versa. Postulates of Boolean Algebra: The following are the important postulates of Boolean algebra 1. Le. & 2. 1.0=0.1=0 & 3. 0.0=0 & worw.majidtahr.com || Contact: +923004003665 | Email: majidtahir61@gmall.com PH eyo eGTheorems of Boolean algebra Boolean theorems can be useful in simplifying a logic expression. That is, in reducing the number of terms in the expression. It is useful in the sense that the number of gates, are reduced which in turn also reduces heat dissipation from the circuit (saves energy) When this is done, the reduced expression will produce a circuit that is less complex than the one which the original expression would have produced. Rule 1: Commutative Laws ‘ona ans Commutative laws DD Oe | z] ® ad For Multiplication: For Addition: @AB=B.A (i)A+B=B+A Rule 2: Associative Laws: (i) (A.B).C = A.(B.C) (ii) (A+B) + C=A+(B+C) Associative Laws Associative Laws Reece & ne a At(B40) te q ec 6 Bsc (asB)+¢ t ‘i ABC ¢ ¢ © For Addition: X+(Y+Z) = ¥+(Z+X) = Z+(X+Y) © For Multiplication X.(Y.2) = Y.(Z.X) = Z.(XY) wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com aeRule 3: Distributive Laws A(B+C)=AB+AC Distributive law : cy - =| : Y=A(B+O) Y=AB+AC © X.(V4Z) = X.Y +X.Z ® (KY) + (XZ) = X(¥+Z) Operations with ‘0’ and ‘1’ Rule 4: OR Laws: These laws use the OR operation. Therefore they are called as OR laws. © 0+xX=X (5)X+0=X > __»—* © 14x=1 % ()X+1=4 ‘—_»>>—_' (J A+0=A a a. iP : (iii) A+A=A (iv) A+A=1 (yxexe1 * PD AND Laws: ‘These laws usé the AND operation. Therefore they are called as AND laws. x (x*020 5 fj}—> axtex Xp @xx=x *T{>—« @xrxs0 * — ° wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com a ()AO=0 (iJAI=A (iii) AA=A (iv) AA=0Idempotent or Identity Laws: (AA)=A Complementation Law: RULE 6: & xX X*X'=0 ‘>D— RULE 8: - 3 & © X4X=1 aes >pD— v Involution Law / INVERSION law: RULE 9: This law uses the NOT operation. The inversion law states that double inversion of a variable result in the original variable itself. This law states that (X) ‘Truth Table for ¥ = x 0 1 o =H = ofn wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com aeAbsorption Law or Redundancy Law: RULE 10: o X#KY=X RULE 11: . o X#KY = X+Y RULE 12: © (KEY).(K4Z) = X4ZY Explanation of Rule10, Rule 11, Rule12 mute men men AAA AvRe= [Arayiaec)= asec APRB=(A+ a8) 47% (ue | arayarc)=aavacesarec LHS=A+A8 - = (ane As) oR (rue) FASACHBAPEC — [Rue7) zal) a ; TAAtABEAR+RE Ruled) =A(Wo} #84480 mat (rveg es = (Ath (ass) =A1#BA880 {rue} - (rueg : 21. (ass) (rules) =Asbatsc {rue g =RHs ; FA(I#8)+80 =A {rule 4 =A1+BC [Rule 2} =A+BC [Rule 4} Theorem 1: ‘The compliment of the product of 2 variables is equal to the a >> - sum of the compliments of individual variables a4 .. . is equivalent to B - A A Thedrem 2: Kit ‘The compliment of the sum of two variables is equal tothe = -B S product of the compliment of each variable B A+B=A-B ABEA+B wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com aeDeMorgan’s Theorems break! break! 4 a. BB A+B i a A+B AB NAND to Negative-OR NOR to Negative-AND The rules that govern Boolean algebra Commutative Laws ASB=B+A AB=BA Associative Laws A+ (B+()=(A+B)+C (B.C) = (A.8).C Distributive Laws ‘A(B +0) = (A.B) + (A.C) A+ (B.C) =(A+B)(A+0) (A+B)(A4+0) =A+BC ‘Tautology/Idempotent Laws AA=A A+A=A Tautology/Identity Laws ASA O+A=A Tautology/Null Laws OA=0 1+A=1 Tautology/Inverse Laws AA=0 A+A=1 Absorption Laws A(A+B)=A A+ (AB) =A A+AB=A4B De Morgan's Laws (A+B) www.majidtahir.com Contact: 4923004003666 || Email: majidtahir61@gmail.comSyllabus Content: 15.2 Logic gates and circuit design Half Adder: The simplest circuit that can be used for binary addition is the half adder. This can be represented by the diagram in the circuit takes two input bits and outputs a sum bit (S) and a carry bit (C). : tT ) >—— (sum) 1 bit half - adder }——> C (carry) }——> cian With the help of half adder, we can design circuits that are capable of performing simple addition with the help of logic gates. Let us first take a look at the addition of single bits. }— S (sum) INPUTS OUTPUTS A o+0=0 Fai) a a, sB|s fc O+1=1 0 0 0 0 B 140=1 0 1 1 0 Canty 141 = 10 0 i 8 1 1 0 1 These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this problem can be solved with the help of an EXOR Gate, if you do care about the output, the sum result must be re-written as a 2-bit output. wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com‘Thus the above equations can be written as 0+0 = 00 A B S +1 = OL 140 = 01 c 141=10 Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out. INPUTS, “OUTPUTS ‘SUM CARRY, o 1 T o From the equation it is clear that this 1-bit adder can be easily implemented with the help of EXOR Gate for the output ‘SUM’ and an AND Gate for the carry. Take a look at the implementation below. For complex addition, there may be cases when you have to add two 8- bit bytes together. This can be done only with the help of full-adder logic. Full Adder: ‘This type of adder is a little more difficult to implement than a half-adder. The main difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as CIN. The sum shows how we have to deal with CARRY from the previous column. This is why we need to join two half adders together to form a full adder: A S (sum) B | Cn OR ote }———> Cont (carry) wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com a‘The output carry is designated as COUT and the normal output is designated as S. Take a look at the truth-table. [ INPUTS ‘ourPUTS Te | s_| cot Le te fe fare [ro a fo eA es Cel. te fate ys opel] ta bits ‘Thus, we can implement a full adder circuit with the help of two half adder circuits. © The first will half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit shown below. © As with the half adder circuits, different logic gates can be used to produce the full adder circuit. © The full adder is the basic building block for multiple binary additions. For example, Figure below shows how two 4-bit numbers can be summed using four full adder circuits. A 8 A oe 8, A 8B, 4 ie ' www.majidtahir.com _ Contact: +923004003666 Email: majidtahir61@gmail.com 8, full adder |= S ! 5Syllabus Content: oes w understanding of how to construct a flip-flop (SR and JK) as data storage elements Flip-Flop Circuits All of the logic circuits you have encountered up to now are combination circuits (the output depends entirely on the input values). We will now consider a second type of logic circuit, known as a sequential circuit (the output depends on the input value produced from a previous output value). Examples of sequential circuits include flip-flop circuits. This chapter will consider two types of flip-flops: SR flip-flops and JK flip-flops. LL 55S aS a a ‘Combinational circuit: a circuit in which the output is dependent only on the input values ‘Sequential circuit: a circuitin which the output depends on the input values and the previous output SR Flip-Flop The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has two inputs, one which will “SET” the device (meaning the output = "1"), and is labelled S and another which will "RESET" the device (meaning the output = "0"), labelled R. SR flip-flops SR flip-flops consist of tWwo cross-coupled NAND gates (note: they can equally well be produced from NOR¢gates). The two inputs are labelled 'S’ and 'R’, and the two outputs are labelled ‘Q’ and ‘G’ (remember Q is equivalent to NOT Q). The Basic SR Flip-flop We can use SR flip-flop circuitts constructed from both NOR gates or NAND gates, as shown in Figure. www.majidtahircom Contact: +923004003666 Email: majidtahir61@gmail.comHow SR Flip-flop works: We will consider SR-Flip Flip using NOR Gates. We will now consider the truth table to match ur SR flip-flop using the initial states of R = 0, S = 1 and Q = 1. The sequence of the stages in the process is shown in Figure 3 0 4) Q=1 R=0 7 1 (4) Q I [5] Qs yD) 0 Q=0. | Senne] 2161416105 Sat ti] Which ves: Ta To] 1}O;1)0 © We have to start with two inputs given in red colour. ® We can take R = 0 and @ = 0 in First Gate which produces Q=1 _ © when Q=4 and Set S=1 is input in second gate in green colour, it produces Q = 0 ® so in SR Flip-Flop when Set value Q=1, Reset value Q = 0. © 1fs=0 and R=0, No change. Flip Flop will remain in present state as shown below © If S= 1 and R = 1, An invalid condition will happen as Q and Q both have to be opposite to each other which are same in invalid state. © Now consider what happens if we change the value of $ from 1 to 0. © See when R = 0 and § = 0, No change in Output, its same as previous state. 7 0 4) Q=1 oe @ pan oR B) Nocchange. Latch 09 NC NC remained in resent state. to{t io Latch SET. oto 4 Latch RESET. 1 _ fat © | Invalid condition 1] The reader is left to consider the other options which lead to the truth table, Tablebelow, for the flip-flop circuit. wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.comInputs | OUTPUTS | Comment rR |a/a @ Oe () o | 1 | 0 | following s=1 change © 4_|_o | 4 (d) o | 0 | 1 | following R= 1 change ©) 1[olo Explani e| ,R=0,Q=1,9=0 isthe set state in this example e| 1, R= 0,Q=1,Q=0 is the re-set state in this example © S=0,R=1,Q=0,0=1 here the value of Qin line (b) remembers the value of Q from line (a); the value of Q in line (d) remembers the value of Qin line (c) ® s=0,R=0,Q=0,Q=1 R changes from 1 to O-and has no effect on outputs (these values are remembered from line (¢)) @ $=1,R=1,Q=0,0=0 Invalid case since Q should be the (opposite) of Q. © The truth table shows how an input value of S= 0 and R = 0 causes no change to the two output values; S = 0 and R = 1 reverses the two output values; S = 1 and R = 0 always gives Q = 1 and Q = 0 which is the set value. © The truth table shows that SR flip-flops can be used as a storage/memory device for one bit; because a value can be remembered but can also be changed it could be used as a oe “rmponent in a memory device such as a RAM chip. Itis important that the fault condition in line (e) is considered when designing and developing storage/memory devices. The NOR Gate SR Flip-flop Below are SR flip flops with NOR Gates and NAND Gates along with truth tables, also showing invalid state: S (set) = ol R (reset) ol NOR Circuit wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.comThe NAND Gate SR Flip-Flop AAs well as using NOR gates, it's also possible to construct simple one-bit SR Flip-flops using two cross-coupled NAND gates connected in the same configuration. The circuit will work in a similar way to the NOR gate circuit above, except that the inputs are active HIGH and the invalid condition exists when both its inputs are at logic level “1”, and this is shown below. 1 Bicep Se Lea oll*{—]x Q SR Flip-flop Re 4 Hof 1 . a we ° Reresey symbol circuit Wet, 0 =1 then NAND #1 output =0 Truth Table If Q=0 and R= then NAND* 2 output =1 S-1 Set Reset Output normal Q=0 11 No enenge* This.is a consistent,} © 1 Osi stable state, esis | 1 9 G0 Oo 6 Invalid state *can be used for Rel data storage normal © The only difference is that in NOR Gate SR Flip Flop Invalid Condition happens when S=1 and R=1 and No-Change happens when S=0 and R=0 © In NAND Gate SR Flip Flop Invalid Condition happens when S=0 and R=0 and No- Change happens when $=1 and R=1 The SR flip-flop has few problems due to which JK flip-flop has been developed worw.majidtahr.com || Contact: +923004003665 | Email: majidtahir61@gmall.comThe JK flip-flop The SR flip-flop has the following problems: © In addition to the possibility of entering an invalid state there is also the potential for a circuit to arrive in an uncertain state, © If inputs do not arrive quite at the same time, the circuit can become unstable. In order to prevent this, the JK flip-lop has been developed. A circuit may include a clock pulse input to give a better chance of synchronizing inputs and additional gates are added. The addition of the synchronised input gives four possible input conditions to the Jk flop: el @ »0 © »no change ® » toggle (which takes care of the invalid S, R states). The JK flip-flop can be illustrated by the symbol shown in Figure JK flip-flop symbol (left) and JK flip-flop using NAND gates only (right) ‘lock Table below is the simplified truth table for the JK flip-flop. 3 | K | Value of | Value of a | ourPuT before clock | after clock pulse pulse ol o 0 0 is unchanged after clock pulse o | o 1 1 1 0 0 1 Q=1 1 0 1 1 0 1 Oo 0 Q=0 o [4 1 ° vila 0 1 Q value toggles between 0 and 1 1 1 1 0 wwwemajidtahir.com |Contact: +923004003666 Email: majidtahir61@gmall.com© »When J = O and K = 0, there is no change to the output value of Q. © > If the values of J or K change, then the value of Q will be the same as the value of J (Qwill be the value of k). © » When J = 1 and K = 1, the Q-value toggles after each clock pulse, thus preventing illegal ur] ae Clock Q states from occurring (in this case, toggle means the flipflop will change from the ‘Set’ 0 ee a 8 Qunchanged state to the 'Re-set’ state or the other way = : zi round). i ——— o\oa t 0 Lt t Qtoggles ‘Truth table for a 3K flip-flop Use of JK flip-flops » Several JK flip-flops can be used to produce shift registers in @ computer. & » A simple binary counter can be made by linking up several JK flip-flop circuits (this requires the toggle function). References: AS & A level by Silvia Lanafield and Dave Duddell Cambridge International AS & A level by David Watson and Hellen Wiliams (Hodder Education) organizations.htmi https: //www.allaboutcircuits.com/textbook/diital/chpt-7/demorgans-theorem: https: //en. wikipedia.ora/wiki/De Morgan%27s laws htt .electronicshub.ora/boolean-algebra-laws-and-theorems; http://Wwww.electronics-tutorials.ws/sequential/seq_1.html http://www. elprocus.com/half-adder-and-full-adder/ www.majidtahircom Contact: +923004003666 Email: majidtahir61@gmail.com