'previéus chapters, 8051 and PIC microcontrollers were discussed which are primarily for low end applications. Now, discussion on the high end microcontroller ARM is it ‘meant particularly for high end processor was first developed at ACORN Computer Limited of Cambridge, England 7 when the concept of RISC was introduced at Stanford Berkley. ARM Limited was found in 1980 ‘and ARM specializes in the concept of ARM ®, which they have licensed to number of other manufacturers to make a variety of chips ‘Same processor core. (50, now the focus is not on family of processors, but conceptually a CPU architecture in number of different chips intended for embedded applications. The ARM arck tect: but it is not a purely RISC architecture because it has been \ nent of embedded applications. for embedded applications are basically high code density, low power ‘snd smaller silicon footprint. Architecturally ARM satisfies various RISC processors as well.Features of ARM ARM has got lot of interesting features. They are listed below, ARM processor has a large uniform register file. basically a LOAD-STORE architecture, where data processing operati n registers and does not involve any memory operations, 'ONS are on bit processor and also has variants of 16 bit and 8 bit architectur, re are 16 bit and 8 bit variants embedded into a 32 bit processor, Later mmerate about 16 bit and 8 bit variants also called as THUMB and jen ature. i got a very good speed vs power consumption ratio and high code densi ed by embedded applications. 5 ot barrel shifter in the data path, which can maximize the hardware usage le on the chip. : also got auto increment and auto decrement addressing modes to optimize loops; this is not very common with RISC processor. Also ARM su nd STORE of multiple data elements through a single instruction. ‘conditional execution’, where an instruction h maximizes the executio as also got a feature named d only when a condition is being met, whic satures make the ARM more suitable for embedded applications anda RM from other typical RISC processors. dea behind this is the! its e implemented intg of ARM architecture. The whole i number of changes and these variations ar @ distinct identity and number. There are four such 1985] was a processor and 26 bit addressing vwith no mult ly operation “row end RIS sions include 32 bit addressing with multip ishes the ARM from the PIC and other pport only ADD or subtract operation. hanced with the availability of signe pressed form of instruction was introduced. instructions. Version STE-includes sign! .d instructions Versionprove To ARM AROHITROTURS i t to the core data path, This data path is organized in such a way an see ae ra i) fetched Fairs memory, and a basic feature of RISC is that He 2 ae fotchod from registers and not from memory. . Instructions typically use two source rogisters and single result/destination register. The ore interesting facts aro the presence of the ‘barrel shifter’ and the in rement/decrement’ i Jc, The barrel shifter on the data path can preprocess the data before it enters the ALU. It ie basically ‘a combinational circuit that can shift a data bit to the left or to the right by an ~ fhutrary number of positions in the same cycle itself ‘Tho difference from classical shift registers is that the classical shift register involves flipflops and the barrel shifter is available in the shift register where the number of shifts soquires an equivalent number of clocks because, the shifting takes place based on clocks. ‘Whoreas the barrel shifter is made up of a combinational circuit where the shifting takes place < {na singlo attempt itself, In fact, tho shift takes place in the same instruction itself, This is ‘ vory basic enhancement present in the ARM data path. ‘The other interesting feature is the increment and decrement logic which can operate on tho registers that are independent of the ALU. This facilitates the implementation of auto- increment and auto-decrement features in the ARM, where it is used for movement of blocks ‘of data between the memory and registers. 7 é &3 ARM ORGANISATION CORE DATA FLOW MODEL é 2 ee flow diagram (Fig. 6.2) where, the functional units are connected by data buses aa ‘The arrows represent the direction of data flow, and the lines represent the Baath 1@ boxes represent either a storage unit or an operation unit. Figure 6.1 can be = ie reference for clear understanding. The detailed description is given as follows: Bus Architecture All microproce: Biba, ssors have bus as the basic communication unit. Data goes in and : oe 6.2 direction of flow is also represented clearly. ee ‘ tecture has separate memories f Bes ebntat et oven toum wchiote ame scn.memo™ Thi & ei memory is u: ' Rig 61, lata memory. The comparison of these two architectures is ihage Harvard von Neumann136 ANALYSIS OF Instruction Decoder It decodes the instruction before execution is carried out. There are three kinds of j set supported in ARM core. They can be ARM instruction set: Jazelle i y THUMB instruction set. With the CPSR one can set the operation state and instruction set can be selected. Load and Store Architecture Reader needs to please go through the RISC vs CISC discussed at the first chapter. ARM in the RISC category which follows the load and store architecture. Means, with load and architecture in place, registers will be mandatory for processing to be carried out. Wi registers one cannot do any sort of operation with ARM core. ° ARM has 2 source registers Rm and Rn and one destination register which result. The destination register is named as Rd. A and B are the two buses help in reading the source operands. Rm and Rn values will be fetched fro: Barrel shifter is a kind of support which is very useful in association with 4 expression evaluation and address calculation,ee 2 ee | E gp TO ABM ARCHES TURE - 64 ARM REGISTER ORGANISATION \ troller must be having lot of registers as it plays a vital role i a Be es and storage functions. A Tegister is used to store ieee ean aii opera in a simpler way, when two numbers are to be added, the numbers to Hag da i oa. in the mind of the person performing addition. With Tespect to processors, the sy \ the numbers are stored can be called as registers. And the result of the addition van t os stored, that again should be register. All the microprocessors or microcontrollers will have some number of registers, The count may vary from architecture to architecture. This * ame information has been given when the 8051 tegisters were dealt. So, one thing is made iE lear that, ve registers purpose remains the same across the microcontrollers or hy ‘The reader will be now taken through the way the registers are organized in ARM. It is a oe: oe to understand with reference to the following diagrammatic representation shown in Se ay (Stack pointer) °709"=m counter) a “[s|2le[u[sle] a] «| ono] m[aa[na|ae] as int (Link register Fig. 6.3. ARM registers The above diagrammatic representation reveals that there are 13 general purpose registers (1912) available for the programmers to use. They are all referred with a prefix r like, 10, r1 vices means the RAM location and also register. All the registers are 32 bits in their size. what the reader is exposed to in the 8051 architecture, there are some special function : available here as well. They are 13, r14 and r15. Each of these three registers have Specific function being assigned and are summarized below. eee flack pointer (SP, r13): Every microcontroller or a processor will have a stack arca , * temporary storage purpose. And one can access the stack through the stack y Pointer. It is similar to the one reader has gone through in 8051. It will hold the » of the top of the stack. om register (LR, r14): The name itself reveals the story behind the register. When subroutine is called, the return address will be put in here and when the subroutine / is over, this register will be used for fetching the address back from where 0 P “ntrol of execution has been initiated. Be eae ‘Well, reader is already aware of what a PC does. It is born It got no address. The ose of PC is to keep a paper mark. “© where should the control go next ike tise: the address of next instruction cuted will be kept in PC. fe advised that, they should not try using r13, r14 and r15 as general they have all rights to use it as a general purpose register, they Gause effects. Then, reader has some more interesting stuff to read any modes of Operation available in ARM. 7 such modes are identifiedand they are all discus’ special, more privi 6.4.1 Current Program Status Register (CPSR) Expanded as Current Program Status Register, it is one of the most importa Int Fogisters ay with ARM architecture. ‘The following Fig. 6.4 can be referred for getting an idea o; ponents of the same. This is referred to be a ee Will lok | 41 to program status word (PSW) of 8051. One major Ap in the case of PSW is an 8 bit register. The folin The follow what are the com| It can be compare CPSR is a 32 bit register where, is self explanatory with clear notes. T' Zoro flag, Carry flag and Overflow flag. Since there is lot of room for extension, few pi ion, few bi @ kept for future usage or for the moment th Shove are two fields which are meant for interrupt Bee ne ig Dela Fee oe aie tid Te inter tay Roa tore lake tertanet Ell hacia Shorlly. Meanwhile with F one can mask or unmask the FIQ See THUMB field, it helps in enabling or disabling the THUMB mode. With Roe CPSR one can now navigate to the next title on modes of the operation oa = reserved ant sed shortly. The immediate action i loged register called as CPSR. eee 'M something Ps it here are 4 flags supported in the form of Nj legativ Unused/ Reserved i Fe T | Mode Te bo eat ‘is get aed future use Reserved for | Used to mask IRQ interrupts Used to mask FIQ interrupts To select THUMB state, If set ri to 1, THUMBS \s set, else normal ARM mode is seTO ARM ARCHITECTURE _yynoDucTion. 139 65 MODES AND STATES \, 85:1 Modes ya microprocessor or a microcontroller will operate in few modes, ic. it will support modes of operation. Same is the case here. ARM architecture supports two types of modes + on a broad classification. They are privileged and non-privileged mode. The name itself reveals + the story behind the screen. Privileged is powerful mode which has got a wide level of access pert and non-privileged is not so. There are total of seven modes supported with ARM, “Efor tem fl in ether privileged or non-privilged mode. In privileged fart pire ‘ permissions to the CPSR register is full. But, non-privileged mode will not permit this. The . jssions are restricted with respect to non-privileged mode. Modes can be set and ‘ pea ith the mode bits of the CPSR. It is of 5 bits wide. The following are the available " and supported mode of operations in ARM: = « Abort mode, ‘« Fast interrupt request mode, e Interrupt request, ‘© Supervisor mode, From these list of available modes only one mode falls into the category of non-privileged mode. It is an user mode and categorized as an under-privileged mode. Its access permissions are limited and restricted. Rest of the all six modes is coming under privileged mode. Next point to be known is what the responsibility of each of the modes is? '» Abort mode will be entered when there is memory access failure. ‘ Fast interrupt request: Support for interrupt is provided in this mode. * Interrupt request: Support for interrupt is provided in this mode. ‘* Supervisor mode: When the processor goes in for a reset or a restart the mode of Supervisory control will be set. ‘* System mode: This is very much similar to the user mode. Only difference is that, it can have complete access to the CPSR without restrictions. * Undefined mode: When the processor encounters an undefined instruction which is totally not known to the processor, then the undefined mode will be entered. . peme: Used by programmer for programs and applications. Name itself makes the clear on what the mode is meant for. ‘the modes be selected? ts in the CPSR helps the programmer in accomplishing this task. The following the summary of binary values to be loaded into the CPSR mode bits for the System mode, © Undefined mode and : . User mode. StSupervisor Abort Undefined System ters made available for the modes. For an instance if the processor moves to th , the registers r13_abort and r14_abort will be made available along with an These kinds of registers which are available only for a particular mode of op d to be as Banked Registers. What is SPSR? This question is answered sho 112_fiq | r13_fiq Fast interrupt request > Interrupt request mode- TO ARM ARCHITECTURE 141 ri4_sve r13_abt | r14_abt Supervisor Abort SPSR SPSR t3_udt | r14_uf Undefined SPSR Fig. 6.5. ARM mode privileges One example on how the mode switch will happen and how the banked registers will te made available will be very helpful and handy. The following Fig. 6.6 will reveal ideas on how the banked registers will be called when there is a mode change. CPSR is the register that an be used for bringing in this mode change or when there is an interrupt getting raised, the ‘mode change will be initiated. felalelel«[s|=|7 cPSR| User mode ro] mt | 2] aa] aa] 5 ia Abort mode r13_abt|r14_abt ‘SPSR_ABORT Fig. 6.6. ARM mode privileges as So, from the above Fig. 6.5 one can understand that when the abort mode is called, r13 espa are replaced with banked registers 113_abt and r14_abt. Also CPSR is replaced with IR abort. It would be apt for the reader to now understand on what is SPSR. ott is expanded as Saved Program Status Register. It is specially meant for privileged operation, There is an exception here; system mode does not have support for SPSR. Ee modes (privileged) have all support for SPSR. SPSR is used to hold the status of , it is a storage register which can hold the current state of CPSR. 852 States The ; of eine to be scanned and learned is on the states. An ARM core supports three states : m namely, (a) ARM, (b) THUMB and (c) Jazelle, of these states will have their own instruction set and the choice can be made with ‘sual. There is a T bit in the CPSR if that bit is set then, the state of operation is THUMB and THUMB instruction sets will be used for the same. Similarly, the mode ARM is selected. There ARM instruction set is used. Other be useful for ARM mode of operation. Jazelle is a state which1 rr helps in increasing the efficiency of JAVA based . Operations when run ‘1 Jazelle states in place, the operations based on Java would be execu: with Any ict All Jazelle instructions are 8 bit instructions. J bit will be found i Dan of with the co-lagsN,Z, V and C the it willbe avalabe, Basod on yr soo 3X can be selected. An example would help the reador with a clear urgent landin, Example 6.1: From the Fig. 6.7, reader should Convey on what is the : core will be operated on setting the values as shown, ‘Mode that th on mt 8 area, 31 Flag fields SCO a0 bi Unused ; = Reserved 7 [m= Intenupt mask bits 0 Unused/ Soleaisilae 2 o. eee, ' | 1 o | at Fig. 6.7. ARM-CPSR = “ele id 31 Flag fields Solution: Zero flag is set from the flag field. So, result of an ALU operation is zero. jazell set and so is THUMB state since T=0, And hence the state selected is ARM. e value is set as 11111. By taking the table 6.1, it can be understood that the Mode and it is a privileged mode. mnt a lot of time in learning on the registers and allied things, one should pipelining and through pipelining, how one can improve the speed of ex ant. There are many stages of pipelining followed in ARM core. They s of pipelining. Depending on which ARM core is being used, the p mined. One simple relevant example should be given now for the need obvious usage of pipelining. Figure 6.8 is the real life examp! je heard of already. It is a car assembly unit and an engineer is check en a car is being analyzed, the next car to be analyzed or che rent car is checked, the next one will automatically get the att as a pipeline. It saves time by keeping the next car ready wht e that could help here in the better understanding ee stand are in the pipeline and they will get their turn > ; he service request accomplished, Many such examP Toller point of view, there are three stages thatFig. 6.8. A simple pipeline in assembly unit They are listed as follows: * Fetch (fetching the instruction for execution from memory, where there will be pool of instructions, which is nothing but the program or the code written by the programmer.) ‘* Decode (Instruction which is fetched needs to identified on what it is? What is meant for? What kind of operation would it perform? etc. This process is referred to be as decoding and the decode stage does this work.) * Execute (This is like running the code after compilation. Once decoded it is all set to be executed. After the run or execution the result can be moved to the result register Rd as shown the data flow model diagram shown in Fig. 6.2.) ne there is no pipelining architecture followed, what will happen? Reader can following set of instructions in a program which has to be executed. 4A small piece of code with three instructions. Instruction : 1 CMP instruction: 3 SUB Weeder Should remember that there is no pipelining in place and in that case how the lt happen? pip g inf , ? What would be the likely steps involved is represented in the following bs dearly visible from the Fig. 6.9. Instruction CMP has to be fetched first, the @ then it should be executed. Only after the first instruction is execu tion for the second instruction, After second instruction, it will move Ailiout completing the current execution it would be highly impossible it looks fine. What is the problem associated with this way only three instructions. When there is a complex pro144 Instruction : 1 CMP Instruction : 2 ADD Instruction : 3 SUB Fig. 6.9. Execution of instructions step by step in a program and if at all there are 5,000 instructions amount of time it would take to fetch, de execute the entire code would be huge. Performance and speed of the system which to deploy that code will be affected in a massive way. What is the remedial me, can it be solved? Pipeline is the solution. How a pipeline works? Figure 6.9 and s instructions can now be taken as reference and solution has been discussed. Figure refined form of Fig. 6.9. ‘Stage-1 Stage-2 Stage-3 Stage Stage-2 Stages ont a >a ‘Stage-2 Stage-3 ont (at > ‘Stage-1 Stage-2 Stage-3 Cycle 4 Fetch > pee Next instruction from the pool of available instructions Fig. 6.10. Three stages of pipelining in ARM stl e of code with three instructions. cmPbe Sell hore the problom of wastage of time is addre: | ‘on that will go in execution state, ‘There i Ce execution state, That will be the only th Sth tho third instruction should have been fotcl Mons, ; sed, At every cyclo, there will be one €n exception until the first instruction is ime where no instruction will be executed. hod for the first instruction to be moved {o execution state, until the third Instruction SUB has been fetched execution would be on hold for the first instruction CMP. By now reader must have got an idea of what is a peline and how it is helping in increasing the execution speed, ‘The | Jha stage pipoline. Figure 6.11 represonts tho 5-stago Pipeline and ay woll in parallel. ARM 7 follows the 3-stage pipeline and ARM 9 fo ‘architecture. next step is to learn on description for each stage ollows the 5-stage pipeline Fetch: Fetching the instruction for execution from. Memory, where there will be poo! of Instructions, which is nothing but the program or the code writen by the programmer. Decode: Instruction which is fetched needs to Identified on what itis? What is meant for what kind of operation would It perform? etc., this process is referred to be as ‘decoding and the decode stage does this work. Buffer/Memory: ALU result will be buffered for a clock ‘eyele here which can facilitate Pipeline flow for all the instructions, [ree [ dxoe Execute: Result wil be gonerated out of this step. [ ane) [ne ‘Write: Results obtained due to the execution are moved to the registers. Fig, 6.11. Five stage pipeline STINTERRUPTS AND EXCEPTIONS mame asics of what an interrupt is all about and on how interrupt is better than ‘tad tipoe, all dealt in chapter 2 under the section 2.8.3. It would be better if the reader Section 2.7,3 once before proceeding with the current description, Womans co. °*cePtion is getting raised or called the immediate action would be using the SMnier (PC). The following could be the causes for an exception to be raised: * An exception could be raised because of the software code which has purposefully (4 Mt with intention, mn, influence would have raised the exception. of the exception currently raised, another exception may get raised. Operation, an exception could be raised as well.‘operation will be changed based on the “ ; ae ah, exception is refered to be as a link register will have to store yey BO an an exception is called, the return address will be put in fous : execution is over, this register will be used for fetch” 284 Whey Sermeiielcantrol of execution has been initiated. SSE lext to come is the SPSR. SPSR is expanded as Saved Program . 4 ™ specially meant for privileged modes of operation. The CPSRe Sa Register to be stored in the SPSR of the newly set mode. 1e Will hayg. Until the raised exception is handled properly and task is completed, there shoga._ any further interrupts. So disabling the IRQ and FIQ have to be done Thee can be performed by using CPSR register. Reader can closely watch the fol | Fig. 6.12 which reveals the fields of CPSR and with this IRQ and FIQ can be disabled, Interrupt mask bits Unused/ 1 F Reserved Fig. 6.12 CPSR "© Now comes another term called as the vector addressing. Where will the code for exceptions be stored? Which address will be used for the storage? Every exception thas an address and that detail is stored in a table. It is referred to be as vec" addressing, Following table 6.2 has got this details included. TABLE 6.2 Vector addresses 0x00000000 0x00000004 000000008 0x0000000¢ 000000010 000000014" st vector “when the processor is turned on ie., when the power is s ippiled ts Maceo his -yector will be reached and instructions will be run, ‘ ¢ Undefined vector ‘When there is a clumsy instruction that the processor could not decode at all, then this vector will come into play. e Software interrupt vector SW1is an instruction available in the ARM which used to summon OS routine. By the time of usage of SWI, SWI vector will be raised. Prefetch abort vector When there is an access attempt from an address for fetching and instruction without proper privileges and permissions this vector will be in the play. (ie., it happens at fetching stage). Data abort vector When an instruction tries to access a memory area where, instruction has no access permissions, then this vector gets raised. Reserved vector Reserved for future use. © Interrupt request When an external hardware is used for raising an interrupt, this vector is used. * Fast interrupt request Ttis used when a speedy response is expected. For this to be used, FIQs should be kept unmasked. * Program counter (PC) will be now loaded with the pertinent vector addresses and that addresses will contain the perfect piece of code (subroutine). That piece of code will be executed. Figure 6.6 should be referred for an instance now. From that one can understand that, there are bank registers available for the privileged modes and they will be now utilized to store the return value and the stack pointer. How will the return from exception happen? Once the work is over, iMlet from. cps Peloaded with approp Correct previous si What wit, Pani .¢,, the exception is handled, the control has to return back to the place R can be restored with the values from SPSR. Program counter can also riate address, And any register which is modified should be restored to tates, happen if multiple exceptions are getting raised at the same time? C state j ine {s. So ARM has got priorities defined for the exceptions and though many Y sot, a poiting raised at one shot, ARM would not be confused as the priorities are nd a. following table 6.3 can be used for knowing the priority levels. Software re Bet rai undefined instruction exceptions have the same level of priority. But they would Sed at the same time.Fast interrupt request Interrupt request Prefetch abort Software interrupUndefined instruction With all these above details reader can move on to the next area of discussion. 6.8 ARM FAMILY—A COMPARISON ‘There are many processors being released with ARM core like ARM7, ARM9, ARM10, ARMi1 and so on. As the number increases followed by ARM, the features do increase as well with more special attributes. For an example ARMS’s speed will be better than the ARM7 and pipelining would be of a different architecture which would afford a better speed. Here in the following table 6.4, a comparison has been made with the different versions of the processor falling under the ARM roof. TABLE 6.4 Feature comparison ARM? ‘ARMS ARMi0 ARMA | Pipeline Three stage | Five stage | Six stage | Hight stage MHz 80 150 | 260 335 MIPS/MHz 0.97 11 13. 12 Architecture (Harvard/Von Neumann) VN. Harvard Harvard Harvard Multiplier 8*32 8°32 16°32 16°32 KEY POINTS TO REMEMBER © ARM is abbreviation of Acorn Risc Machine. (© ARM is based on RISC architecture. © ARM follows the load and store architecture. © ARM7 follows the von Neumann architecture. © There are total of 16 registers available for the user to access freely. Out o 114 and ri5 are meant for stack pointer, link register and program counter (© There are three states supported by ARM core. ARM, THUMB and JAZELLE. that 113)yyrmonuerion 9 CPSR is to PSW oF o CPSR supp! 9 THUMB state can o Jazelle is a speci 9 SPSR is meant to store the status yeturning from the exception call. o There are sev" « Abort mode Fast interrupt reques «Interrupt request «Supervisor mode © There are two broad user mode all other 6 Pipelining is us © ARM supports multiple stages of pipel in different architectures. © ARM7 supports a three stag © ARM9 supports 5 stage pipe © RESET is the exception with hi 70 ARM ARCHITECTURE. a Current Program Status Register f the 8051 microcontroller. It isa rts Negative, Carry, Overflow a t mode classifications ©! pipeline whic! |, Objective Type A. Slate ‘T’ for True and ‘F’ for False sta 1. ARM has got barrel shifter in the data p: ements: on the chip. 2, Program counter has a unique address value. 3. Modes Modes cannot be set and changed with the mo 4 When the processor encounters an undefined i Processor, then the undefined mode will be en| 5. Th CPSRs current value is stored in the SPSR before entering the newly B + re in the Blanks: As, sic feature of RISC is that operands get fel 2. Bi » Every mi oma a crocontroller or a processor will have a an access the stack through the | state of operation which of the CPSR and it will be used to restore after en modes of operation supportet f modes as privileged and non-privilege Jining which has memory ighest priority. aaa led (Try yourself first then consult the answers) ath, which can maximize the hardwar 149 which is used as a status register, simi 32 bit register. oa eae nd Zero flags. be set with accessing the CPSR and setting the THUMB bit T. supports the JAVA based operations. d in ARM core. They are: « System mode * Undefined mode * User mode d. Except modes fall in this category. sed to increase speed of execution. lining. 3, 5 and 6 stage pipelines ar e followed h has Fetch, Decode and Execute stages. and write stages in addition. e usage available ode bits of the CPSR nstruction which is totally not known to the tered set mode. and not from memory. 1a for temporary storage purpose tched from