SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64 bytes of transmit

and receive FIFOs, IrDA SIR built-in support
Rev. 01 — 4 January 2006 Product data sheet

1. General description
The SC16IS740/750/760 is a slave I2C-bus/SPI interface to a single-channel high
performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and
sleeping current. The SC16IS750 and SC16IS760 also provide the application with 8
additional programmable I/O pins. The device comes in very small HVQFN24, TSSOP24
(SC16IS750/760) and TSSOP16 (SC16IS740) packages, which makes it ideally suitable
for hand-held, battery operated applications. This family of products enables seamless
protocol conversion from I2C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.

The SC16IS760 differs from the SC16IS750 in that it supports SPI clock speeds up to
15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS750, and in that it supports
IrDA SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS760 is functionally and
electrically the same as the SC16IS750. The SC16IS740 is functionally and electrically
identical to the SC16IS750, with the exception of the programmable I/O pins which are
only present on the SC16IS750.

The SC16IS740/750/760’s internal register set is backward-compatible with the widely

used and widely popular 16C450. This allows the software to be easily written or ported
from another platform.

The SC16IS740/750/760 also provides additional advanced features such as auto

hardware and software flow control, automatic RS-485 support, and software reset. This
allows the software to reset the UART at any moment, independent of the hardware reset
signal.

2. Features

2.1 General features

■ Single full-duplex UART
■ Selectable I2C-bus or SPI interface
■ 3.3 V or 2.5 V operation
■ Industrial temperature range: –40 °C to +85 °C
■ 64 bytes FIFO (transmitter and receiver)
■ Fully compatible with industrial standard 16C450 and equivalent
■ Baud rates up to 5 Mbit/s in 16× clock mode
■ Auto hardware flow control using RTS/CTS
■ Auto software flow control with programmable Xon/Xoff characters
■ Single or double Xon/Xoff characters
■ Automatic RS-485 support (automatic slave address detection)
Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

■ Up to eight programmable I/O pins (SC16IS750 and SC16IS760 only)

■ RS-485 driver direction control via RTS signal
■ RS-485 driver direction control inversion
■ Built-in IrDA encoder and decoder interface
■ SC16IS750 supports IrDA SIR with speeds up to 115.2 kbit/s
■ SC16IS760 supports IrDA SIR with speeds up to 1.152 Mbit/s1
■ Software reset
■ Transmitter and receiver can be enabled/disabled independent of each other
■ Receive and Transmit FIFO levels
■ Programmable special character detection
■ Fully programmable character formatting
◆ 5-bit, 6-bit, 7-bit or 8-bit character
◆ Even, odd, or no parity
◆ 1, 11⁄2, or 2 stop bit
■ Line break generation and detection
■ Internal Loopback mode
■ Sleep current less than 30 µA at 3.3 V
■ Industrial and commercial temperature ranges
■ Available in HVQFN24, TSSOP24 (SC16IS750/760) and TSSOP16 (SC16IS740)
packages

2.2 I2C-bus features

■ Noise filter on SCL/SDA inputs
■ 400 kbit/s maximum speed
■ Compliant with I2C-bus fast speed
■ Slave mode only

2.3 SPI features

■ SC16IS750 supports 4 Mbit/s maximum SPI clock speed
■ SC16IS760 supports 15 Mbit/s maximum SPI clock speed
■ Slave mode only
■ SPI Mode 0

3. Applications
■ Factory automation and process control
■ Portable and battery operated devices
■ Cellular data devices

1. Please note that IrDA SIR at 1.152 Mbit/s is not compatible with IrDA MIR at that speed. Please refer to application notes for usage
of IrDA SIR at 1.152 Mbit/s.

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Product data sheet Rev. 01 — 4 January 2006 2 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

4. Ordering information
Table 1: Ordering information
Type number Package
Name Description Version
SC16IS740IPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
SC16IS750IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; SOT616-3
24 terminals; body 4 × 4 × 0.85 mm
SC16IS750IPW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
SC16IS760IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; SOT616-3
24 terminals; body 4 × 4 × 0.85 mm
SC16IS760IPW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

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Product data sheet Rev. 01 — 4 January 2006 3 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

5. Block diagram

VDD

SC16IS750/760
RESET
SCL TX
16C450
SDA COMPATIBLE RX
A0 REGISTER RTS
I2C-BUS SETS
A1 CTS
IRQ
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)
4
VDD GPIO[3:0]

VDD GPIO GPIO4/DSR

I2C/SPI REGISTER GPIO5/DTR

GPIO6/CD
GPIO7/RI

XTAL1 XTAL2 VSS 002aab014

Fig 1. Block diagram of SC16IS750/760 I2C-bus interface

VDD

SC16IS740
RESET
SCL TX
16C450
SDA COMPATIBLE RX
A0 REGISTER RTS
I2C-BUS SETS
A1 CTS
IRQ
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)

VDD

VDD

I2C/SPI

XTAL1 XTAL2 VSS 002aab971

Fig 2. Block diagram of SC16IS740 I2C-bus interface

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Product data sheet Rev. 01 — 4 January 2006 4 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

VDD

SC16IS750/760
RESET
SCLK TX
16C450
CS COMPATIBLE RX
SO REGISTER RTS
SPI SETS
SI CTS
IRQ
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)
4
VDD GPIO[3:0]

GPIO GPIO4/DSR
I2C/SPI REGISTER GPIO5/DTR
GPIO6/CD
GPIO7/RI

002aab396
XTAL1 XTAL2 VSS

Fig 3. Block diagram of SC16IS750/760 SPI interface

VDD

SC16IS740
RESET
SCLK TX
16C450
CS COMPATIBLE RX
SO REGISTER RTS
SPI SETS
SI CTS
IRQ
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)

VDD

I2C/SPI

002aab972
XTAL1 XTAL2 VSS

Fig 4. Block diagram of SC16IS740 SPI interface

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Product data sheet Rev. 01 — 4 January 2006 5 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

6. Pinning information

6.1 Pinning

VDD 1 16 XTAL2 VDD 1 16 XTAL2

A0 2 15 XTAL1 CS 2 15 XTAL1
A1 3 14 RESET SI 3 14 RESET
n.c. 4 13 RX SO 4 13 RX
SC16IS740IPW SC16IS740IPW
SCL 5 12 TX SCLK 5 12 TX
SDA 6 11 CTS VDD 6 11 CTS
IRQ 7 10 RTS IRQ 7 10 RTS
I2C 8 9 VSS SPI 8 9 VSS

002aab973 002aab974

a. I2C-bus interface b. SPI interface

Fig 5. Pin configuration for TSSOP16

CTS 1 24 RTS CTS 1 24 RTS

TX 2 23 GPIO7/RI TX 2 23 GPIO7/RI
RX 3 22 GPIO6/CD RX 3 22 GPIO6/CD
RESET 4 21 GPIO5/DTR RESET 4 21 GPIO5/DTR
XTAL1 5 20 GPIO4/DSR XTAL1 5 20 GPIO4/DSR
XTAL2 6 19 VSS XTAL2 6 19 VSS
SC16IS750IPW SC16IS750IPW
VDD 7 18 GPIO3 VDD 7 18 GPIO3
SC16IS760IPW SC16IS760IPW
I2C 8 17 GPIO2 SPI 8 17 GPIO2
A0 9 16 GPIO1 CS 9 16 GPIO1
A1 10 15 GPIO0 SI 10 15 GPIO0
n.c. 11 14 IRQ SO 11 14 IRQ
SCL 12 13 SDA SCLK 12 13 VDD

002aab016 002aab399

a. I2C-bus interface b. SPI interface

Fig 6. Pin configuration for TSSOP24

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Product data sheet Rev. 01 — 4 January 2006 6 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

19 GPIO6/CD

19 GPIO6/CD
20 GPIO7/RI

20 GPIO7/RI
22 CTS
21 RTS

22 CTS
21 RTS
24 RX

24 RX
terminal 1 terminal 1
23 TX

23 TX
index area index area

RESET 1 18 GPIO5/DTR RESET 1 18 GPIO5/DTR

XTAL1 2 17 GPIO4/DSR XTAL1 2 17 GPIO4/DSR
XTAL2 3 SC16IS750IBS 16 VSS XTAL2 3 SC16IS750IBS 16 VSS
VDD 4 SC16IS760IBS 15 GPIO3 VDD 4 SC16IS760IBS 15 GPIO3
I2C 5 14 GPIO2 SPI 5 14 GPIO2
A0 6 13 GPIO1 CS 6 13 GPIO1
SDA 10
IRQ 11
GPIO0 12

VDD 10
IRQ 11
GPIO0 12
7
8
9

7
8
9
A1
n.c.
SCL

SI
SO
SCLK
002aab015 002aab401

Transparent top view Transparent top view

a. I2C-bus interface b. SPI interface

Fig 7. Pin configuration for HVQFN24

6.2 Pin description

Table 2: Pin description
Symbol Pin Type Description
TSSOP16 TSSOP24 HVQFN24
CTS 11 1 22 I UART clear to send (active LOW). A logic 0 (LOW) on the CTS
pin indicates the modem or data set is ready to accept transmit
data from the SC16IS740/750/760. Status can be tested by
reading MSR[4]. This pin only affects the transmit and receive
operations when auto-CTS function is enabled via the Enhanced
Feature Register EFR[7] for hardware flow control operation.
TX 12 2 23 O UART transmitter output. During the local Loopback mode, the
TX output pin is disabled and TX data is internally connected to
the UART RX input.
RX 13 3 24 I UART receiver input. During the local Loopback mode, the RX
input pin is disabled and TX data is connected to the UART RX
input internally.
RESET 14 4 1 I device hardware reset (active LOW) [2]
XTAL1 15 5 2 I Crystal input or external clock input. Functions as a crystal input
or as an external clock input. A crystal can be connected
between XTAL1 and XTAL2 to form an internal oscillator circuit
(see Figure 15). Alternatively, an external clock can be
connected to this pin.
XTAL2 16 6 3 O Crystal output or clock output. (See also XTAL1.) XTAL2 is used
as a crystal oscillator output.
VDD 1 7 4 - power supply
I2C/SPI 8 8 5 I I2C-bus or SPI interface select. I2C-bus interface is selected if
this pin is at logic HIGH. SPI interface is selected if this pin is at
logic LOW.

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Product data sheet Rev. 01 — 4 January 2006 7 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 2: Pin description …continued

Symbol Pin Type Description
TSSOP16 TSSOP24 HVQFN24
CS/A0 2 9 6 I SPI chip select or I2C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip
select pin (Schmitt-trigger, active LOW). If I2C-bus configuration
is selected by I2C/SPI pin, this pin along with A1 pin allows user
to change the device’s base address.
SI/A1 3 10 7 I SPI data input pin or I2C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data
input pin. If I2C-bus configuration is selected by I2C/SPI pin, this
pin along with A0 pin allows user to change the device’s base
address. To select the device address, please refer to Table 32.
SO 4 11 8 O SPI data output pin. If SPI configuration is selected by I2C/SPI
pin, this is a 3-stateable output pin. If I2C-bus configuration is
selected by I2C/SPI pin, this pin function is undefined and must
be left as n.c. (not connected).
SCL/SCLK 5 12 9 I I2C-bus or SPI input clock.
SDA 6 13 10 I/O I2C-bus data input/output, open-drain if I2C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this
pin is an undefined pin and must be connected to VDD.
IRQ 7 14 11 O Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register
(IER). Interrupt conditions include: change of state of the input
pins, receiver errors, available receiver buffer data, available
transmit buffer space, or when a modem status flag is detected.
An external resistor (1 kΩ for 3.3 V, 1.5 kΩ for 2.5 V) must be
connected between this pin and VDD.
GPIO0 - 15 12 I/O programmable I/O pin
GPIO1 - 16 13 I/O programmable I/O pin
GPIO2 - 17 14 I/O programmable I/O pin
GPIO3 - 18 15 I/O programmable I/O pin
GPIO4/DSR - 20 17 I/O programmable I/O pin or modem’s DSR pin [1]
GPIO5/DTR - 21 18 I/O programmable I/O pin or modem’s DTR pin [1]
GPIO6/CD - 22 19 I/O programmable I/O pin or modem’s CD pin [1]
GPIO7/RI - 23 20 I/O programmable I/O pin or modem’s RI pin [1]
RTS 10 24 21 O UART request to send (active LOW). A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send.
Writing a logic 1 in the modem control register MCR[1] will set
this pin to a logic 0, indicating data is available. After a reset this
pin is set to a logic 1. This pin only affects the transmit and
receive operations when auto-RTS function is enabled via the
Enhanced Feature Register (EFR[6]) for hardware flow control
operation.
VSS 9 19 16 - ground
VSS - - center pad - The center pad on the back side of the HVQFN24 package is
metallic and should be connected to ground on the
printed-circuit board.

[1] Selectable with IOControl register bit 1.

[2] See Section 7.4 “Hardware reset, Power-On Reset (POR) and software reset”

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Product data sheet Rev. 01 — 4 January 2006 8 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7. Functional description
The UART will perform serial-to-I2C conversion on data characters received from
peripheral devices or modems, and I2C-to-serial conversion on data characters
transmitted by the host. The complete status the SC16IS740/750/760 UART can be read
at any time during functional operation by the host.

The SC16IS740/750/760 can be placed in an alternate mode (FIFO mode) relieving the
host of excessive software overhead by buffering received/transmitted characters. Both
the receiver and transmitter FIFOs can store up to 64 characters (including three
additional bits of error status per character for the receiver FIFO) and have selectable or
programmable trigger levels.

The SC16IS740/750/760 has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTS output and CTS input
signals. Software flow control automatically controls data flow by using programmable
Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (216 – 1).

7.1 Trigger levels

The SC16IS740/750/760 provides independently selectable and programmable trigger
levels for both receiver and transmitter interrupt generation. After reset, both transmitter
and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of
one character. The selectable trigger levels are available via the FCR. The programmable
trigger levels are available via the TLR. If TLR bits are cleared then selectable trigger level
in FCR is used. If TLR bits are not cleared then programmable trigger level in TLR is used.

7.2 Hardware flow control

Hardware flow control is comprised of auto-CTS and auto-RTS (see Figure 8). Auto-CTS
and auto-RTS can be enabled/disabled independently by programming EFR[7:6].

With auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated. If TCR bits are cleared then selectable trigger levels in FCR are
used in place of TCR.

If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.

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Product data sheet Rev. 01 — 4 January 2006 9 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

UART 1 UART 2

SERIAL TO RX TX PARALLEL
PARALLEL TO SERIAL
RX TX
FIFO FIFO
FLOW RTS CTS FLOW
CONTROL CONTROL

PARALLEL TX RX SERIAL TO
TO SERIAL PARALLEL
TX RX
FIFO FIFO
FLOW CTS RTS FLOW
CONTROL CONTROL

002aab656

Fig 8. Autoflow control (Auto-RTS and Auto-CTS) example

7.2.1 Auto-RTS
Figure 9 shows RTS functional timing. The receiver FIFO trigger levels used in auto-RTS
are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger
level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.
The sending device (for example, another UART) may send an additional character after
the trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.

RX start character stop start character stop start

N N+1

RTS

receive
1 2 N N+1
FIFO
read
002aab040

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1
Fig 9. RTS functional timing

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Product data sheet Rev. 01 — 4 January 2006 10 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.2 Auto-CTS
Figure 10 shows CTS functional timing. The transmitter circuitry checks CTS before
sending the next data byte. When CTS is active, the transmitter sends the next byte. To
stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces
interrupts to the host system. When flow control is enabled, CTS level changes do not
trigger host interrupts because the device automatically controls its own transmitter.
Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.

TX start bit 0 to bit 7 stop start bit 0 to bit 7 stop

CTS

002aab041

(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the
current character, but it does not send the next character.
(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 10. CTS functional timing

7.3 Software flow control

Software flow control is enabled through the enhanced feature register and the Modem
Control Register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0]. Table 3 shows software flow control options.

Table 3: Software flow control options (EFR[3:0])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow control
0 0 X X no transmit flow control
1 0 X X transmit Xon1, Xoff1
0 1 X X transmit Xon2, Xoff2
1 1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2
X X 0 0 no receive flow control
X X 1 0 receiver compares Xon1, Xoff1
X X 0 1 receiver compares Xon2, Xoff2
1 0 1 1 transmit Xon1, Xoff1
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 transmit Xon2, Xoff2
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 transmit Xon1 and Xon2, Xoff1 and Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 0 1 1 no transmit flow control
receiver compares Xon1 and Xon2, Xoff1 and Xoff2

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

There are two other enhanced features relating to software flow control:

• Xon Any function (MCR[5]): Receiving any character will resume operation after
recognizing the Xoff character. It is possible that an Xon1 character is recognized as
an Xon Any character, which could cause an Xon2 character to be written to the RX
FIFO.
• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the
RX FIFO.

7.3.1 RX
When software flow control operation is enabled, the SC16IS740/750/760 will compare
incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2
must be received sequentially). When the correct Xoff characters are received,
transmission is halted after completing transmission of the current character. Xoff
detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.

7.3.2 TX
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0] or the selectable trigger level in FCR[7:6]

Xon1/Xoff2 character is transmitted when the RX FIFO reaches the RESUME trigger level
programmed in TCR[7:4] or RX FIFO falls below the lower selectable trigger level in
FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,
or 7 bits, then the 5, 6, or 7 least significant bits of XOFF1/XOFF2 or XON1/XON2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 11 shows an example of software flow control.

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Product data sheet Rev. 01 — 4 January 2006 12 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

UART1 UART2

TRANSMIT FIFO RECEIVE FIFO

data
PARALLEL-TO-SERIAL SERIAL-TO-PARALLEL

Xoff–Xon–Xoff
SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL

Xon1 WORD Xon1 WORD

Xon2 WORD Xon2 WORD

Xoff1 WORD Xoff1 WORD

compare
Xoff2 WORD Xoff2 WORD
programmed
Xon-Xoff
characters 002aaa229

Fig 11. Example of software flow control

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Product data sheet Rev. 01 — 4 January 2006 13 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.4 Hardware reset, Power-On Reset (POR) and software reset

These three reset methods are identical and will reset the internal registers as indicated in
Table 4.

Table 4 summarizes the state of register.

Table 4: Register reset [1]

Register Reset state
Interrupt Enable Register all bits cleared
Interrupt Identification Register bit 0 is set; all other bits cleared
FIFO Control Register all bits cleared
Line Control Register reset to 0001 1101 (1Dh)
Modem Control Register all bits cleared
Line Status Register bit 5 and bit 6 set; all other bits cleared
Modem Status Register bits 0:3 cleared; bits 4:7 input signals
Enhanced Feature Register all bits cleared
Receiver Holding Register pointer logic cleared
Transmitter Holding Register pointer logic cleared
Transmission Control Register all bits cleared.
Trigger Level Register all bits cleared.
Transmit FIFO level reset to 0100 0000 (40h)
Receive FIFO level all bits cleared
I/O direction [2] all bits cleared
I/O interrupt enable [2] all bits cleared
I/O control [3] all bits cleared
Extra Feature Register all bits cleared

[1] Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR or Software Reset, that is, they hold their initialization values during reset.
[2] This register is not supported in SC16IS740.
[3] Only UART Software Reset bit is supported in this register.

Table 5 summarizes the state of registers after reset.

Table 5: Output signals after reset

Signal Reset state
TX HIGH
RTS HIGH
I/Os inputs
IRQ HIGH by external pull-up

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Product data sheet Rev. 01 — 4 January 2006 14 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.5 Interrupts
The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized
levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable
each of the seven types of interrupts and the IRQ signal in response to an interrupt
generation. When an interrupt is generated, the IIR indicates that an interrupt is pending
and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt
control functions.

Table 6: Summary of interrupt control functions

IIR[5:0] Priority Interrupt type Interrupt source
level
000001 none none none
000110 1 receiver line status OE, FE, PE, or BI errors occur in characters in the
RX FIFO
001100 2 RX time-out Stale data in RX FIFO
000100 2 RHR interrupt Receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)
000010 3 THR interrupt Transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)
000000 4 modem status [1] Change of state of modem input pins
110000 5 I/O pins [1] Input pins change of state
010000 6 Xoff interrupt Receive Xoff character(s)/ special character
100000 7 CTS, RTS RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)

[1] Available only on SC16IS750/SC16IS760.

It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.5.1 Interrupt mode operation

In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the
receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced. Figure 12 shows Interrupt mode operation.

IIR
read IIR
IRQ
HOST

IER
1 1 1 1

THR RHR

002aab042

Fig 12. Interrupt mode operation

7.5.2 Polled mode operation

In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO
Interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU. Figure 13 shows FIFO
Polled mode operation.

read LSR LSR

HOST

IER
0 0 0 0

THR RHR

002aab043

Fig 13. FIFO Polled mode operation

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.6 Sleep mode

Sleep mode is an enhanced feature of the SC16IS740/750/760 UART. It is enabled when
EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered
when:

• The serial data input line, RX, is idle (see Section 7.7 “Break and time-out
conditions”).
• The TX FIFO and TX shift register are empty.
• There are no interrupts pending except THR.
Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using
these clocks, the power consumption is greatly reduced. The UART will wake up when any
change is detected on the RX line, when there is any change in the state of the modem
input pins, or if data is written to the TX FIFO.

Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLH.

7.7 Break and time-out conditions

When the UART receives a number of characters and these data are not enough to set off
the receive interrupt (because they do not reach the receive trigger level), the UART will
generate a time-out interrupt instead, 4 character times after the last character is
received. The time-out counter will be reset at the center of each stop bit received or each
time the receive FIFO is read.

A break condition is detected when the RX pin is pulled LOW for a duration longer than
the time it takes to send a complete character plus Start, Stop and Parity bits. A break
condition can be sent by setting LCR[6]. When this happens the TX pin will be pulled LOW
until LSR[6] is cleared by the software.

7.8 Programmable baud rate generator

The SC16IS740/750/760 UART contains a programmable baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (216 – 1). An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as
shown in Figure 14. The output frequency of the baud rate generator is 16× the baud rate.
The formula for the divisor is:

 XTAL1 crystal input frequency

 ---------------------------------------------------------------------------
prescaler 
divisor = --------------------------------------------------------------------------------- (1)
desired baud rate × 16

where:

prescaler = 1, when MCR[7] is set to ‘0’ after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to ‘1’ after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Figure 14 shows the internal prescaler and baud rate generator circuitry.

PRESCALER MCR[7] = 0
LOGIC
(DIVIDE-BY-1)
internal
XTAL1 INTERNAL BAUD RATE baud rate
OSCILLATOR input clock GENERATOR clock for
XTAL2 LOGIC LOGIC transmitter
reference and receiver
PRESCALER clock
LOGIC
(DIVIDE-BY-4) MCR[7] = 1
002aaa233

Fig 14. Prescaler and baud rate generator block diagram

DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.

Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency
1.8432 MHz and 3.072 MHz, respectively.

Figure 15 shows the crystal clock circuit reference.

Table 7: Baud rates using a 1.8432 MHz crystal

Desired baud rate Divisor used to generate Percent error difference
16× clock between desired and actual
50 2304 0
75 1536 0
110 1047 0.026
134.5 857 0.058
150 768 0
300 384 0
600 192 0
1200 96 0
1800 64 0
2000 58 0.69
2400 48 0
3600 32 0
4800 24 0
7200 16 0
9600 12 0
19200 6 0
38400 3 0
56000 2 2.86

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 8: Baud rates using a 3.072 MHz crystal

Desired baud rate Divisor used to generate Percent error difference
16× clock between desired and actual
50 2304 0
75 2560 0
110 1745 0.026
134.5 1428 0.034
150 1280 0
300 640 0
600 320 0
1200 160 0
1800 107 0.312
2000 96 0
2400 80 0
3600 53 0.628
4800 40 0
7200 27 1.23
9600 20 0
19200 10 0
38400 5 0

XTAL1 XTAL2

1.8432 MHz

C1 C2
22 pF 33 pF

002aab402

Fig 15. Crystal oscillator circuit reference

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8. Register descriptions
The programming combinations for register selection are shown in Table 9.

Table 9: Register map - read/write properties

Register name Read mode Write mode
RHR/THR Receive Holding Register (RHR) Transmit Holding Register (THR)
IER Interrupt Enable Register (IER) Interrupt Enable Register
IIR/FCR Interrupt Identification Register (IIR) FIFO Control Register (FCR)
LCR Line Control Register (LCR) Line Control Register
MCR Modem Control Register (MCR) [1] Modem Control Register [1]
LSR Line Status Register (LSR) n/a
MSR Modem Status Register (MSR) n/a
SPR Scratchpad Register (SPR) Scratchpad Register
TCR Transmission Control Register (TCR) [2] Transmission Control Register [2]
TLR Trigger Level Register (TLR) [2] Trigger Level Register [2]
TXLVL Transmit FIFO Level Register n/a
RXLVL Receive FIFO Level Register n/a
IODir [3] I/O pin Direction Register I/O pin Direction Register
IOState [3] I/O pin States Register n/a
IOIntEna [3] I/O Interrupt Enable Register I/O Interrupt Enable Register
IOControl [3] I/O pins Control Register I/O pins Control Register
EFCR Extra Features Register Extra Features Register
DLL divisor latch LSB (DLL) [4] divisor latch LSB [4]
DLH divisor latch MSB (DLH) [4] divisor latch MSB [4]
EFR Enhanced Feature Register (EFR) [5] Enhanced Feature Register [5]
XON1 Xon1 word [5] Xon1 word [5]
XON2 Xon2 word [5] Xon2 word [5]
XOFF1 Xoff1 word [5] Xoff1 word [5]
XOFF2 Xoff2 word [5] Xoff2 word [5]

[1] MCR[7] can only be modified when EFR[4] is set.

[2] Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables.
[3] Available only on SC16IS750/SC16IS760.
[4] Accessible only when LCR[7] is logic 1.
[5] Accessible only when LCR is set to 1011 1111b (0xBF).

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 10: SC16IS740/750/760 internal registers

Register
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
address
General register set [1]
0x00 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
0x00 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W
0x01 IER CTS RTS Xoff [2] sleep modem receive THR empty RX data R/W
interrupt interrupt mode [2] status line status interrupt available
enable [2] enable [2] interrupt interrupt interrupt
0x02 FCR RX RX TX TX trigger reserved TX FIFO RX FIFO FIFO W
trigger trigger trigger level [3] reset [5] reset [5] enable
level level level (LSB) [2]

(MSB) (LSB) (MSB) [2]

0x02 IIR [6] FIFO FIFO interrupt interrupt interrupt interrupt interrupt interrupt R
enable enable priority priority priority priority priority status
bit 4 [2] bit 3 [2] bit 2 bit 1 bit 0
0x03 LCR Divisor set break set parity even parity stop bit word length word length R/W
Latch parity enable bit 1 bit 0
Enable
0x04 MCR clock IrDA Xon loopback reserved TCR and RTS DTR/(IO5) R/W
divisor [2] mode Any [2] enable [3] TLR [4]

enable [2] enable [2]

0x05 LSR FIFO THR and THR break framing parity error overrun data in R
data error TSR empty interrupt error error receiver
empty
0x06 MSR CD/(IO6) RI/(IO7) DSR/ CTS ∆CD/ ∆RI/(IO7) ∆DSR/ ∆CTS R
[4] [4] (IO4) [4] (IO6) [4] [4] (IO4) [4]
0x07 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x06 TCR [7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x07 TLR [7] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x08 TXLVL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
0x09 RXLVL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
0x0A IODir [4] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x0B IOState bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
[4]

0x0C IOIntEna bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
[4]

0x0D reserved reserved reserved reserved reserved reserved reserved reserved reserved
[3] [3] [3] [3] [3] [3] [3] [3] [3]

0x0E IOControl reserved reserved reserved reserved UART reserved I/O[7:4] or latch R/W
[4] [3] [3] [3] [3] software [3] RI, CD,
reset DTR, DSR
0x0F EFCR IrDA reserved auto auto reserved transmitter receiver 9-bit mode R/W
mode [3] RS-485 RS-485 [3] disable disable enable
(slow/ RTS RTS
fast) [8] output direction
inversion control

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 10: SC16IS740/750/760 internal registers …continued

Register
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
address
Special register set [9]
0x00 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x01 DLH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Enhanced register set [10]
0x02 EFR Auto CTS Auto RTS special enable software software software software R/W
character enhanced flow flow flow control flow control
detect functions control control bit 1 bit 0
bit 3 bit 2
0x04 XON1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x05 XON2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x06 XOFF1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0x07 XOFF2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

[1] These registers are accessible only when LCR[7] = 0.

[2] These bits in can only be modified if register bit EFR[4] is enabled.
[3] These bits are reserved and should be set to 0.
[4] Only available on the SC16IS750/SC16IS760.
[5] After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2 × Tclk of XTAL1 before reading or writing
data to RHR and THR, respectively.
[6] Burst reads on the serial interface (that is, reading multiple elements on the I2C-bus without a STOP or repeated START condition, or
reading multiple elements on the SPI bus without de-asserting the CS pin), should not be performed on the IIR register.
[7] These registers are accessible only when MCR[2] = 1 and EFR[4] = 1.
[8] IrDA mode slow/fast for SC16IS760, slow only for SC16IS750.
[9] The special register set is accessible only when LCR[7] = 1 and not 0xBF.
[10] Enhanced Feature Registers are only accessible when LCR = 0xBF.

8.1 Receive Holding Register (RHR)

The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX pin. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.

8.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX pin. If
the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow
occurs.

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels. Table 11 shows FIFO Control Register bit settings.

Table 11: FIFO Control Register bits description

Bit Symbol Description
7:6 FCR[7] (MSB), RX trigger. Sets the trigger level for the RX FIFO.
FCR[6] (LSB) 00 = 8 characters
01 = 16 characters
10 = 56 characters
11 = 60 characters
5:4 FCR[5] (MSB), TX trigger. Sets the trigger level for the TX FIFO.
FCR[4] (LSB) 00 = 8 spaces
01 = 16 spaces
10 = 32 spaces
11 = 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3 FCR[3] reserved
2 FCR[2] [1] reset TX FIFO
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
level logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
1 FCR[1] [1] reset RX FIFO
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
level logic (the Receive Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0 FCR[0] FIFO enable
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO

[1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the
XTAL1 clock.

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.4 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12
shows the Line Control Register bit settings.

Table 12: Line Control Register bits description

Bit Symbol Description
7 LCR[7] divisor latch enable
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6 LCR[6] Break control bit. When enabled, the break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition).
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
4 LCR[4] parity type select
logic 0 = odd parity is generated (if LCR[3] = 1)
logic 1 = even parity is generated (if LCR[3] = 1)
3 LCR[3] parity enable
logic 0 = no parity (normal default condition).
logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity
2 LCR[2] Number of stop bits. Specifies the number of stop bits.
0 to 1 stop bit (word length = 5, 6, 7, 8)
1 to 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received; see Table 15.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 13: LCR[5] parity selection

LCR[5] LCR[4] LCR[3] Parity selection
X X 0 no parity
0 0 1 odd parity
0 1 1 even parity
1 0 1 forced parity ‘1’
1 1 1 forced parity ‘0’

Table 14: LCR[2] stop bit length

LCR[2] Word length (bits) Stop bit length (bit times)
0 5, 6, 7, 8 1
1 5 11⁄2
1 6, 7, 8 2

Table 15: LCR[1:0] word length

LCR[1] LCR[0] Word length (bits)
0 0 5
0 1 6
1 0 7
1 1 8

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.5 Line Status Register (LSR)

Table 16 shows the Line Status Register bit settings.

Table 16: Line Status Register bits description

Bit Symbol Description
7 LSR[7] FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = transmit hold register is not empty
logic 1 = transmit hold register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
4 LSR[4] break interrupt
logic 0 = no break condition (normal default condition)
logic 1 = a break condition occurred and associated character is 00h, that
is, RX was LOW for one character time frame
3 LSR[3] framing error
logic 0 = no framing error in data being read from RX FIFO (normal default
condition).
logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit
2 LSR[2] parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
1 LSR[1] overrun error
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
0 LSR[0] data in receiver
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO

When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem. Table 17 shows the Modem Control Register bit settings.

Table 17: Modem Control Register bits description

Bit Symbol Description
7 MCR[7] [1] clock divisor
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6 MCR[6] [1] IrDA mode enable
logic 0 = normal UART mode
logic 1 = IrDA mode
5 MCR[5] [1] Xon Any
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
4 MCR[4] enable loop-back
logic 0 = normal operating mode
logic 1 = enable local Loop-back mode (internal). In this mode the
MCR[1:0] signals are looped back into MSR[4:5] and the TX output is
looped back to the RX input internally.
3 MCR[3] reserved
2 MCR[2] TCR and TLR enable
logic 0 = disable the TCR and TLR register.
logic 1 = enable the TCR and TLR register.
1 MCR[1] RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW). In loop-back mode,
controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled
by hardware flow control.
0 MCR[0] DTR [2]. If GPIO5 is selected as DTR modem pin through IOControl
register bit 1, the state of DTR pin can be controlled as below. Writing to
IOState bit 5 will not have any effect on this pin.
logic 0 = Force DTR output to inactive (HIGH)
logic 1 = Force DTR output to active (LOW)

[1] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
[2] Only available on SC16IS750/SC16IS760.

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Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.7 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the host. It also indicates when a control input
from the modem changes state. Table 18 shows Modem Status Register bit settings.

Table 18: Modem Status Register bits description

Bit Symbol Description
7 MSR[7] CD [1] (active HIGH, logical 1). If GPIO6 is selected as CD modem pin
through IOControl register bit 1, the state of CD pin can be read from this
bit. This bit is the complement of the CD input. Reading IOState bit 6 does
not reflect the true state of CD pin.
6 MSR[6] RI [1] (active HIGH, logical 1). If GPIO7 is selected as RI modem pin through
IOControl register bit 1, the state of RI pin can be read from this bit. This bit
is the complement of the RI input. Reading IOState bit 6 does not reflect the
true state of RI pin.
5 MSR[5] DSR [1] (active HIGH, logical 1). If GPIO4 is selected as DSR modem pin
through IOControl register bit 1, the state of DSR pin can be read from this
bit. This bit is the complement of the DSR input. Reading IOState bit 4 does
not reflect the true state of DSR pin.
4 MSR[4] CTS (active HIGH, logical 1). This bit is the complement of the CTS input.
3 MSR[3] ∆CD [1]. Indicates that CD input has changed state. Cleared on a read.
2 MSR[2] ∆RI [1]. Indicates that RI input has changed state from LOW to HIGH.
Cleared on a read.
1 MSR[1] ∆DSR [1]. Indicates that DSR input has changed state. Cleared on a read.
0 MSR[0] ∆CTS. Indicates that CTS input has changed state. Cleared on a read.

[1] Only available on SC16IS750/SC16IS760.

Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.8 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation. Table 19 shows the Interrupt Enable Register bit settings.

Table 19: Interrupt Enable Register bits description

Bit Symbol Description
7 IER[7] [1] CTS interrupt enable
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
6 IER[6] [1] RTS interrupt enable
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
5 IER[5] [1] Xoff interrupt
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
4 IER[4] [1] Sleep mode
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 7.6 “Sleep mode” for details.
3 IER[3] Modem Status Interrupt [2].
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
Remark: See IOControl register bit 1 for the description of how to program the
pins as modem pins.
2 IER[2] Receive Line Status interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1 IER[1] Transmit Holding Register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
0 IER[0] Receive Holding Register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt

[1] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
[2] Only available on the SC16IS750/SC16IS760.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.9 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 20 shows Interrupt Identification Register bit settings.

Table 20: Interrupt Identification Register bits description

Bit Symbol Description
7:6 IIR[7:6] mirror the contents of FCR[0]
5:1 IIR[5:1] 5-bit encoded interrupt. See Table 21.
0 IIR[0] interrupt status
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending

Table 21: Interrupt source

Priority IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt
level
1 0 0 0 1 1 0 Receiver Line Status error
2 0 0 1 1 0 0 Receiver time-out interrupt
2 0 0 0 1 0 0 RHR interrupt
3 0 0 0 0 1 0 THR interrupt
4 0 0 0 0 0 0 modem interrupt [1] [2]
5 1 1 0 0 0 0 input pin change of state [1] [2]
6 0 1 0 0 0 0 received Xoff signal/
special character
7 1 0 0 0 0 0 CTS, RTS change of state
from active (LOW) to inactive
(HIGH)

[1] Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState
register.
[2] Only available on SC16IS750/SC16IS760.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.10 Enhanced Features Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows
the enhanced feature register bit settings.

Table 22: Enhanced Features Register bits description

Bit Symbol Description
7 EFR[7] CTS flow control enable
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
6 EFR[6] RTS flow control enable.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO resume transmission trigger level TCR[7:4] is reached.
5 EFR[5] Special character detect
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to FIFO
and IIR[4] is set to a logical 1 to indicate a special character has been
detected.
4 EFR[4] Enhanced functions enable bit
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
so that they can be modified.
3:0 EFR[3:0] Combinations of software flow control can be selected by programming these
bits. See Table 3 “Software flow control options (EFR[3:0])”.

8.11 Division registers (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.

Note that DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.12 Transmission Control Register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission
during hardware/software flow control. Table 23 shows Transmission Control Register bit
settings.

Table 23: Transmission Control Register bits description

Bit Symbol Description
7:4 TCR[7:4] RX FIFO trigger level to resume
3:0 TCR[3:0] RX FIFO trigger level to halt transmission

TCR trigger levels are available from 0 to 60 characters with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer
must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware
check to make sure this condition is met. Also, the TCR must be programmed with this
condition before Auto-RTS or software flow control is enabled to avoid spurious operation
of the device.

8.13 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for
interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of
4. Table 24 shows trigger level register bit settings.

Table 24: Trigger Level Register bits description

Bit Symbol Description
7:4 TLR[7:4] RX FIFO trigger levels (4 to 60), number of characters available.
3:0 TLR[3:0] TX FIFO trigger levels (4 to 60), number of spaces available.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 characters
to 60 characters are available with a granularity of four. The TLR should be programmed
for N⁄4, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the trigger
level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level
defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger
level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
that is, ‘00’.

8.14 Transmitter FIFO Level register (TXLVL)

This register is a read-only register, it reports the number of spaces available in the
transmit FIFO.

Table 25: Transmitter FIFO Level register bits description

Bit Symbol Description
7 - not used; set to zeros
6:0 TXLVL[6:0] number of spaces available in TXFIFO, from 0 (0x00) to 64 (0x40)

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.15 Receiver FIFO Level register (RXLVL)

This register is a read-only register, it reports the fill level of the receive FIFO. That is, the
number of characters in the RXFIFO.

Table 26: Receiver FIFO Level register bits description

Bit Symbol Description
7 - not used; set to zeros
6:0 RXLVL[6:0] number of characters stored in RXFIFO, from 0 (0x00) to 64 (0x40)

8.16 Programmable I/O pins Direction register (IODir)

This register is only available on the SC16IS750 and SC16IS760. This register is used to
program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to GPIO7.

Table 27: IODir register bits description

Bit Symbol Description
7:0 IODir set GPIO pins [7:0] to input or output
0 = input
1 = output

Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending
interrupt will be cleared, that is, the interrupt signal will be negated.

8.17 Programmable I/O pins State Register (IOState)

This register is only available on the SC16IS750 and SC16IS760. When ‘read’, this
register returns the actual state of all I/O pins. When ‘write’, each register bit will be
transferred to the corresponding IO pin programmed as output.

Table 28: IOState register bits description

Bit Symbol Description
7:0 IOState Write this register:
set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register:
return states of all pins

8.18 I/O Interrupt Enable Register (IOIntEna)

This register is only available on the SC16IS750 and SC16IS760. This register enables
the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] are programmed
as modem pins, their interrupt generation must be enabled via IER register bit 3. In this
case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].

Table 29: IOIntEna register bits description

Bit Symbol Description
7:0 IOIntEna input interrupt enable
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.19 I/O Control register (IOControl)

This register is only available on the SC16IS750 and SC16IS760.

Table 30: IOControl register bits description

Bit Symbol Description
7:4 - reserved for future use
3 SRESET software reset
A write to bit will reset the device. Once the device is reset this bit is
automatically set to ‘0’
2 - reserved for future use
1 GPIO[7:4] or This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR
modem pins pins.
0 = GPIO[7:4] behave as I/O pins
1 = GPIO[7:4] behave as RI, CD, DTR, DSR
0 IOLATCH enable/disable inputs latching
0 = input values are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.

Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled
by the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI,
DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these
three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the
state of the DTR pin cannot be controlled by MCR[0].

As modem CD, RI, DSR pins, the status at the input of these three pins can be read from
MSR[7:5] and MSR[3:1], and the state of DTR pin can be controlled by MCR[0]. Also, if
modem status interrupt bit is enabled, IER[3], a change of state of RI, CD, DSR pins will
trigger a modem interrupt. Bit[7:4] of the IODir, IOState, and IOIntEna registers will not
have any effect on these three pins.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.20 Extra Features Control Register (EFCR)

Table 31: Extra Features Control Register bits description
Bit Symbol Description
7 IRDA MODE IrDA mode
0 = IrDA SIR, 3⁄16 pulse ratio, data rate up to 115.2 kbit/s
1 = IrDA SIR, 1⁄4 pulse ratio, data rate up to 1.152 Mbit/s [1]
6 - reserved
5 RTSINVER invert RTS signal in RS-485 mode
0: RTS = 0 during transmission and RTS = 1 during reception
1: RTS = 1 during transmission and RTS = 0 during reception
4 RTSCON enable the transmitter to control the RTS pin
0 = transmitter does not control RTS pin
1 = transmitter controls RTS pin
3 - reserved
2 TXDISABLE Disable transmitter. UART does not send serial data out on the
transmit pin, but the transmit FIFO will continue to receive data from
host until full. Any data in the TSR will be sent out before the
transmitter goes into disable state.
0: transmitter is enabled
1: transmitter is disabled
1 RXDISABLE Disable receiver. UART will stop receiving data immediately once this
bit set to a 1, and any data in the TSR will be sent to the receive FIFO.
User is advised not to set this bit during receiving.
0: receiver is enabled
1: receiver is disabled
0 9-BIT MODE Enable 9-bit or Multidrop mode (RS-485).
0: normal RS-232 mode
1: enables RS-485 mode

[1] For SC16IS760 only.

9. RS-485 features

9.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the
logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTS pin. The transmitter automatically asserts the
RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin
(logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware flow
control function.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

9.2 RS-485 RTS output inversion

EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.
When the transmitter has data to be sent it will deasserts the RTS pin (logic 1), and when
the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

9.3 Auto RS-485

EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of
operation, a ‘master’ station transmits an address character followed by data characters
for the addressed ‘slave’ stations. The slave stations examine the received data and
interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 mode the software would have to disable the hardware and
software flow control functions.

9.3.1 Normal multidrop mode

The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).
The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an
address byte is received (parity bit = 1). This address byte will cause the UART to set the
parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at
this time), and at the same time puts this address byte in the RX FIFO. After the controller
examines the byte it must make a decision whether or not to enable the receiver; it should
enable the receiver if the address byte addresses its ID address, and must not enable the
receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until
being disabled by the controller after the controller has received a complete message from
the ‘master’ station. If the controller does not disable the receiver after receiving a
message from the ‘master’ station, the receiver will generate a parity error upon receiving
another address byte. The controller then determines if the address byte addresses its ID
address, if it is not, the controller then can disable the receiver. If the address byte
addresses the ‘slave’ ID address, the controller take no further action, the receiver will
receive the subsequent data.

9.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the
address byte) the receiver will try to detect an address byte that matches the programmed
character in the XOFF2 register. If the received byte is a data byte or an address byte that
does not match the programmed character in the XOFF2 register, the receiver will discard
these data. Upon receiving an address byte that matches the Xoff2 character, the receiver
will be automatically enabled if not already enabled, and the address character is pushed
into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also
generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will
then receive the subsequent data from the ‘master’ station until being disabled by the
controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match Xoff2 character,
the receiver will be automatically disabled and the address byte is ignored. If the address
byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the
parity bit in the parity error bit (LSR bit 2).
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10. I2C-bus operation

The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.

10.1 Data transfers

One data bit is transferred during each clock pulse (see Figure 16). The data on the SDA
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see Figure 17). The bus is considered to be busy after the START condition and
free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.

SDA

SCL

data line change

stable; of data
data valid allowed mba607

Fig 16. Bit transfer on the I2C-bus

SDA SDA

SCL SCL
S P

START condition STOP condition

mba608

Fig 17. START and STOP conditions

The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit.
(see Figure 18). The clock pulse related to the acknowledge bit is generated by the
master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see
Figure 19).

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

acknowledgement signal
from receiver

SDA
MSB

SCL S 0 1 6 7 8 0 1 2 to 7 8 P
ACK ACK
START STOP
condition byte complete, clock line held LOW condition
interrupt within receiver while interrupt is serviced
002aab012

Fig 18. Data transfer on the I2C-bus

data output transmitter stays off of the bus

by transmitter during the acknowledge clock

data output acknowledgement signal

by receiver from receiver

SCL from master S 0 1 6 7 8

002aab013
START
condition

Fig 19. Acknowledge on the I2C-bus

A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.

There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.

The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.

10.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.

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An address on the network is seven bits long, appearing as the most significant bits of the
address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is
transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete
data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is
shown in Figure 20.

SDA

SCL S 0 to 6 7 8 0 to 6 7 8 0 to 6 7 8 P

START address R/W ACK data ACK data ACK STOP

condition condition

002aab046

Fig 20. A complete data transfer

When an address is sent, each device in the system compares the first seven bits after the
START with its own address. If there is a match, the device will consider itself addressed
by the master, and will send an acknowledge. The device could also determine if in this
transaction it is assigned the role of a slave receiver or slave transmitter, depending on the
R/W bit.

Each node of the I2C-bus network has a unique seven-bit address. The address of a
microcontroller is of course fully programmable, while peripheral devices usually have
fixed and programmable address portions.

When the master is communicating with one device only, data transfers follow the format
of Figure 20, where the R/W bit could indicate either direction. After completing the
transfer and issuing a STOP condition, if a master would like to address some other
device on the network, it could start another transaction by issuing a new START.

Another way for a master to communicate with several different devices would be by using
a ‘repeated START’. After the last byte of the transaction was transferred, including its
acknowledge (or negative acknowledge), the master issues another START, followed by
address byte and data—without effecting a STOP. The master may communicate with a
number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes
place, the master issues a STOP and releases the bus. Possible data formats are
demonstrated in Figure 21. Note that the repeated START allows for both change of a
slave and a change of direction, without releasing the bus. We shall see later on that the
change of direction feature can come in handy even when dealing with a single device.

In a single master system, the repeated START mechanism may be more efficient than
terminating each transfer with a STOP and starting again. In a multimaster environment,
the determination of which format is more efficient could be more complicated, as when a
master is using repeated STARTs it occupies the bus for a long time and thus preventing
other devices from initiating transfers.

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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

data transferred
(n bytes + acknowledge)

master write: S SLAVE ADDRESS W A DATA A DATA A P

START condition write acknowledge acknowledge acknowledge

STOP condition

data transferred
(n bytes + acknowledge)

master read: S SLAVE ADDRESS R A DATA A DATA NA P

START condition read acknowledge acknowledge not

acknowledge
STOP condition

data transferred data transferred

(n bytes + acknowledge) (n bytes + acknowledge)

combined
S SLAVE ADDRESS R/W A DATA A Sr SLAVE ADDRESS R/W A DATA A P
formats:

START condition read or acknowledge acknowledge repeated read or acknowledge acknowledge

write START condition write
STOP condition
direction of transfer
may change at this point
002aab458

Fig 21. I2C-bus data formats

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10.3 Addressing
Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The first byte after the START condition carries the address of
the slave device and the read/write bit. Table 32 shows how the SC16IS740/750/760’s
address can be selected by using A1 and A0 pins. For example, if these 2 pins are
connected to VDD, then the SC16IS740/750/760’s address is set to 0x90, and the master
communicates with it through this address.

Table 32: SC16IS740/750/760 address map

A1 A0 SC16IS750/760 I2C addresses (hex) [1]
VDD VDD 0x90 (1001 000X)
VDD VSS 0x92 (1001 001X)
VDD SCL 0x94 (1001 010X)
VDD SDA 0x96 (1001 011X)
VSS VDD 0x98 (1001 100X)
VSS VSS 0x9A (1001 101X)
VSS SCL 0x9C (1001 110X)
VSS SDA 0x9E (1001 111X)
SCL VDD 0xA0 (1010 000X)
SCL VSS 0xA2 (1010 001X)
SCL SCL 0xA4 (1010 010X)
SCL SDA 0xA6 (1010 011X)
SDA VDD 0xA8 (1010 100X)
SDA VSS 0xAA (1010 101X)
SDA SCL 0xAC (1010 110X)
SDA SDA 0xAE (1010 111X)

[1] X = logic 0 for write cycle; X = logic 1 for read cycle.

10.4 Use of sub-addresses

When a master communicates with the SC16IS740/750/760 it must send a sub-address
in the byte following the slave address byte. This sub-address is the internal address of
the word the master wants to access for a single byte transfer, or the beginning of a
sequence of locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the
device address, it does not contain a direction (R/W) bit, and like any byte transferred on
the bus it must be followed by an acknowledge.

A register write cycle is shown in Figure 22. The START is followed by a slave address
byte with the direction bit set to ‘write’, a sub-address byte, a number of data bytes, and a
STOP signal. The sub-address indicates which register the master wants to access. and
the data bytes which follow will be written one after the other to the sub-address location.

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 41 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

S SLAVE ADDRESS W A REGISTER ADDRESS A nDATA A P

002aab047

White block: host to SC16IS740/750/760

Grey block: SC16IS740/750/760 to host
Fig 22. Master writes to slave

The register read cycle (see Figure 23) commences in a similar manner, with the master
sending a slave address with the direction bit set to ‘write’ with a following sub-address.
Then, in order to reverse the direction of the transfer, the master issues a repeated START
followed again by the device address, but this time with the direction bit set to ‘read’. The
data bytes starting at the internal sub-address will be clocked out of the device, each
followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.

S SLAVE ADDRESS W A REGISTER ADDRESS A S SLAVE ADDRESS R A

nDATA A LAST DATA NA P

002aab048

White block: host to SC16IS740/750/760

Grey block: SC16IS740/750/760 to host
Fig 23. Master read from Slave

Table 33: Register address byte (I2C)

Bit Name Function
7 - not used
6:3 A[3:0] UART’s internal register select
2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
0 - not used

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 42 of 61

 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
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Product data sheet
9397 750 14832

11. SPI operation

Philips Semiconductors
SCLK

SO R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0

002aab433

R/W = 0; A[3:0] = register address; CH1 = 0, CH0 = 0

a. Register write

SCLK

SO R/W A3 A2 A1 A0 CH1 CH0 X

SI D7 D6 D5 D4 D3 D2 D1 D0
002aab434

R/W = 1; A[3:0] = register address; CH1 = 0, CH0 = 0

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

b. Register read
Rev. 01 — 4 January 2006

SCLK

SO R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

last bit 002aab435

R/W = 0; A[3:0] = 0000; CH1 = 0, CH0 = 0

c. FIFO write cycle

SC16IS740/750/760
SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

SO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

last bit 002aab436

R/W = 1; A[3:0] = 0000; CH1 = 0, CH0 = 0

d. FIFO read cycle
Fig 24. SPI operation
43 of 61
Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 34: Register address byte (SPI)

Bit Name Function
7 R/W 1: read from UART
0: write to UART
6:3 A[3:0] UART’s internal register select
2:1 CH1, CH0 channel select: CH1 = 0, CH0 = 0
Other values are reserved and should not be used.
0 - not used

12. Limiting values

Table 35: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.3 +4.6 V
VI input voltage any input −0.3 +5.5 [1] V
II input current any input −10 +10 mA
IO output current any output −10 +10 mA
Ptot total power dissipation - 300 mW
P/out power dissipation per output - 50 mW
Tamb ambient temperature operating −40 +85 °C
Tstg storage temperature −65 +150 °C

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present.
4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.

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Product data sheet Rev. 01 — 4 January 2006 44 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

13. Static characteristics

Table 36: Static characteristics
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = –40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit
Min Max Min Max
Supplies
VDD supply voltage 2.3 2.7 3.0 3.6 V
IDD supply current operating; no load - 6.0 - 6.0 mA
Inputs I2C/SPI, RX, CTS
VIH HIGH-state input voltage 1.6 5.5 [1] 2.0 5.5 [1] V
VIL LOW-state input voltage - 0.6 - 0.8 V
IL leakage current input; VI = 0 V or 5.5 V [1] - 1 - 1 µA
Ci input capacitance - 3 - 3 pF
Outputs TX, RTS, SO
VOH HIGH-state output voltage IOH = −400 µA 1.85 - - - V
IOH = −4 mA - - 2.4 - V
VOL LOW-state output voltage IOL = 1.6 mA - 0.4 - - V
IOL = 4 mA - - - 0.4 V
Co output capacitance - 4 - 4 pF
Inputs/outputs GPIO0 to GPIO7 (SC16IS750 and SC16IS760 only)
VIH HIGH-state input voltage 1.6 5.5 [1] 2.0 5.5 [1] V
VIL LOW-state input voltage - 0.6 - 0.8 V
VOH HIGH-state output voltage IOH = −400 µA 1.85 - - - V
IOH = −4 mA - - 2.4 - V
VOL LOW-state output voltage IOL = 1.6 mA - 0.4 - - V
IOL = 4 mA - - - 0.4 V
IL leakage current input; VI = 0 V or 5.5 V [1] - 1 - 1 µA
Co output capacitance - 4 - 4 pF
Output IRQ
VOL LOW-state output voltage IOL = 1.6 mA - 0.4 - - V
IOL = 4 mA - - - 0.4 V
Co output capacitance - 4 - 4 pF
I2C-bus input/output SDA
VIH HIGH-state input voltage 1.6 5.5 [1] 2.0 5.5 [1] V
VIL LOW-state input voltage - 0.6 - 0.8 V
VOL LOW-state output voltage IOL = 1.6 mA - 0.4 - - V
IOL = 4 mA - - - 0.4 V
IL leakage current input; VI = 0 V or 5.5 V [1] - 10 - 10 µA
Co output capacitance - 7 - 7 pF

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 45 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 36: Static characteristics …continued

VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = –40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit
Min Max Min Max
I2C-bus inputs SCL, CS/A0, SI/A1
VIH HIGH-state input voltage 1.6 5.5 [1] 2.0 5.5 [1] V
VIL LOW-state input voltage - 0.6 - 0.8 V
IL leakage current input; VI = 0 V or 5.5 V [1] - 10 - 10 µA
Ci input capacitance - 7 - 7 pF
Clock input XTAL1 [2]
VIH HIGH-state input voltage 1.8 5.5 [1] 2.4 5.5 [1] V
VIL LOW-state input voltage - 0.45 - 0.6 V
IL leakage current input; VI = 0 V or 5.5 V [1] −30 +30 −30 +30 µA
Ci input capacitance - 3 - 3 pF
Sleep current
IDD(sleep) sleep current inputs are at VDD or ground - 30 - 30 µA

[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.
[2] XTAL2 should be left open when XTAL1 is driven by an external clock.

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 46 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

14. Dynamic characteristics

Table 37: I2C-bus timing specifications [1]
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = −40 °C to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
All output load = 25 pF, except SDA output load = 400 pF.
Symbol Parameter Conditions Standard mode Fast mode Unit
I2C-bus I2C-bus
Min Max Min Max
fSCL SCL clock frequency [2] 0 100 0 400 kHz
tBUF bus free time between STOP condition 4.7 - 1.3 - µs
and START condition
tHD;STA START condition hold time 4.0 - 0.6 - µs
tSU;STA START condition set-up time 4.7 - 0.6 - µs
tSU;STO STOP condition set-up time 4.7 - 0.6 - µs
tHD;DAT data hold time 0 - 0 - ns
tVD;ACK data valid acknowledge time - 0.6 - 0.6 µs
tVD;DAT data valid time SCL LOW to - 0.6 - 0.6 ns
data out valid
tSU;DAT data set-up time 250 - 150 - ns
tLOW SCL LOW time 4.7 - 1.3 - µs
tHIGH SCL HIGH time 4.0 - 0.6 - µs
tf fall time SDA and SCL - 300 - 300 ns
tr rise time SDA and SCL - 1000 - 300 ns
tSP pulse width of spikes which must be - 50 - 50 ns
suppressed by the input filter
tId1 I2C-bus GPIO output valid time [3] 0.5 - 0.5 - µs
td2 I2C-bus modem input interrupt valid time 0.2 - 0.2 - µs
td3 I2C-bus modem input interrupt clear time 0.2 - 0.2 - µs
td4 I2C input pin interrupt valid time 0.2 - 0.2 - µs
td5 I2C input pin interrupt clear time 0.2 - 0.2 - µs
td6 I2C-bus receive interrupt valid time 0.2 - 0.2 - µs
td7 I2C-bus receive interrupt clear time 0.2 - 0.2 - µs
td8 I2C-bus transmit interrupt clear time 1.0 - 0.5 - µs
td15 SCL delay time after reset [4] 3 - 3 - µs

[1] A detailed description of the I2C-bus specification, with applications, is given in brochure “The I2C-bus and how to use it”. This brochure
may be ordered using the code 9398 393 40011.
[2] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
[3] Only applicable to the SC16IS750 and SC16IS760.
[4] 2 X1 clocks or 3 µs, whichever is less.

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 47 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

RESET
td15

SCL
002aab437

Fig 25. SCL delay after reset

START bit 7 bit 0 STOP

bit 6 acknowledge
protocol condition MSB LSB condition
(A6) (A)
(S) (A7) (R/W) (P)

tSU;STA tLOW tHIGH

1/f
SCL

SCL

tBUF tf
tr tSP

SDA

tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO

002aab489

Rise and fall times refer to VIL and VIH.

Fig 26. I2C-bus timing diagram

SDA SLAVE ADDRESS W A A IOSTATE REG. A DATA A

td1

GPIOn
002aab255

Fig 27. Write to output (SC16IS750 and SC16IS760 only)

ACK to master

SDA SLAVE ADDRESS W A AMSR REGISTER A S SLAVE ADDRESS R A DATA A

IRQ

td2 td3

MODEM pin
002aab256

Fig 28. Modem input pin interrupt (SC16IS750 and SC16IS760 only)

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 48 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

ACK from slave ACK from slave ACK from master

SDA SLAVE ADDRESS W A A IOSTATE REG. A S SLAVE ADDRESS R A DATA A P

IRQ

td4 td5

GPIOn
002aab257

Fig 29. GPIO pin interrupt (SC16IS750 and SC16IS760 only)

next
start stop start
bit bit bit

RX D0 D1 D2 D3 D4 D5 D6 D7

td6

IRQ

002aab258

Fig 30. Receive interrupt

SDA SLAVE ADDRESS W A A RHR A S SLAVE ADDRESS R A DATA A P

IRQ

td7 002aab259

Fig 31. Receive interrupt clear

SDA SLAVE ADDRESS W A ATHR REGISTER A DATA A

IRQ

td8
002aab260

Fig 32. Transmit interrupt clear

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 49 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 38: fXTAL dynamic characteristics

VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = −40 °C to +85 °C
Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit
Min Max Min Max
tw1, tw2 clock pulse duration 10 - 6 - ns
fXTAL oscillator/clock frequency [1] [2] - 48 - 80 MHz

[1] Applies to external clock, crystal oscillator max. 24 MHz.

1
[2] f XTAL = -------
t w3

tw2 tw1

EXTERNAL
CLOCK

tw3 002aaa112

1
f XTAL = -------
t 3w

Fig 33. External clock timing

Table 39: SC16IS740/750 SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = −40 °C to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
All output load = 25 pF, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
tTR CS HIGH to SO 3-state delay time CL = 100 pF - - 100 ns
tCSS CS to SCLK setup time 100 - - ns
tCSH CS to SCLK hold time 20 - - ns
tDO SCLK fall to SO valid delay time CL = 100 pF - - 100 ns
tDS SI to SCLK setup time 100 - - ns
tDH SI to SCLK hold time 20 - - ns
tCP SCLK period tCL + tCH 250 - - ns
tCH SCLK HIGH time 100 - - ns
tCL SCLK LOW time 100 - - ns
tCSW CS HIGH pulse width 200 - - ns
td9 SPI output data valid time 200 - - ns
td10 SPI modem output data valid time 200 - - ns
td11 SPI transmit interrupt clear time 200 - - ns
td12 SPI modem input interrupt clear time 200 - - ns
td13 SPI interrupt clear time 200 - - ns
td14 SPI receive interrupt clear time 200 - - ns

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 50 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 40: SC16IS760 SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = −40 °C to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
All output load = 25 pF, unless otherwise specified.
Symbol Parameter Conditions VDD = 2.5 V VDD = 3.3 V Unit
Min Max Min Max
tTR CS HIGH to SO 3-state delay time CL = 100 pF - 100 - 100 ns
tCSS CS to SCLK setup time 100 - 100 - ns
tCSH CS to SCLK hold time 20 - 20 - ns
tDO SCLK fall to SO valid delay time CL = 100 pF - 25 - 20 ns
tDS SI to SCLK setup time 10 - 10 - ns
tDH SI to SCLK hold time 10 - 10 - ns
tCP SCLK period tCL + tCH 83 - 67 - ns
tCH SCLK HIGH time 30 - 25 - ns
tCL SCLK LOW time 30 - 25 - ns
tCSW CS HIGH pulse width 200 - 200 - ns
td9 SPI output data valid time 200 - 200 - ns
td10 SPI modem output data valid time 200 - 200 - ns
td11 SPI transmit interrupt clear time 200 - 200 - ns
td12 SPI modem input interrupt clear time 200 - 200 - ns
td13 SPI interrupt clear time 200 - 200 - ns
td14 SPI receive interrupt clear time 200 - 200 - ns

CS

tCSH tCL tCH tCSW

tCSS tCSH

SCLK

tDH
tDS

SI

tDO tTR

SO

002aab066

Fig 34. Detailed SPI-bus timing

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 51 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

CS

SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0

td9
GPIOx
002aab438

R/W = 0; A[3:0] = IOState (0x0B); CH1 = 0, CH0 = 0

Fig 35. SPI write IOState to GPIO switch (SC16IS750 and SC16IS760 only)

CS

SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0

td10
DTR (GPIO5)
002aab439

R/W = 0; A[3:0] = MCR (0x04); CH1 = 0, CH0 = 0

Fig 36. SPI write MCR to DTR output switch (SC16IS750 and SC16IS760 only)

CS

SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0

SO
td11
IRQ
002aab440

R/W = 0; A[3:0] = THR (0x00); CH1 = 0, CH0 = 0

Fig 37. SPI write THR to clear TX INT

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 52 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

CS

SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X

SO D7 D6 D5 D4 D3 D2 D1 D0
td12
IRQ
002aab441

R/W = 1; A[3:0] = MSR (0x06); CH1 = 0, CH0 = 0

Fig 38. Read MSR to clear modem INT (SC16IS750 and SC16IS760 only)

CS

SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X

SO D7 D6 D5 D4 D3 D2 D1 D0
td13
IRQ
002aab442

R/W = 1; A[3:0] = IOState (0x0B); CH1 = 0, CH0 = 0

Fig 39. Read IOState to clear GPIO INT (SC16IS750 and SC16IS760 only)

CS

SCLK

SI R/W A3 A2 A1 A0 CH1 CH0 X

SO D7 D6 D5 D4 D3 D2 D1 D0

td14
IRQ
002aab443

R/W = 1; A[3:0] = RHR (0x00); CH1 = 0, CH0 = 0

Fig 40. Read RHR to clear RX INT

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 53 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

15. Package outline

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

D E A
X

y HE v M A

16 9

Q
A2 (A 3)
A
A1
pin 1 index

θ
Lp
L
1 8
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
o
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8
mm 1.1 0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT403-1 MO-153
03-02-18

Fig 41. Package outline SOT403-1 (TSSOP16)

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 54 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm SOT616-3

D B A

terminal 1
index area
A
A1
E c

detail X

e1 C
1/2 e
y1 C y
e b v M C A B
7 12 w M C
L
13
6
e

Eh e2

1/2 e

1
18

terminal 1
index area 24 19
Dh X

0 2.5 5 mm

scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1
max.

mm 0.05 0.30 4.1 2.75 4.1 2.75 0.5

1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1
0.00 0.18 3.9 2.45 3.9 2.45 0.3

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

04-11-19
SOT616-3 --- MO-220 ---
05-03-10

Fig 42. Package outline SOT616-3 (HVQFN24)

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 55 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

D E A
X

y HE v M A

24 13

Q
A2 (A 3) A
A1
pin 1 index

θ
Lp
L
1 12
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.

mm
0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o
1.1 0.25 0.65 1 0.2 0.13 0.1
0.05 0.80 0.19 0.1 7.7 4.3 6.2 0.50 0.3 0.2 0o

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT355-1 MO-153
03-02-19

Fig 43. Package outline SOT355-1 (TSSOP24)

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 56 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

16. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be totally safe, it is desirable to take precautions appropriate to handling MOS
devices. Advice can be found in Data Handbook IC24 under “Handling MOS devices”.

17. Soldering

17.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

17.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

17.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically

developed.

If wave soldering is used the following conditions must be observed for optimal results:
9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 57 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

17.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.

17.5 Package related soldering information

Table 41: Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1] Soldering method
Wave Reflow [2]
BGA, HTSSON..T [3],
LBGA, LFBGA, SQFP, not suitable suitable
SSOP..T [3], TFBGA, VFBGA, XSON
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable [4] suitable
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
PLCC [5], SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended [5] [6] suitable
SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable
CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.

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Product data sheet Rev. 01 — 4 January 2006 58 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

18. Abbreviations
Table 42: Abbreviations
Acronym Description
CPU Central Processing Unit
FIFO First In, First Out
GPIO General Purpose Input/Output
I2C-bus Inter IC bus
IrDA Infrared Data Association
LCD Liquid Crystal Display
POR Power-On Reset
SIR Serial InfraRed
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver/Transmitter

19. Revision history

Table 43: Revision history
Document ID Release date Data sheet status Change Order number Supersedes
notice
SC16IS740_750_760_1 20060104 Product data sheet - 9397 750 14832 -

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Product data sheet Rev. 01 — 4 January 2006 59 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

20. Data sheet status

Level Data sheet status [1] Product status [2] [3] Definition
I Objective data Development This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

21. Definitions customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is Right to make changes — Philips Semiconductors reserves the right to
extracted from a full data sheet with the same type number and title. For make changes in the products - including circuits, standard cells, and/or
detailed information see the relevant data sheet or data handbook. software - described or contained herein in order to improve design and/or
Limiting values definition — Limiting values given are in accordance with performance. When the product is in full production (status ‘Production’),
the Absolute Maximum Rating System (IEC 60134). Stress above one or relevant changes will be communicated via a Customer Product/Process
more of the limiting values may cause permanent damage to the device. Change Notification (CPCN). Philips Semiconductors assumes no
These are stress ratings only and operation of the device at these or at any responsibility or liability for the use of any of these products, conveys no
other conditions above those given in the Characteristics sections of the license or title under any patent, copyright, or mask work right to these
specification is not implied. Exposure to limiting values for extended periods products, and makes no representations or warranties that these products are
may affect device reliability. free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
23. Trademarks
Notice — All referenced brands, product names, service names and
22. Disclaimers trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

24. Contact information

For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14832 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet Rev. 01 — 4 January 2006 60 of 61

Philips Semiconductors SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

25. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 8.17 Programmable I/O pins State Register
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 (IOState). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 8.18 I/O Interrupt Enable Register (IOIntEna) . . . . 33
2.2 I2C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2 8.19 I/O Control register (IOControl) . . . . . . . . . . . 34
2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8.20 Extra Features Control Register (EFCR) . . . . 35
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 RS-485 features . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 9.1 Auto RS-485 RTS control. . . . . . . . . . . . . . . . 35
9.2 RS-485 RTS output inversion. . . . . . . . . . . . . 36
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
9.3 Auto RS-485. . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 9.3.1 Normal multidrop mode . . . . . . . . . . . . . . . . . 36
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3.2 Auto address detection. . . . . . . . . . . . . . . . . . 36
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 2
I C-bus operation . . . . . . . . . . . . . . . . . . . . . . 37
7 Functional description . . . . . . . . . . . . . . . . . . . 9 10.1 Data transfers. . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.2 Addressing and transfer formats . . . . . . . . . . 38
7.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 9 10.3 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10.4 Use of sub-addresses . . . . . . . . . . . . . . . . . . 41
7.2.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3 Software flow control . . . . . . . . . . . . . . . . . . . 11
12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.1 RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.3.2 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Static characteristics . . . . . . . . . . . . . . . . . . . 45
7.4 Hardware reset, Power-On Reset (POR) and 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 47
software reset . . . . . . . . . . . . . . . . . . . . . . . . . 14 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 54
7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 Handling information . . . . . . . . . . . . . . . . . . . 57
7.5.1 Interrupt mode operation . . . . . . . . . . . . . . . . 16
17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.5.2 Polled mode operation . . . . . . . . . . . . . . . . . . 16
17.1 Introduction to soldering surface mount
7.6 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.7 Break and time-out conditions . . . . . . . . . . . . 17
17.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 57
7.8 Programmable baud rate generator . . . . . . . . 17
17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 57
8 Register descriptions . . . . . . . . . . . . . . . . . . . 20 17.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 58
8.1 Receive Holding Register (RHR) . . . . . . . . . . 22 17.5 Package related soldering information . . . . . . 58
8.2 Transmit Holding Register (THR) . . . . . . . . . . 22
18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 23
8.4 Line Control Register (LCR) . . . . . . . . . . . . . . 24 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 59
8.5 Line Status Register (LSR) . . . . . . . . . . . . . . . 26 20 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 60
8.6 Modem Control Register (MCR) . . . . . . . . . . . 27 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.7 Modem Status Register (MSR). . . . . . . . . . . . 28 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.8 Interrupt Enable Register (IER) . . . . . . . . . . . 29 23 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.9 Interrupt Identification Register (IIR). . . . . . . . 30
24 Contact information . . . . . . . . . . . . . . . . . . . . 60
8.10 Enhanced Features Register (EFR) . . . . . . . . 31
8.11 Division registers (DLL, DLH) . . . . . . . . . . . . . 31
8.12 Transmission Control Register (TCR) . . . . . . . 32
8.13 Trigger Level Register (TLR). . . . . . . . . . . . . . 32
8.14 Transmitter FIFO Level register (TXLVL) . . . . 32
8.15 Receiver FIFO Level register (RXLVL) . . . . . . 33
8.16 Programmable I/O pins Direction register
(IODir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

© Koninklijke Philips Electronics N.V. 2006

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 4 January 2006
Document number: 9397 750 14832
Published in The Netherlands