USB controller The USB controller provides the hardware to interface a USB link to a data flow stored in a double

port memory (DPRAM). The USB controller requires a 48 MHz 0.25% reference clock (for Full-Speed operation), which is the output of an internal PLL. The PLL generates the internal high frequency (48 MHz) clock for USB interface, the PLL input is generated from an external lower frequency (the crystal oscillator or external clock input pin from XTAL1; to satisfy the USB frequency accuracy and jitter, only this clock source allows proper functionnality of the USB controller). The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed) bit clock from the received USB differential data and to transmit data according to full or low speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus. To comply with the USB Electrical specification, USB Pads (D+ or D-) should be powered within the 3.0 to 3.6V range. As AT90USB64/128 can be powered up to 5.5V, an internal regulator provides the USB pads power supply. Figure 21-1. USB controller Block Diagram overview Host / OTG mode Figure 21-7. Host/OTG application with 3.0V to 3.6 I/O Figure 21-8. Host/OTG application with 5V I/O Design guidelines Serial resistors on USB Data lines must have 22 Ohms value (+/- 5%). Traces from the input USB receptable (or from the cable connection in the case of a tethered device) to the USB microcontroller pads should be as short as possibles, and follow differential traces routing rules (same length, as near as possible, avoid vias accumulation). Voltage transcient / ESD suppressors may also be used to prevent USB pads to be damaged by external disturbances. Ucap capacitor should be 1F (+/- 10%) for correct operation. A 10F capacitor is highly recommended on VBUS line 21.4 General Operating Modes 21.4.1 Introduction After a hardware reset, the USB controller is disabled. When enabled, the USB controller has to run the Device Controller or the Host Controller. This is performed using the USB ID detection. If the ID pin is not connected to ground, the USB ID bit is set by hardware (internal pull up on the UID pad) and the USB Device controller is selected. The ID bit is cleared by hardware when a low level has been detected on the ID pin. The Device controller is then disabled and the Host controller enabled.

The software anyway has to select the mode (Host, Device) in order to access to the Device controller registers or to the Host controller registers, which are multiplexed. For example, even if the USB controller has detected a Device mode (pin ID high), the software shall select the device mode (bit HOST cleared), otherwise it will access to the host registers. This is also true for the Host mode. Note: For the AT90USB646/1286 products the Host mode is not included in the USB controller, and the ID pin is not used and should be configured and used as a general I/O. 21.7 Memory management The controller does only support the following memory allocation management. The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/End-point 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order. The reservation of a Pipe or an Endpoint ki is done when its ALLOC bit is set. Then, the hardware allocates the memory and inserts it between the Pipe/Endpoints ki-1 and ki+1. The ki+1 Pipe/Endpoint memory slides up and its data is lost. Note that the ki+2 and upper Pipe/Endpoint memory does not slide. Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the ki+1 Pipe/Endpoint memory automatically slides down. Note that the ki+2 and upper Pipe/Endpoint memory does not slide. The following figure illustrates the allocation and reorganization of the USB memory in a typical example: Table 21-1. Allocation and reorganization USB memory flow

First, Pipe/Endpoint 0 to Pipe/Endpoint 5 are configured, in the growing order. The memory of each is reserved in the DPRAM. Then, the Pipe/Endpoint 3 is disabled (EPEN=0), but its memory reservation is internally kept by the controller. Its ALLOC bit is cleared: the Pipe/Endpoint 4 slides down, but the Pipe/Endpoint 5 does notslide. Finally, if the firmware chooses to reconfigure the Pipe/Endpoint 3, with a bigger size. The controller reserved the memory after the endpoint 2 memory and automatically slide the Pipe/Endpoint 4. The Pipe/Endpoint 5 does not move and a memory conflict appear, in that both Pipe/Endpoint 4 and 5 use a common area. The data of those endpoints are potentially lost. Note that: the data of Pipe/Endpoint 0 are never lost whatever the activation or deactivation of the higher Pipe/Endpoint. Its data is lost if it is deactivated.

 Deactivate and reactivate the same Pipe/Endpoint with the same parameters does not lead to a slide of the higher endpoints. For those endpoints, the data are preserved. CFGOK is set by hardware even in the case where there is a conflict in the memory allocation. 21.10 Plug-in detection The USB connection is detected by the VBUS pad, thanks to the following architecture: Figure 21-16. Plug-in Detection Input Block Diagram

The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level : The Session_valid signal is active high when the voltage on the VBUS pad is higher or equal to 1.4V. If lower than 1.4V, the signal is not active. The Vbus_valid signal is active high when the voltage on the VBUS pad is higher or equal to 4.4V. If lower than 4.4V, the signal is not active. The VBUS status bit is set when VBUS is greater than Vbus_valid. The VBUS status bit is cleared when VBUS falls below Session_valid (hysteresis behavior). The VBUSTI flag is set each time the VBUS bit state changes. 21.10.2 Host mode The Host must use the UVCON pin to drive an external power switch or regulator that powers the Vbus line. The UVCON pin is automatically asserted and set high by hardware when UVCONE and VBUSREQ bits are set by firmware. If a device connects (pull-up on DP or DM) within 300ms of Vbus delivery, the DCONNI flag will rise. But, once VBUSREQ bit has been set, if no peripheral connection is detected within 300ms, the BCERRI flag (and interrupt) will rise and Vbus delivery will be stopped (UVCON cleared). If that behavior represents a limitation for the Host application, the following work-around may be used : 1. UVCONE and VBUSREQ must be cleared 2. VBUSHWC must be set (to disable hardware control of UVCON pin) 3. PORTE,7 pin (alternate function of UVCON pin) must be set by firmware 4. a device connection will be detected thanks to the SRPI flag (that may usually be used to detect a DP/DM pulse sent by an OTG B-Device that requests a new session)

21.11 ID detection The ID pin transition is detected thanks to the following architecture:

Figure 21-17. ID Detection Input Block Diagram

The ID pin can be used to detect the USB mode (Peripheral or Host) or software selected. This allows the UID pin to be used has general purpose I/O even when USB interface is enable. When the UID pin is selected, by default, (no A-plug or B-plug), the macro is in the Peripheral mode (internal pull-up). The IDTI interrupt is triggered when a A-plug (Host) is plugged or unplugged. The interrupt is not triggered when a B-plug (Periph) is plugged or unplugged. ID detection is independant of USB global interface enable. 21.12 Registers description 21.12.1 UHWCON USB general registers

7 UIMOD: USB Mode Bit This bit has no effect when the UIDE bit is set (external UID pin activated). Set to enable the USB device mode. Clear to enable the USB host mode. 6 UIDE: UID pin Enable Set to enable the USB mode selection (peripheral/host) through the UID pin. Clear to enable the USB mode selection (peripheral/host) with UIMOD bit register. UIDE should be modified only when the USB interface is disabled (USBE bit cleared). 5 Reserved 4 UVCONE: UVCON pin Enable Set to enable the UVCON pin control. Clear to disable the UVCON pin control. This bit should be set only when the USB interface is enable. 3-1 Reserved 0 UVREGE: USB pad regulator Enable Set to enable the USB pad regulator. Clear to disable the USB pad regulator. USBCON

7 USBE: USB macro Enable Bit Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the USB transceiver and to disable the USB controller clock inputs.

 6 HOST: HOST Bit Set to enable the Host mode. Clear to enable the device mode. 5 FRZCLK: Freeze USB Clock Bit Set to disable the clock inputs (the Resume Detection is still active). This reduces the power consumption. Clear to enable the clock inputs. 4 OTGPADE: OTG Pad Enable Set to enable the OTG pad. Clear to disable the OTG pad. The OTG pad is actually the VBUS pad. Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the USB macro is disabled. This pad must be enabled in both Host and Device modes in order to allow USB operation (attaching, transmitting...). 3-2 Reserved 1 IDTE: ID Transition Interrupt Enable Bit Set this bit to enable the ID Transition interrupt generation. Clear this bit to disable the ID Transition interrupt generation. 0 VBUSTE: VBUS Transition Interrupt Enable Bit Set this bit to enable the VBUS Transition interrupt generation. Clear this bit to disable the VBUS Transition interrupt generation. USBSTA

7-4 - Reserved 3 SPEED: Speed Status Flag This should be read only when the USB controller operates in host mode, in device mode the value read from this bit is undetermined. Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the controller is in LOW-SPEED mode. 2 Reserved 1 ID: IUD pin Flag The value read from this bit indicates the state of the UID pin. 0 VBUS: VBus Flag The value read from this bit indicates the state of the VBUS pin. This bit can be used in device mode to monitor the USB bus connection state of the appication. See Section 21.10, page 259 for more details. USBINT USBINT

7-2 - Reserved 1 IDTI: D Transition Interrupt Flag Set by hardware when a transition (high to low, low to high) has been detected on the UID pin. Shall be cleared by software. 0 VBUSTI: IVBUS Transition Interrupt Flag Set by hardware when a transition (high to low, low to high) has been detected on the VBUS pad.

OTGCON

7-6 - Reserved 5 HNPREQ: HNP Request Bit Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP when the controller is in the Host mode (A). Clear otherwise. 4 SRPREQ: SRP Request Bit Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the controller is initiating a SRP. 3 SRPSEL: SRP Selection Bit Set to choose VBUS pulsing as SRP method. Clear to choose data line pulsing as SRP method. 2 VBUSHWC: VBus Hardware Control Bit Set to disable the hardware control over the UVCON pin. Clear to enable the hardware control over the UVCON pin. See for more details 1 VBUSREQ: VBUS Request Bit Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit shall be used when the controller is in the Host mode. Cleared by hardware when VBUSRQC is set. 0 VBUSRQC: VBUS Request Clear Bit Set to deassert the UVCON pin in order to enable the VBUS power supply generation. This bit shall be used when the controller is in the Host mode. Cleared by hardware immediately after the set. OTGTCON

7 Reserved 6-5 PAGE: Timer page access Bit Set/clear to access a special timer register. See Section 21.9, page 259 for more details. 4-3 - Reserved 1-0 VALUE: Value Bit Set to initialize the new value of the timer. See Section 21.9, page 259 for more details. OTGIEN

7-6 - Reserved 5 STOE: Suspend Time-out Error Interrupt Enable Bit Set to enable the STOI interrupt. Clear to disable the STOI interrupt. 4 HNPERRE: HNP Error Interrupt Enable Bit Set to enable the HNPERRI interrupt. Clear to disable the HNPERRI interrupt. 3 ROLEEXE: Role Exchange Interrupt Enable Bit Set to enable the ROLEEXI interrupt. Clear to disable the ROLEEXI interrupt.

 2 BCERRE: B-Connection Error Interrupt Enable Bit Set to enable the BCERRI interrupt. Clear to disable the BCERRI interrupt. 1 VBERRE: VBus Error Interrupt Enable Bit Set to enable the VBERRI interrupt. Clear to disable the VBERRI interrupt. 0 SRPE: SRP Interrupt Enable Bit Set to enable the SRPI interrupt. Clear to disable the SRPI interrupt. OTGINT

7-6 - Reserved 5 STOI: Suspend Time-out Error Interrupt Flag Set by hardware when a time-out error (more than 150 ms) has been detected after a suspend. Shall be cleared by software. 4 HNPERRI: HNP Error Interrupt Flag Set by hardware when an error has been detected during the protocol. Shall be cleared by software. 3 ROLEEXI: Role Exchange Interrupt Flag Set by hardware when the USB controller has successfully swapped its mode, due to an HNP negotiation: Host to Device or Device to Host. However the mode selection bit (Host/Device) is unchanged and must be changed by firmware in order to reach the correct RAM locations and events bits. Shall be cleared by software. 2 BCERRI: B-Connection Error Interrupt Flag Set by hardware when an error occur during the B-Connection (i.e. if Peripheral has not connected after 300ms of Vbus delivery request). Shall be cleared by software. 1 VBERRI: V-Bus Error Interrupt Flag Set by hardware when a drop on VBus has been detected. Shall be cleared by software. 0 SRPI: SRP Interrupt Flag Set by hardware when a SRP has been detected. Shall be used in the Host mode only. Shall be cleared by software. 22.18 Registers 22.18.1 UDCON UDINT UDIEN UDADDR UDFNUMH UDFNUML UDMFN 22.18.2 UENUM UERST UECONX USB device endpoint registers USB device general registers

UECFG0X UECFG1X UESTA0X UESTA1X UEINTX UEIENX UEDATX UEBCHX UEBCLX UEINT 23. USB Host Operating Modes This mode is available only on AT90USB647/1287 products. 23.1 Pipe description For the USB Host controller, the term of Pipe is used instead of Endpoint for the USB Device controller. A Host Pipe corresponds to a Device Endpoint, as described in the USB specification: Figure 23-1. Pipes and Endpoints in a USB system

In the USB Host controller, a Pipe will be associated to a Device Endpoint, considering the Device Configuration Descriptors. 23.2 Detach The reset value of the DETACH bit is 1. Thus, the firmware has the responsibility of clearing this bit before switching to the Host mode (HOST set). 23.3 Power-on and Reset The next diagram explains the USB host controller main states on power-on: Figure 23-2. USB host controller states after reset.

USB host controller state after an hardware reset is Reset. When the USB controller is enabled and the USB Host controller is selected, the USB controller is in Idle state. In this state, the USB Host controller waits for the Device connection, with a minimum power consumption. The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to enter in Host Ready state. The Host controller enters in Suspend state when the USB bus is in Suspend state, i.e. when the Host controller doesnt generate the Start of Frame. In this state, the USB consumption is minimum. The Host controller exits to the Suspend state when starting to generate the SOF over the USB line. 23.4 Device Detection A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In other words, when the USB Host Controller detects the Device pull-up on the D+ line. To enable this detection, the Host Controller has to provide the Vbus power supply to the Device. The Device Disconnection is detected by the USB Host controller when the USB Idle correspond to D+ and D- low on the USB line. 23.5 Pipe Selection Prior to any operation performed by the CPU, the Pipe must first be selected. This is done by setting PNUM2:0 bits (UPNUM register) with the Pipe number which will be managed by the CPU. The CPU can then access to the various Pipe registers and data. 23.6 Pipe Configuration The following flow must be respected in order to activate a Pipe: Figure 23-3. Pipe activation flow:

Once the Pipe is activated (EPEN set) and, the hardware is ready to send requests to the Device. When configured (CFGOK = 1), only the Pipe Token (PTOKEN) and the polling interval for Interrupt pipe can be modified. A Control type pipe supports only 1 bank. Any other value will lead to a configuration error (CFGOK = 0).

A clear of PEN will reset the configuration of the Pipe. All the corresponding Pipe registers are reset to there reset values. Please refers to the Memory Management chapter for more details. Note: The firmware has to configure the Default Control Pipe with the following parameters: Type: Control Token: SETUP Data bank: 1 Size: 64 Bytes The firmware asks for 8 bytes of the Device Descriptor sending a GET_DESCRIPTOR request. These bytes contains the MaxPacketSize of the Device default control endpoint and the firmware reconfigures the size of the Default Control Pipe with this size parameter. 23.8 Address Setup Once the Device has answer to the first Host requests with the default address (0), the Host assigns a new address to the device. The Host controller has to send a USB reset to the device and perform a SET ADDRESS control request, with the new address to be used by the Device. This control request ended, the firmware write the new address into the UHADDR register. All following requests, on every Pipes, will be performed using this new address. When the Host controller send a USB reset, the UHADDR register is reset by hardware and the following Host requests will be performed using the default address (0). 23.10 USB Pipe Reset The firmware can reset a Pipe using the pipe reset register. The configuration of the pipe and the data toggle remains unchanged. Only the bank management and the status bits are reset to their initial values. To completely reset a Pipe, the firmware has to disable and then enable the pipe. 23.11 Pipe Data Access In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM register and performs read or write action on the UPDATX register. 23.13 OUT Pipe management The Pipe must be configured and not frozen first. Note: if the firmware decides to switch to suspend mode (clear SOFEN) even if a bank is ready to be sent, the USB controller will automatically exit from Suspend mode and the bank will be sent. The TXOUT bit is set by hardware when the current bank becomes free. This triggers an interrupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the next bank. 23.14 IN Pipe management The Pipe must be configured first. When the Host requires data from the device, the firmware has to determine first the IN mode to use using the INMODE bit: INMODE = 0. The INRQX register is taken in account. The Host controller will perform (INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This mode avoids to have extra IN requests on a Pipe. INMODE = 1. The USB controller will perform infinite IN request until the firmware freezes the Pipe.

The IN request generation will start when the firmware clear the PFREEZE bit. Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an interrupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the status of the new bank. 23.16 Registers 23.16.1 UHCON General USB Host registers

7-3 - Reserved 2 - RESUME - Send USB Resume Set this bit to generate a USB Resume on the USB bus. Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect. This bit should be set only when the start of frame generation is enable (SOFEN bit set). 1 - RESET - Send USB Reset Set this bit to generate a USB Reset on the USB bus. Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect. Refer to the USB reset section for more details. 0 - SOFEN - Start Of Frame Generation Enable Set this bit to generate SOF on the USB bus in full speed mode and keep-alive in low speed mode. Clear this bit to disable the SOF generation and to leave the USB bus in Idle state. UHINT

7 - Reserved 6 - HWUPI Host Wake-Up Interrupt. Set by hardware when a non-idle state is detected on the USB bus. This interrupt should be enable only to wake up the CPU core from power down mode. Shall be clear by software to acknowledge the interrupt. Setting by software has no effect. 5 - HSOFI - Host Start Of Frame Interrupt Set by hardware when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is set. When using the host controller in low speed mode, this bit is also set when a keep-alive is sent. Shall be cleared by software to acknowledge the interrupt. Setting by software has no effect. 4 - RXRSMI - Upstream Resume Received Interrupt Set by hardware when an Upstream Resume has been received from the Device. Shall be cleared by software. Setting by software has no effect. 3 - RSMEDI - Downstream Resume Sent Interrupt Set by hardware when a Downstream Resume has been sent to the Device. Shall be cleared by software. Setting by software has no effect. 2 - RSTI - USB Reset Sent Interrupt Set by hardware when a USB Reset has been sent to the Device. Shall be cleared by software. Setting by software has no effect.

 1 - DDISCI Device Disconnection Interrupt Set by hardware when the device has been removed from the USB bus. Shall be cleared by software. Setting by software has no effect. 0 - DCONNI - Device Connection Interrupt Set by hardware when a new device has been connected to the USB bus. Shall be cleared by software. Setting by software has no effect. UHIEN

7 - Reserved 6 - HWUPE - Host Wake-Up Interrupt Enable Set this bit to enable HWUP interrupt. For correct interrupt handle execution, this interrupt should be enable only before entering power-down mode. Clear this bit to disable HWUP interrupt. 5 - HSOFE - Host Start Of frame Interrupt Enable Set this bit to enable HSOF interrupt. Clear this bit to disable HSOF interrupt. 4 - RXRSME -Upstream Resume Received Interrupt Enable Set this bit to enable the RXRSMI interrupt. Clear this bit to disable the RXRSMI interrupt. 3 - RSMEDE - Downstream Resume Sent Interrupt Enable Set this bit to enable the RSMEDI interrupt. Clear this bit to disable the RSMEDI interrupt. 2 - RSTE - USB Reset Sent Interrupt Enable Set this bit to enable the RSTI interrupt. Clear this bit to disable the RSTI interrupt. 1 - DDISCE - Device Disconnection Interrupt Enable Set this bit to enable the DDISCI interrupt. Clear this bit to disable the DDISCI interrupt. 0 - DCONNE - Device Connection Interrupt Enable Set this bit to enable the DCONNI interrupt. Clear this bit to disable the DCONNI interrupt. UHADDR

7 - Reserved 6-0 - HADDR6:0 - USB Host Address These bits contain the address of the USB Device. UHFNUMH

7-4 - Reserved 3-0 - FNUM10:8 - Frame Number The value contained in this register is the current SOF number. This value can be modified by software.

UHFNUML

7-0 - FNUM7:0 - Frame Number The value contained in this register is the current SOF number. This value can be modified by software. UHFLEN

7-0 - FLEN7:0 - Frame Length The value contained the data frame length transmitted. 23.16.2 USB Host Pipe registers UPNUM

7-3 - Reserved 2-0 - PNUM2:0 - Pipe Number Select the pipe using this register. The USB Host registers ended by a X correspond then to this number. This number is used for the USB controller following the value of the PNUMD bit. UPRST

7 - Reserved 6 - P6RST - Pipe 6 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 6. 5 - P5RST - Pipe 5 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 5. 4 - P4RST - Pipe 4 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 4. 3 - P3RST - Pipe 3 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 3. 2 - P2RST - Pipe 2 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 2. 1 - P1RST - Pipe 1 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 1. 0 - P0RST - Pipe 0 Reset Set this bit to 1 and reset this bit to 0 to reset the Pipe 0.

UPCONX

7 - Reserved 6 - PFREEZE - Pipe Freeze Set this bit to Freeze the Pipe requests generation. Clear this bit to enable the Pipe request generation. This bit is set by hardware when: - the pipe is not configured - a STALL handshake has been received on this Pipe - An error occurs on the Pipe (UPINTX.PERRI = 1) - (INRQ+1) In requests have been processed This bit is set at 1 by hardware after a Pipe reset or a Pipe enable. 5 - INMODE - IN Request mode Set this bit to allow the USB controller to perform infinite IN requests when the Pipe is not frozen. Clear this bit to perform a pre-defined number of IN requests. This number is stored in the UIN-RQX register. 4 - Reserved 3 - RSTDT - Reset Data Toggle Set this bit to reset the Data Toggle to its initial value for the current Pipe. Cleared by hardware when proceed. Clearing by software has no effect. 2 - Reserved 1 - Reserved 0 - PEN - Pipe Enable Set to enable the Pipe. Clear to disable and reset the Pipe. UPCFG0X

7-6 - PTYPE1:0 - Pipe Type Select the type of the Pipe: - 00: Control - 01: Isochronous - 10: Bulk - 11: Interrupt 5-4 - PTOKEN1:0 - Pipe Token Select the Token to associate to the Pipe - 00: SETUP - 01: IN - 10: OUT - 11: reserved 3-0 - PEPNUM3:0 - Pipe Endpoint Number Set this field according to the Pipe configuration. Set the number of the Endpoint targeted by the Pipe. This value is from 0 and 15.

UPCFG1X

7 - Reserved 6-4 - PSIZE2:0 - Pipe Size Select the size of the Pipe: - 000: 8 - 001: 16 - 010: 32 - 011: 64 - 100: 128 (only for endpoint 1) - 101: 256 (only for endpoint 1) - 110: Reserved. Do not use this configuration. - 111: Reserved. Do not use this configuration. 3-2 - PBK1:0 - Pipe Bank Select the number of bank to declare for the current Pipe. - 00: 1 bank - 01: 2 banks - 10: invalid - 11: invalid ALLOC Configure Pipe Memory. Set to configure the pipe memory with the characteristics. Clear to update the memory allocation. Refer to the Memory Management chapter for more details. 7 - Reserved The value read from these bits is always 0. Do not set these bits. UPCFG2X

7 - INTFRQ7:0 - Interrupt Pipe Request Frequency These bits are the maximum value in millisecond of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe. UPSTAX

7 - CFGOK - Configure Pipe Memory OK Set by hardware if the required memory configuration has been successfully performed. Cleared by hardware when the pipe is disabled. The USB reset and the reset pipe have no effect on the configuration of the pipe. 6 - OVERFI - Overflow Set by hardware when a the current Pipe has received more data than the maximum length of the current Pipe. An interrupt is triggered if the FLERRE bit is set. Shall be cleared by software. Setting by

software has no effect. 5 - UNDERFI - Underflow Set by hardware when a transaction underflow occurs in the current isochronous or interrupt Pipe. The Pipe cant send the data flow required by the device. A ZLP will be sent instead. An interrupt is triggered if the FLERRE bit is set. Shall be cleared by software. Setting by software has no effect. Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent and the UNDERFI bit is set. 4 - Reserved 3-2 - DTSEQ1:0 - Toggle Sequencing Flag Set by hardware to indicate the PID data of the current bank: 00b Data0 01b Data1 1xb Reserved. For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the current bank. For IN Pipe, this value indicates the last data toggle received on the current bank. 1-0 - NBUSYBK1:0 - Busy Bank Flag Set by hardware to indicate the number of busy bank. For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer. For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device. 00b All banks are free 01b 1 busy bank 10b 2 busy banks 11b Reserved. UPINRQX

7-0 - INRQ7:0 - IN Request Number Before Freeze Enter the number of IN transactions before the USB controller freezes the pipe. The USB controller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed. This register has no effect when the INMODE bit is set (infinite IN requests generation till the pipe is not frozen). UPERRX

7-6 - Reserved 5 - COUNTER1:0 - Error counter This counter is increased by the USB controller each time an error occurs on the Pipe. When this value reaches 3, the Pipe is automatically frozen. Clear these bits by software. 4 - CRC16 - CRC16 Error Set by hardware when a CRC16 error has been detected. Shall be cleared by software. Setting by software has no effect. 3 - TIMEOUT - Time-out Error Set by hardware when a time-out error has been detected. Shall be cleared by software. Setting by software has no effect.

 2 - PID - PID Error Set by hardware when a PID error has been detected. Shall be cleared by software. Setting by software has no effect. 1 - DATAPID - Data PID Error Set by hardware when a data PID error has been detected. Shall be cleared by software. Setting by software has no effect. 0 - DATATGL - Bad Data Toggle Set by hardware when a data toggle error has been detected. Shall be cleared by software. Setting by software has no effect. UPINTX

7 - FIFOCON - FIFO Control For OUT and SETUP Pipe: Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP. Clear to send the FIFO data and to switch the bank. Setting by software has no effect. For IN Pipe: Set by hardware when a new IN message is stored in the current bank, at the same time than RXIN. Clear to free the current bank and to switch to the following bank. Setting by software has no effect. 6 - NAKEDI - NAK Handshake received Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers an interrupt if the NAKEDE bit is set in the UPIENX register. Shall be clear to handshake the interrupt. Setting by software has no effect. 5 - RWAL - Read/Write Allowed OUT Pipe: Set by hardware when the firmware can write a new data into the Pipe FIFO. Cleared by hardware when the current Pipe FIFO is full. IN Pipe: Set by hardware when the firmware can read a new data into the Pipe FIFO. Cleared by hardware when the current Pipe FIFO is empty. This bit is also cleared by hardware when the RXSTALL or the PERR bit is set 4 - PERRI -PIPE Error Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the source of the error. Automatically cleared by hardware when the error source bit is cleared. 3 - TXSTPI - SETUP Bank ready Set by hardware when the current SETUP bank is free and can be filled. This triggers an interrupt if the TXSTPE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. 2 - TXOUTI -OUT Bank ready Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error Set by hardware when a STALL handshake has been received on the current bank of the Pipe.

The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. For Isochronous Pipe: Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if the TXSTPE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. 0 - RXINI - IN Data received Set by hardware when a new USB message is stored in the current bank of the Pipe. This triggers an interrupt if the RXINE bit is set in the UPIENX register. Shall be cleared to handshake the interrupt. Setting by software has no effect. UPIENX

7 - FLERRE - Flow Error Interrupt enable Set to enable the OVERFI and UNDERFI interrupts. Clear to disable the OVERFI and UNDERFI interrupts. 6 - NAKEDE -NAK Handshake Received Interrupt Enable Set to enable the NAKEDI interrupt. Clear to disable the NAKEDI interrupt. 5 - Reserved 4 - PERRE -PIPE Error Interrupt Enable Set to enable the PERRI interrupt. Clear to disable the PERRI interrupt. 3 - TXSTPE - SETUP Bank ready Interrupt Enable Set to enable the TXSTPI interrupt. Clear to disable the TXSTPI interrupt. 2 - TXOUTE - OUT Bank ready Interrupt Enable Set to enable the TXOUTI interrupt. Clear to disable the TXOUTI interrupt. 1 - RXSTALLE - STALL Received Interrupt Enable Set to enable the RXSTALLI interrupt. Clear to disable the RXSTALLI interrupt. 0 - RXINE - IN Data received Interrupt Enable Set to enable the RXINI interrupt. Clear to disable the RXINI interrupt. UPDATX

7-0 - PDAT7:0 - Pipe Data Bits Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM. UPBCHX

7-3 - Reserved 2-0 - PBYCT10:8 - Byte count (high) Bits Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is provided by the UPBCLX register.

UPBCLX

7-0 - PBYCT7:0 - Byte Count (low) Bits Set by the hardware. PBYCT10:0 is: - (for OUT Pipe) increased after each writing into the Pipe and decremented after each byte sent, - (for IN Pipe) increased after each byte received by the host, and decremented after each byte read by the software. UPINT

7 - Reserved 6-0 - PINT6:0 - Pipe Interrupts Bits Set by hardware when an interrupt is triggered by the UPINTX register and if the corresponding endpoint interrupt enable bit is set. Cleared by hardware when the interrupt source is served.