COMPUTER ORGANIZATION AND DESIGN

5th
Edition
The Hardware/Software Interface

Chapter 4
The Processor
 §4.1 Introduction
Introduction
 CPU performance factors
 Instruction count
 Determined by ISA and compiler
 CPI and Cycle time
 Determined by CPU hardware

 We will examine two MIPS implementations

 A simplified version (single-cycle CPU)
 A more realistic version (pipelined CPU)

Chapter 4 — The Processor — 2

Introduction
 The simplified CPU (Single-cycle CPU)
 ALU (Arithmetic Logic Unit)
 Datapath
 Control Signals
 ALU control
 Main control
 Instructions supported
 Memory reference: lw, sw
 Arithmetic/logical: add, sub, and, or, slt
 Control transfer: beq, j
 Simple subset, shows most aspects
Chapter 4 — The Processor — 3
 The ALU (Appendix)
operation

 A 32-bit ALU
a

32 ALU
result

32

32

 First, let’s review Boolean Logic we’ll need

 Multiplexor S

A note: we call this a 2-input mux

C even though it has 3 inputs!
B

Chapter 4 — The Processor — 4

 The ALU
 1-bit and/or

CarryIn

 1-bit addition: a
Sum
cout = a b + a cin + b cin b

sum = a xor b xor cin

CarryOut

 How could we build a 1-bit ALU for add, and, and or?
 How could we build a 32-bit ALU?

Chapter 4 — The Processor — 5

The ALU – ADD function
32-bit ALU

1-bit
ALU

Chapter 4 — The Processor — 6

The ALU – SUB function
 What about subtraction (a-b)?  a + (-b)
 How do we negate b?
 Two’s complement approach: invert every bit and add 1

 A very clever solution:

Note: need Cin0 = 1 for sub

Combining Binvert and Cin0

Chapter 4 — The Processor — 7

 The ALU - NOR function
 NOR function
 How do we get “a NOR b” ?
(DeMorgan’s law)

Chapter 4 — The Processor — 8

 The ALU – SLT function
 Slt produces a 1 if rs < rt and 0 otherwise;
most significant bit
 use subtraction: (a-b) < 0 implies a < b
all other bits

(sign-bit value)

Chapter 4 — The Processor — 9

The ALU - SLT

Control lines
Ainv Binv Operation Function
0 0 00 and
0 0 01 or
0 0 10 add
0 1 10 sub
0 1 11 slt
1 1 00 nor

Chapter 4 — The Processor — 10

 The ALU

Control lines
Ainv Binv Operation Function
0 0 00 and
0 0 01 or
0 0 10 add
0 1 10 sub
0 1 11 slt
1 1 00 nor

Chapter 4 — The Processor — 11

 ALU- Test for equality (for beq)
• Use subtraction:
(a-b) = 0 implies a = b
Note: zero is
 Notice control lines: a 1 when the
result is zero!
0000 = and
0001 = or
0010 = add
0110 = subtract
0111 = slt
1100 = NOR

Note: we only perform the first five

functions in the implementation
later

Chapter 4 — The Processor — 12

CPU Overview
Instruction Execution
 PC  instruction memory, fetch instruction
 Register numbers  register file, read registers
 Depending on instruction class
 Use ALU to calculate
 Arithmetic/logic result

 Memory address for load/store

 Branch target address

 Access data memory for load/store

 PC  target address or PC + 4

Chapter 4 — The Processor — 13

CPU Overview
• The datapath

Chapter 4 — The Processor — 14

Multiplexers
 Can’t just join
wires together
 Use multiplexers

Chapter 4 — The Processor — 15

Control

Chapter 4 — The Processor — 16

 §4.2 Logic Design Conventions
Logic Design Basics
 Information encoded in binary
 Low voltage = 0, High voltage = 1
 One wire per bit
 Multi-bit data encoded on multi-wire buses
 Combinational element
 Operate on data
 Output is a function of input
 State (sequential) elements
 Store information

Chapter 4 — The Processor — 17

Combinational Elements
 AND-gate  Adder A
Y
+
 Y=A&B  Y=A+B B

A
Y
B

 Arithmetic/Logic Unit
 Multiplexer  Y = F(A, B)
 Y = S ? In1 : In0
A
In0 M
u Y ALU Y
In1 x
B
S F

Chapter 4 — The Processor — 18

Sequential Elements
 Register: stores data in a circuit
 Uses a clock signal to determine when to
update the stored value
 Edge-triggered: update when Clk changes
from 0 to 1

Clk

D Q
D

Clk
Q

Chapter 4 — The Processor — 19

 Sequential Elements
 Register with write control
 Only updates on clock edge when write
control input is 1
 Used when stored value is required later

Clk

Write
D Q
Write D
Clk
Q

Chapter 4 — The Processor — 20

Clocking Methodology
 Combinational logic transforms data during
clock cycles
 Between clock edges
 Input from state elements, output to state
element
 Longest delay determines clock period

Chapter 4 — The Processor — 21

 §4.3 Building a Datapath
Building a Datapath
 Datapath
 Elements that process data and addresses
in the CPU
 Registers, ALUs, mux’s, memories, …
 We will build a MIPS datapath
incrementally
 Refining the overview design

Chapter 4 — The Processor — 22`

Instruction Fetch

Increment by
4 for next
32-bit instruction
register

Chapter 4 — The Processor — 23

R-Format Instructions
 Read two register operands
 Perform arithmetic/logical operation
 Write register result

Chapter 4 — The Processor — 24

Load/Store Instructions
 Read register operands
 Calculate address using 16-bit offset
 Use ALU, but sign-extend offset
 Load: Read memory and update register
 Store: Write register value to memory

Chapter 4 — The Processor — 25

Branch Instructions
 Read register operands
 Compare operands
 Use ALU, subtract and check Zero output
 Calculate target address
 Sign-extend displacement
 Shift left 2 places (word displacement)
 Add to PC + 4
 Already calculated by instruction fetch

Chapter 4 — The Processor — 26

Branch Instructions
Just
re-routes
wires

Uses the ALU to evaluate the

branch condition and a
Sign-bit wire separate adder to compute the
replicated branch target

Chapter 4 — The Processor — 27

How to combines these together?

Instruction
fetch Load & Store

R-type Beq
Composing the Elements
 First-cut data path does an instruction in
one clock cycle
 Each datapath element can only do one
function at a time
 Hence, we need separate instruction and data
memories
 Use multiplexers where alternate data
sources are used for different instructions

Chapter 4 — The Processor — 29

The Datapath with MUXs and Control Signals

(beq)

(sw)

(R) (lw)

(R)
(lw, sw)

(R, lw)
(lw)

Chapter 4 — The Processor — 30

Difference in the write-register field

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

rd rs rt
add $t0, $t1, $t2
rt rs
write for
lw $t0, 4($t1) R-type
rs rt and load
beq $t0, $t1, L

Chapter 4 — The Processor — 31

Full Datapath

(lw)
rt M
U
rd X

(R)
Chapter 4 — The Processor — 32
A Simple Datapath for MIPS Inst. Set
 A Simple Datapath for MIPS Inst. Set

R-type
add $rd, $rs, $rt
 A Simple Datapath for MIPS Inst. Set

Load
lw $rt, 32($rs)
 A Simple Datapath for MIPS Inst. Set

Branch
beq $rs, $rt, L
 §4.4 A Simple Implementation Scheme
ALU Control
 ALU used for
 Load/Store: F = add
 Branch: F = subtract
 R-type: F depends on funct field
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than (slt)
1100 NOR

Chapter 4 — The Processor — 37

ALU Control
 Assume 2-bit ALUOp derived from opcode
 Combinational logic derives ALU control

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111

Chapter 4 — The Processor — 38

ALU Control (Appendix)
ALUOp Funct field Operation
ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0 C3 C2 C1 C0
0 0 X X X X X X 0010 (lw/sw)
X 1 X X X X X X 0110 (beq)
1 X X X 0 0 0 0 0010 (add)
1 X X X 0 0 1 0 0110 (sub)
1 X X X 0 1 0 0 0000 (AND)
1 X X X 0 1 0 1 0001 (OR)
1 X X X 1 0 1 0 0111 (slt)
The ALU Control

ALU
Control

Instruction [5:0]
ALUOp

Chapter 4 — The Processor — 40

The Main Control Unit
 Control signals derived from instruction

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for sign-extend

read except R-type and add
for load and load

Chapter 4 — The Processor — 41

The Main Control Unit
(set to 0) (set to 1)

Chapter 4 — The Processor — 42

The ALU Control

Chapter 4 — The Processor — 43

Datapath With Control

rs

rt

rd

Chapter 4 — The Processor — 44

 R-Type Instruction

rs

rt

rd

add $rd, $rs, $rt

1 0 0 1 0 0 0 1 0
 Load Instruction

rs

rt

rd

lw $rt, 32($rs)

0 1 1 1 1 0 0 0 0 — 46
 Branch-on-Equal Instr.

rs

rt

rd

beq $rs, $rt, L

x 0 x 0 0 0 1 0 1
The Main Control Unit
 The setting of the control lines:

 The encoding for each of the opcodes of interest:

Chapter 4 — The Processor — 48

Main Control Unit (Appendix)

Chapter 4 — The Processor — 49

Implementing Jumps
Jump Instruction (opcode=2)

 Jump uses word address

 Update PC with concatenation of
 Top 4 bits of old PC Target address
 26-bit jump address PC+4 address 00
31:28 27:2 1:0
 00
 Need an extra control signal decoded from opcode

Chapter 4 — The Processor — 50

Datapath With Jumps Added

Chapter 4 — The Processor — 51

Performance Issues
 Longest delay determines clock period
 Critical path: load instruction
 Instruction memory  register file  ALU 
data memory  register file
 Not feasible to vary period for different
instructions
 Violates design principle
 Making the common case fast
 We will improve performance by pipelining

Chapter 4 — The Processor — 52

 §4.5 An Overview of Pipelining
Pipelining Analogy
 Pipelined laundry: overlapping execution
 Parallelism improves performance

 Four loads:
 Speedup
= 8/3.5 = 2.3
 Non-stop:
 Speedup
= 2n/(0.5n + 1.5) ≈ 4
= number of stages

Chapter 4 — The Processor — 53

MIPS Pipeline
 Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

Chapter 4 — The Processor — 54

 Pipeline Performance
 Assume time for stages is
 100ps for register read or write
 200ps for other stages
 Compare pipelined datapath with single-cycle
datapath
IF ID EX MEM WB
Instr Instr fetch Register ALU op Memory Register Total time
read access write
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 55

Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 56

Pipeline Speedup
 If all stages are balanced
 i.e., all take the same time
 Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
 If not balanced, speedup is less
 Speedup due to increased throughput
 Latency (time for each instruction) does not
decrease

Chapter 4 — The Processor — 57

Pipelining and ISA Design
 MIPS ISA designed for pipelining
 All instructions are 32-bits
 Easier to fetch in one cycle
 c.f. x86: 1- to 17-byte instructions
 Few and regular instruction formats
 Can decode and read registers in one step
 Load/store addressing
 Can calculate address in 3rd stage, access memory
in 4th stage
 Alignment of memory operands
 Memory access takes only one cycle

Chapter 4 — The Processor — 58

Hazards
 Situations that prevent starting the next
instruction in the next cycle
 Structure hazards
 A required resource is busy
 Data hazard
 Need to wait for previous instruction to
complete its data read/write
 Control hazard
 Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 59

Structure Hazards
 Conflict for use of a resource
 hardware cannot support the combination of
instruction in the same clock.
 In MIPS pipeline with a single memory
 Load/store requires data access
 Instruction fetch would have to stall for that cycle

 require separate instr./data memories (or caches)

Structural hazard occurs if

there is only one memory

IF Chapter 4 — The Processor — 60

Data Hazards
 An instruction depends on completion of
data access by a previous instruction
 data that is needed to execute the instruction is
still in the pipeline, not yet available.

 Ex. 1 Ex. 2 ( load-use data hazard )

add $s0, $t0, $t1 lw $s0, 4($t1)
sub $t2, $s0, $t3 sub $t2, $s0, $t3
IF ID EX ME WB IF ID EX ME WB
IF ID EX ME WB IF ID EX ME WB

Chapter 4 — The Processor — 61

Data Hazards - stall
 Stall the instructions (bubble)
 add $s0, $t0, $t1
sub $t2, $s0, $t3

Chapter 4 — The Processor — 62

Data Hazards - Forwarding
 Use result when it is computed
 Don’t wait for it to be stored in a register
 Requires extra connections in the datapath

Chapter 4 — The Processor — 63

Load-Use Data Hazard
 Can’t always avoid stalls by forwarding
 If value not computed when needed
 Can’t forward backward in time!

Chapter 4 — The Processor — 64

Code Scheduling to Avoid Stalls
 Reorder code to avoid use of load result in
the next instruction
 C code for A = B + E; C = B + F;
[3] [0] [1] [4] [0] [2]

lw $t1, 0($t0) lw $t1, 0($t0)

lw $t2, 4($t0) lw $t2, 4($t0)
stall add $t3, $t1, $t2 lw $t4, 8($t0)
sw $t3, 12($t0) add $t3, $t1, $t2
lw $t4, 8($t0) sw $t3, 12($t0)
stall add $t5, $t1, $t4 add $t5, $t1, $t4
sw $t5, 16($t0) sw $t5, 16($t0)
13 cycles 11 cycles

Chapter 4 — The Processor — 65

Control Hazards
 Branch determines flow of control
 Fetching next instruction depends on branch
outcome
 Pipeline can’t always fetch correct instruction
 Still working on ID stage of branch (however, the
branch outcome is determined at EX stage.)
 In MIPS pipeline
 Need to compare registers and compute
target early in the pipeline
 Add hardware to do it in ID stage

Chapter 4 — The Processor — 66

Stall on Branch
 Wait until branch outcome determined
before fetching next instruction
 Assume extra hardware has been added to test
registers and calculate branch address at ID stage

Chapter 4 — The Processor — 67

Branch Prediction
 Longer pipelines can’t readily determine
branch outcome early
 Stall penalty becomes unacceptable
 Predict outcome of branch
 Only stall if prediction is wrong
 In MIPS pipeline
 Can predict branches not taken
 Fetch instruction after branch, with no delay

Chapter 4 — The Processor — 68

MIPS with Predict Not Taken

Prediction
correct

Prediction
incorrect

Chapter 4 — The Processor — 69

More-Realistic Branch Prediction
 Static branch prediction
 Based on typical branch behavior
 Example: loop and if-statement branches
 Predict backward branches taken
 Predict forward branches not taken
 Dynamic branch prediction
 Hardware measures actual branch behavior
 e.g., record recent history of each branch
 Assume future behavior will continue the trend
 When wrong, stall while re-fetching, and update history

Chapter 4 — The Processor — 70

Pipeline Summary
The BIG Picture

 Pipelining improves performance by

increasing instruction throughput
 Executes multiple instructions in parallel
 Each instruction has the same latency
 Subject to hazards
 Structure, data, control
 Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 71
 §4.6 Pipelined Datapath and Control
MIPS Pipelined Datapath

MEM

Right-to-left WB
flow leads to
hazards

Chapter 4 — The Processor — 72

Pipeline registers
 Need registers between stages
 To hold information produced in previous cycle

Chapter 4 — The Processor — 73

Pipeline Operation Diagram
 Cycle-by-cycle flow of instructions through
the pipelined datapath
 “Single-clock-cycle” pipeline diagram
 Shows pipeline usage in a single cycle
 Highlight resources used
 c.f. “multi-clock-cycle” diagram
 Graph of operation over time
 We’ll look at “single-clock-cycle” diagrams
for load & store illustrations.

Chapter 4 — The Processor — 74

Multi-Cycle Pipeline Diagram
 Traditional form

Chapter 4 — The Processor — 75

Multi-Cycle Pipeline Diagram
 Form showing resource usage

Chapter 4 — The Processor — 76

Single-Cycle Pipeline Diagram
 State of pipeline in a given cycle

Chapter 4 — The Processor — 77

 IF for Load, Store, …

Memory[PC] IF/ID
PC+4  PC
PC+4  IF/ID
Note: Shaded left-half: Write Shaded right-half: Read

Chapter 4 — The Processor — 78

 ID for Load, Store, …

Reg[IF/ID.rs]  ID/EX
Reg[IF/ID.rt]  ID/EX
Sign-extend( IF/ID.Instr[15:0] )  ID/EX
IF/ID.pc+4  ID/EX

Chapter 4 — The Processor — 79

 EX for Load

mem-addr = ID/EX.reg[rs]+ID/EX.sign-ext32  EX/MEM

Chapter 4 — The Processor — 80

 MEM for Load

mem-data= Memory[EX/MEM. mem-addr]  MEM/WB

Chapter 4 — The Processor — 81

WB for Load

Wrong
register
number

MEM/WB.mem-data  Reg[ rt ]

Chapter 4 — The Processor — 82

Corrected Datapath for Load

IF/ID.rt -> ID/EX -> EX/MEM -> MEM/WB for lw

How about R-type instruction ?

Chapter 4 — The Processor — 83

Corrected Datapath for Load and R-type

rt

rd

Chapter 4 — The Processor — 84

 EX for Store

mem-addr = ID/EX.reg[rs]+ID/EX.sign-ext32  EX/MEM

Anything else ? See next page

Chapter 4 — The Processor — 85
 MEM for Store

Reg[ rt ]  MEM[EX/MEM. mem-addr]

How to get Reg[rt]? add “ID/EX.Reg[rt]  EX/MEM” to EX stage
Chapter 4 — The Processor — 86
WB for Store

Do nothing at this stage.

Chapter 4 — The Processor — 87

 Pipelined Control (Simplified)
IF ID EX MEM WB

rt

rd

Totally 9 control signals

Chapter 4 — The Processor — 88

Pipelined Control
 Control signals derived from instruction
 As in single-cycle implementation
 Pass control signals along just like the data
 Create control info. at ID stage and then used in appropriate
stage as pipeline move down

Chapter 4 — The Processor — 89

 Pipelined Control

Instr. Execution/address calculation stage Memory access stage control Write-back stage
control lines lines control lines
RegDst ALUOp1 ALUOp0 ALUSrc Branch MemRead MemWrite RegWrite MemtoReg
R-format 1 1 0 0 0 0 0 1 0
lw 0 0 0 1 0 1 0 1 1
sw X 0 0 1 0 0 1 0 X
beq X 0 1 0 1 0 0 0 x

 IF: the control signals to read instruction memory and to write

PC are always asserted for at each cycle, so there is nothing
special to control at this stage.
 ID: As in IF, the same thing happens at every cycle, so no
optional control signals to set.

Chapter 4 — The Processor — 90

Pipelined Control

Chapter 4 — The Processor — 91

 §4.7 Data Hazards: Forwarding vs. Stalling
Data Hazards in ALU Instructions
 Consider this sequence:
sub $2, $1,$3
and $12,$2,$5
or $13,$6,$2
add $14,$2,$2
sw $15,100($2)
 We can resolve hazards with forwarding
 How do we detect when to forward?

Chapter 4 — The Processor — 92

Dependencies & Forwarding

EX/MEM MEM/WB

Chapter 4 — The Processor — 93

Detecting the Need to Forward
 Pass register numbers along pipeline
 e.g., ID/EX.RegisterRs = register number for Rs
sitting in ID/EX pipeline register
 ALU operand register numbers in EX stage
are given by
 ID/EX.RegisterRs, ID/EX.RegisterRt
 Data hazards when
Fwd from
1a. EX/MEM.RegisterRd = ID/EX.RegisterRs EX/MEM
pipeline reg
1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
2a. MEM/WB.RegisterRd = ID/EX.RegisterRs Fwd from
MEM/WB
2b. MEM/WB.RegisterRd = ID/EX.RegisterRt pipeline reg

Chapter 4 — The Processor — 94

Detecting the Need to Forward
 But only if forwarding instruction will write
to a register!
 EX/MEM.RegWrite, MEM/WB.RegWrite
 And only if Rd for that instruction is not
$zero
 EX/MEM.RegisterRd ≠ 0,
MEM/WB.RegisterRd ≠ 0

Chapter 4 — The Processor — 95

Forwarding Conditions
 EX hazard (the sub-and in p.83)
 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
ForwardA = 10
 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
ForwardB = 10
 MEM hazard (the sub-or in p.83)
 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01

Chapter 4 — The Processor — 96

Forwarding

Without
forwarding paths

With
forwarding paths

1a.EX/MEM.RegRd = ID/EX.RegRs 2a.MEM/WB.RegRd = ID/EX.RegRs

1b.EX/MEM.RegRd = ID/EX.RegRt 2b.MEM/WB.RegRd = ID/EX.RegRt
 Forwarding Control
 The control values for the forwarding
multiplexors
 Double Data Hazard
 Consider the sequence:
add $1,$1,$2
MEM/WB.RegisterRd = ID/EX.RegisterRs
add $1,$1,$3
EX/MEM.RegRd
= ID/EX.RegRs
add $1,$1,$4
 Both hazards occur
 Want to use the most recent
 Revise MEM hazard condition
 Only fwd if EX hazard condition isn’t true

Chapter 4 — The Processor — 99

Revised Forwarding Condition
EX hazard
 MEM hazard
 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRs))
and (MEM/WB.RegisterRd = ID/EX.RegisterRs))
ForwardA = 01
 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)
and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd = ID/EX.RegisterRt))
and (MEM/WB.RegisterRd = ID/EX.RegisterRt))
ForwardB = 01

Chapter 4 — The Processor — 100

Datapath with Forwarding

Chapter 4 — The Processor — 101

Load-Use Data Hazard

Need to stall
for one cycle

Chapter 4 — The Processor — 102

Load-Use Hazard Detection
 Check when using instruction is decoded
in ID stage
 ALU operand register numbers in ID stage
are given by
 IF/ID.RegisterRs, IF/ID.RegisterRt
 Load-use hazard when A load instr.
 ID/EX.MemRead and
((ID/EX.RegisterRt = IF/ID.RegisterRs) or
(ID/EX.RegisterRt = IF/ID.RegisterRt))
 If detected, stall and insert bubble

Chapter 4 — The Processor — 103

How to Stall the Pipeline
 Force control values in ID/EX register
to 0
 EX, MEM and WB do nop (no-operation)
 Prevent update of PC and IF/ID register
 Using instruction is decoded again
 Following instruction is fetched again
 1-cycle stall allows MEM to read data for lw
 Can subsequently forward to EX stage

Chapter 4 — The Processor — 104

Stall/Bubble in the Pipeline

Stall inserted
here

Chapter 4 — The Processor — 105

Stall/Bubble in the Pipeline
 stall the pipeline: keep an instruction in the same stage
 bubble – change the EX, MEM, WB controls fields of the ID/EX to 0
 Keep the instr. in IF and ID for one more cycle (and and or below)

Or, more accurately…

Chapter 4 — The Processor — 106
 Datapath with Hazard Detection
Hazard detected: 0 as mux input (and  bubble), PCWrite = 0, IF/Dwrite = 0

00
01
10
fwdA
00
01
10

fwdB
Stalls and Performance
The BIG Picture

 Stalls reduce performance

 But are required to get correct results
 Compiler can arrange code to avoid
hazards and stalls
 Requires knowledge of the pipeline structure

Chapter 4 — The Processor — 108

 §4.8 Control Hazards
Branch Hazards
 If branch outcome determined in MEM

Flush these
instructions
(Set control
values to 0)

PC

Chapter 4 — The Processor — 109

 Reducing Branch Delay
 Add hardware to determine outcome to ID stage
 Target address adder
 Register comparator (XOR two registers and OR the result)
 Example: branch taken
36: sub $10, $4, $8
40: beq $1, $3, 7 For wrong branch decision:
44: and $12, $2, $5 flush the instr. at IF stage
48: or $13, $2, $6 (use IF.Flush to clear IF/ID.instr.)
52: add $14, $4, $2
56: slt $15, $6, $7
...
72: lw $4, 50($7)

Chapter 4 — The Processor — 110

Example: Branch Taken

Chapter 4 — The Processor — 111

Example: Branch Taken

Chapter 4 — The Processor — 112

Data Hazards for Branches
 Since we add hardware to determine branch outcome at
ID stage, we need to compare two registers at ID stage
 If a comparison register is a destination of 2nd or 3rd
preceding ALU instruction  resolve with forwarding

add $1, $2, $3 IF ID EX MEM WB

add $4, $5, $6 IF ID EX MEM WB

… IF ID EX MEM WB

beq $1, $4, target IF ID EX MEM WB

 Can resolve using forwarding

Chapter 4 — The Processor — 113
Data Hazards for Branches
 If a comparison register is a destination of
preceding ALU instruction or 2nd preceding
load instruction
 Need 1 stall cycle

lw $1, addr IF ID EX MEM WB

add $4, $5, $6 IF ID EX MEM WB

stalled
beq $1, $4, target IF ID EX MEM WB

Chapter 4 — The Processor — 114

Data Hazards for Branches
 If a comparison register is a destination of
immediately preceding load instruction
 Need 2 stall cycles

lw $1, addr IF ID EX MEM WB

beq stalled IF ID

beq stalled ID

beq $1, $0, target ID EX MEM WB

Chapter 4 — The Processor — 116

Dynamic Branch Prediction
 In deeper and superscalar pipelines, branch
penalty is more significant
 Use dynamic prediction
 Branch prediction buffer (aka branch history table)
 Indexed by address of branch instruction
 Stores outcome (taken/not taken)
 To execute a branch
 Check table, expect the same outcome
 Start fetching from fall-through or target
 If wrong, flush pipeline and flip prediction

Chapter 4 — The Processor — 117

1-Bit Predictor: Shortcoming
 Inner loop branches mispredicted twice!
outer: …
…
inner: …
…
beq …, …, inner
…
beq …, …, outer

 Mispredict as taken on last iteration of

inner loop
 Then mispredict as not taken on first
iteration of inner loop next time around
Chapter 4 — The Processor — 118
T T T T T N T T T T T N T T T T T N TTT
T T T T T T N T T T T T N T T T T T NTT

Chapter 4 — The Processor — 119

2-Bit Predictor
 Only change prediction on two successive
mispredictions
The 4th, 5th Edition

Chapter 4 — The Processor — 120

Branch predictor
 Branch: T – N – T – N – N – T – N
 Predictors are initialized to taken.

 1-bit: T – N – T – N – N – T – N
 T T  N T  N N T
 2-bit: T – N – T – N – N – T – N
T T  T T T  N  T
 2-bit: T – N – T – N – N – N – T – N
T T  T T T  N  N N
Chapter 4 — The Processor — 121
Calculating the Branch Target

 Even with predictor, still need to calculate

the target address
 1-cycle penalty for a taken branch
 Branch target buffer
 Cache of target addresses
 Indexed by PC when instruction fetched
 If hit and instruction is branch predicted taken, can
fetch target immediately

Chapter 4 — The Processor — 122

 §4.9 Exceptions
Exceptions and Interrupts
 “Unexpected” events requiring change
in flow of control
 Different ISAs use the terms differently
 Exception
 Arises within the CPU
 e.g., undefined opcode, overflow, syscall, …
 Interrupt
 From an external I/O controller
 Dealing with them without sacrificing
performance is hard

Chapter 4 — The Processor — 123

 Handling Exceptions
 In MIPS, managed by a System Control Coprocessor (CP0)
 Save PC of interrupted instruction
 In MIPS: Exception Program Counter (EPC)
 Save indication of the problem
 In MIPS: Cause register
 We’ll assume 1-bit: 0 for undefined opcode, 1 for overflow
 Jump to handler at 8000 0180
 In MIPS, a single entry point for all exceptions
 OS decodes the status register to find the cause
 Alternative: vectored Interrupts
 Handler address determined by the cause
 E.g.: Undefined opcode: C000 0000
 Overflow: C000 0020
 …: C000 0040

Chapter 4 — The Processor — 124

Handler Actions
 Read cause, and transfer to relevant
handler
 Determine action required
 If restartable
 Take corrective action
 use EPC to return to program
 Otherwise
 Terminate program
 Report error using EPC, cause, …

Chapter 4 — The Processor — 125

Exceptions in a Pipeline
 Another form of control hazard
 Consider overflow on add in EX stage
add $1, $2, $1
 Prevent $1 from being clobbered

 Complete previous instructions

 Flush add and subsequent instructions

 Set Cause and EPC register values

 Transfer control to handler

 Similar to mispredicted branch

 Use much of the same hardware

Chapter 4 — The Processor — 126

 Pipeline with Exceptions
 Flush instructions at IF, ID, EX when an exception is detected at EX.
 Supply 8000 0180 to PC. Add Cause, EPC, IF.Flush, ID.Flush, EX.Flush

127
Exception Properties
 Restartable exceptions
 Pipeline can flush the instruction
 Handler executes, then returns to the
instruction
 Refetched and executed from scratch
 PC saved in EPC register
 Identifies causing instruction
 Actually PC + 4 is saved
 Handler must adjust

Chapter 4 — The Processor — 128

Exception Example
 Exception on add in
40 sub $11, $2, $4
44 and $12, $2, $5
48 or $13, $2, $6
4C add $1, $2, $1
50 slt $15, $6, $7
54 lw $16, 50($7)
…
 Handler
80000180 sw $25, 1000($0)
80000184 sw $26, 1004($0)
…

Chapter 4 — The Processor — 129

Exception Example

Chapter 4 — The Processor — 130

Exception Example

Chapter 4 — The Processor — 131

Multiple Exceptions
 Pipelining overlaps multiple instructions
 Could have multiple exceptions at once
 Simple approach: deal with exception from
earliest instruction
 Flush subsequent instructions
 “Precise” exceptions
 In complex pipelines
 Multiple instructions issued per cycle
 Out-of-order completion
 Maintaining precise exceptions is difficult!

Chapter 4 — The Processor — 132

Imprecise Exceptions
 Just stop pipeline and save state
 Including exception cause(s)
 Let the handler work out
 Which instruction(s) had exceptions
 Which to complete or flush
 May require “manual” completion
 Simplifies hardware, but more complex handler
software
 Not feasible for complex multiple-issue
out-of-order pipelines

Chapter 4 — The Processor — 133

 §4.10 Parallelism and Advanced Instruction Level Parallelism
Instruction-Level Parallelism (ILP)
 Pipelining: executing multiple instructions in
parallel
 To increase ILP
 Deeper pipeline
 Less work per stage  shorter clock cycle

 Multiple issue
 Replicate pipeline stages  multiple pipelines

 Start multiple instructions per clock cycle

 CPI < 1, so use Instructions Per Cycle (IPC)

 E.g., 4GHz 4-way multiple-issue

 16 BIPS, peak CPI = 0.25, peak IPC = 4

 But dependencies reduce this in practice

Chapter 4 — The Processor — 134

Multiple Issue
 Static multiple issue
 Compiler groups instructions to be issued together
 Packages them into “issue slots”
 Compiler detects and avoids hazards
 Dynamic multiple issue
 CPU examines instruction stream and chooses
instructions to issue each cycle
 Compiler can help by reordering instructions
 CPU resolves hazards using advanced techniques at
runtime

Chapter 4 — The Processor — 135

Speculation
 “Guess” what to do with an instruction
 Start operation as soon as possible
 Check whether guess was right
 If so, complete the operation
 If not, roll-back and do the right thing
 Common to static and dynamic multiple issue
 Examples
 Speculate on branch outcome
 Roll back if path taken is different
 Speculate on load
 Roll back if location is updated

Chapter 4 — The Processor — 136

Static Multiple Issue
 Compiler groups instructions into “issue
packets”
 Group of instructions that can be issued on a
single cycle
 Determined by pipeline resources required
 Think of an issue packet as a very long
instruction
 Specifies multiple concurrent operations
  Very Long Instruction Word (VLIW)

Chapter 4 — The Processor — 139

Scheduling Static Multiple Issue
 Compiler must remove some/all hazards
 Reorder instructions into issue packets
 No dependencies with a packet
 Possibly some dependencies between
packets
 Varies between ISAs; compiler must know!
 Pad with nop if necessary

Chapter 4 — The Processor — 140

MIPS with Static Dual Issue
 Two-issue packets
 One ALU/branch instruction
 One load/store instruction
 64-bit aligned
 ALU/branch, then load/store
 Pad an unused instruction with nop
Address Instruction type Pipeline Stages
n ALU/branch IF ID EX MEM WB
n+4 Load/store IF ID EX MEM WB
n+8 ALU/branch IF ID EX MEM WB
n + 12 Load/store IF ID EX MEM WB
n + 16 ALU/branch IF ID EX MEM WB
n + 20 Load/store IF ID EX MEM WB

Chapter 4 — The Processor — 141

MIPS with Static Dual Issue

Chapter 4 — The Processor — 142

Hazards in the Dual-Issue MIPS
 More instructions executing in parallel
 EX data hazard
 Forwarding avoided stalls with single-issue
 Now can’t use ALU result in load/store in same packet
 add $t0, $s0, $s1
load $s2, 0($t0)
 Split into two packets, effectively a stall
 Load-use hazard
 Still one cycle use latency, but now two instructions
 More aggressive scheduling required

Chapter 4 — The Processor — 143

Scheduling Example
 Schedule this for dual-issue MIPS
Loop: lw $t0, 0($s1) # $t0=array element
addu $t0, $t0, $s2 # add scalar in $s2
sw $t0, 0($s1) # store result
addi $s1, $s1,–4 # decrement pointer
bne $s1, $zero, Loop # branch $s1!=0

nop lw $t0, 0($s1)

addi $s1, $s1,–4 nop
addu $t0, $t0, $s2 nop
bne
addi $s1, $zero,
$s1,–4 Loop sw $t0, 4
0($s1)
($s1)
bne $s1, $zero, Loop

 IPC = 5/4 = 1.25 (c.f. peak IPC = 2)

Chapter 4 — The Processor — 144
Loop Unrolling
 Replicate loop body to expose more
parallelism
 Reduces loop-control overhead
 Use different registers per replication
 Called “register renaming”
 Avoid loop-carried “anti-dependencies”
 Store followed by a load of the same register
 Aka “name dependence”
 Reuse of a register name

Chapter 4 — The Processor — 145

 Loop: lw $t0, 0($s1) Loop: lw $t0, 0($s1)
addu $t0, $t0, $s2 addu $t0, $t0, $s2
sw $t0, 0($s1) sw $t0, 0($s1)
addi $s1, $s1,–4 $t1
lw $t0, 0($s1)
bne $s1, $zero, Loop -4
addu $t0, $t0, $s2
sw $t0, 0($s1)
Antidependence (name dependence) lw
$t2
$t0, 0($s1)
-The ordering forced by the reuse of a addu $t0, $t0, $s2 -8
name (register), not true data sw $t0, 0($s1)
dependence. $t3
lw $t0, 0($s1)
addu $t0, $t0, $s2 -12
Register Renaming: sw $t0, 0($s1)
- to remove anti-dependence.
addi $s1, $s1,–4 -16
- e.g., $t0  $t0, $t1, $t2, $t3 bne $s1, $zero, Loop

Chapter 4 — The Processor — 146

 lw $t0, 0($s1)
addu $t0, $t0, $s2
sw $t0, 0($s1)
lw $t1, -4($s1)
addu $t1, $t0, $s2
sw $t1, -4($s1)
lw $t2, -8($s1)
addu $t2, $t0, $s2
sw $t2, -8($s1)
lw $t3, -12($s1)
addu $t3, $t0, $s2
sw $t3, -12($s1)
addi $s1, $s1,–16
bne $s1, $zero, Loop

nop lw $t0, 0($s1)

nop
addu $t0, $t0, $s2 nop
sw $t0, 0($s1)
Loop Unrolling Example
ALU/branch Load/store cycle
Loop: addi $s1, $s1,–16 lw $t0, 0($s1)
0($s1) 1
nop lw $t1, 12($s1)
12($s1)
-4 ($s1) 2
addu $t0, $t0, $s2 lw 8($s1)
$t2, 8($s1)
-8 ($s1) 3
addu $t1, $t1, $s2 lw 4($s1)
-12($s1)
$t3, 4($s1) 4
addu $t2, $t2, $s2 sw 0($s1)
$t0, 16($s1)
16($s1) 5
addu $t3, $t4, $s2 sw -4($s1)
$t1, 12($s1)
12($s1) 6
nop sw -8($s1)
$t2, 8($s1)
8($s1) 7
bne $s1, $zero, Loop sw -12($s1)
$t3, 4($s1)
4($s1) 8

 IPC = 14/8 = 1.75

 Closer to 2, but at cost of registers and code size

Chapter 4 — The Processor — 148

Dynamic Multiple Issue
 “Superscalar” processors
 CPU decides whether to issue 0, 1, 2, …
instructions each cycle
 Avoiding structural and data hazards
 Avoids the need for compiler scheduling
 Though it may still help
 Code semantics ensured by the CPU

Chapter 4 — The Processor — 149

Dynamic Pipeline Scheduling
 It is hardware support
 Allow the CPU to execute instructions out of
order to avoid stalls (out-of-order execution)
 But commit result to registers in order (in-order
commit)
lw $t0, 20($s2)
addu $t1, $t0, $t2
sub $s4, $s4, $t3
slti $t5, $s4, 20
 Can start sub while addu is waiting for lw
Chapter 4 — The Processor — 150
 Dynamically Scheduled CPU
Preserves
dependencies

Hold pending
operands

Results also sent

to any waiting
reservation stations

Reorders buffer for

register writes
Can supply
operands for
issued instructions

Chapter 4 — The Processor — 151

Register Renaming
 Reservation stations and reorder buffer
effectively provide register renaming
 On instruction issue to reservation station
 If operand is available in register file or
reorder buffer
 Copied to reservation station
 No longer required in the register; can be
overwritten
 If operand is not yet available
 It will be provided to the reservation station by
another function unit directly.
 Register update may not be required
Chapter 4 — The Processor — 152
Why Do Dynamic Scheduling?
 Why not just let the compiler schedule
code? (Note: dynamic scheduling is hardware
support)
 Not all stalls are predicable
 e.g., cache misses
 Can’t always schedule around branches
 Branch outcome is dynamically determined
 Different implementations of an ISA have
different latencies and hazards

Chapter 4 — The Processor — 154

Does Multiple Issue Work?
The BIG Picture

 Yes, but not as much as we’d like

 Programs have real dependencies that limit ILP
 Some dependencies are hard to eliminate
 e.g., pointer aliasing
 Some parallelism is hard to expose
 Limited window size during instruction issue
 Memory delays and limited bandwidth
 Hard to keep pipelines full
 Speculation can help if done well
Chapter 4 — The Processor — 155
Power Efficiency
 Complexity of dynamic scheduling and
speculations requires power
 Multiple simpler cores may be better
Microprocessor Year Clock Rate Pipeline Issue Out-of-order/ Cores Power
Stages width Speculation
i486 1989 25MHz 5 1 No 1 5W
Pentium 1993 66MHz 5 2 No 1 10W
Pentium Pro 1997 200MHz 10 3 Yes 1 29W
P4 Willamette 2001 2000MHz 22 3 Yes 1 75W
P4 Prescott 2004 3600MHz 31 3 Yes 1 103W
Core 2006 2930MHz 14 4 Yes 2 75W
UltraSparc III 2003 1950MHz 14 4 No 1 90W
UltraSparc T1 2005 1200MHz 6 1 No 8 70W

Chapter 4 — The Processor — 156

 §4.11 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Pipelines
Cortex A8 and Intel i7
Processor ARM A8 Intel Core i7 920
Market Personal Mobile Device Server, cloud
Thermal design power 2 Watts 130 Watts
Clock rate 1 GHz 2.66 GHz
Cores/Chip 1 4
Floating point? No Yes
Multiple issue? Dynamic Dynamic
Peak instructions/clock cycle 2 4
Pipeline stages 14 14
Pipeline schedule Static in-order Dynamic out-of-order
with speculation
Branch prediction 2-level 2-level
1st level caches/core 32 KiB I, 32 KiB D 32 KiB I, 32 KiB D
2nd level caches/core 128-1024 KiB 256 KiB
3rd level caches (shared) - 2- 8 MB

Chapter 4 — The Processor — 157

ARM Cortex-A8 Pipeline & Performance

Chapter 4 — The Processor — 158

Core i7 Pipeline

Chapter 4 — The Processor — 159

Core i7 Performance

Chapter 4 — The Processor — 160

Performance Impact

Chapter 4 — The Processor — 161

 §4.11 Real Stuff: The AMD Opteron X4 (Barcelona) Pipeline
The Opteron X4 Microarchitecture

72 physical
registers

Chapter 4 — The Processor — 162

The Opteron X4 Pipeline Flow
 For integer operations

 FP is 5 stages longer
 Up to 106 RISC-ops in progress
 Bottlenecks
 Complex instructions with long dependencies
 Branch mispredictions
 Memory access delays

Chapter 4 — The Processor — 163

 §4.13 Fallacies and Pitfalls
Fallacies
 Pipelining is easy (!)
 The basic idea is easy
 The devil is in the details
 e.g., detecting data hazards
 Pipelining is independent of technology
 So why haven’t we always done pipelining?
 More transistors make more advanced techniques
feasible
 Pipeline-related ISA design needs to take account
of technology trends
 e.g., predicated instructions
Chapter 4 — The Processor — 164
Pitfalls
 Poor ISA design can make pipelining
harder
 e.g., complex instruction sets (VAX, IA-32)
 Significant overhead to make pipelining work
 IA-32 micro-op approach
 e.g., complex addressing modes
 Register update side effects, memory indirection
 e.g., delayed branches
 Advanced pipelines have long delay slots

Chapter 4 — The Processor — 165

 §4.14 Concluding Remarks
Concluding Remarks
 ISA influences design of datapath and control
 Datapath and control influence design of ISA
 Pipelining improves instruction throughput
using parallelism
 More instructions completed per second
 Latency for each instruction not reduced
 Hazards: structural, data, control
 Multiple issue and dynamic scheduling (ILP)
 Dependencies limit achievable parallelism
 Complexity leads to the power wall

Chapter 4 — The Processor — 166