SVA Quick Reference Directives Disable Clause

[ label : ] assert property (prop_expr) [ action_block ] ; disable iff (boolean_expr)

Product Version: IUS 11.1 (17.13.1) Checks a property during verification. Example: default disable iff (boolean_expr)
Release Date: December 2011 (17.11) Specifies a reset expression. Checking of the
This quick reference describes the SystemVerilog Assertion constructs
property P5 (AA); property is terminated asynchronously when the
@(negedge clk) (b ##1 c) |=> expression is true. Example:
supported by Cadence Design Systems. For more information about (AA ##[1:2] (d||AA));
SystemVerilog Assertions, see the Assertion Writing Guide. endproperty property P4;
assert property (P5(a)); @(negedge clk) disable iff (rst)
Note: Numbers in parentheses indicate the section in the IEEE (c) |-> (##[max-1:$] d);
1800-2005 Standard for SystemVerilog for the given construct.
[label:] assume property (prop_expr) [ action_block ] ; endproperty
(17.13.2) Constrains the inputs considered for the
property during verification. In simulation, treated like Property Expressions
Binding assert. Example:
sequence_expr |-> property_expr
bind target bind_obj [ (params)] bind_inst (ports) ; A1: assume (@(ena) !rst); (17.11.2) The property expression must be true in the
(17.15) Attaches a SystemVerilog module or interface to [label:] cover property (prop_expr) [ pass_statement ] ; last cycle that the sequence expression is true
a Verilog module or interface instance, or to a VHDL [label:] cover sequence (seq_expr) [ pass_statement ] ; (overlapping). Example:
entity/architecture. Multiple targets supported. Example:
(17.13.3) Monitors the property or sequence for coverage property P4;
bind fifo fifo_full v1(clk,empty,full); and reports statistics. The statement is executed when @(negedge clk)
disable iff (rst)
bind top.dut.fifo1 fifo_full v2(clk,empty,full); the property succeeds. Cover sequence reports all (c) |-> (##[max-1:$] d);
bind fifo:fifo1,fifo2 fifo_full v3(clk,empty,full); matches. Example: endproperty
Immediate Assertions C1: cover property (@(event) a |-> b ##[2:5] c); sequence_expr |=> property_expr
[ label : ] assert (boolean_expr) [ action_block ] ; (17.11.2) The property expression must be true in the
expect Statement first cycle after the sequence expression is true.
(17.2) Tests an expression when the statement is expect (prop_expr) [ action_block ] ; Example:
executed in the procedural code. Example:
(17.16) Blocks the current process until the property property property P5 (AA);
enable_set_during_read_op_only : assert succeeds or fails. Example: @(negedge clk)
(state >= ‘start_read && state <= ‘finish_read); (b ##1 c) |=> (AA ##[1:2] (d||AA));
else $warning("Enable set when state => %b", expect( @(posedge clk) ##[1:10] endproperty
state); top.TX_Monitor.data == value ) success = 1; property_expr and property_expr
else success = 0;
Declarations (17.11) Returns true if both property expressions are
Clock Expressions true. Example:
sequence identifier [ argument_list ] ;
sequence_expr [ seq_op sequence_expr ] ... ; @( {{posedge | negedge} clock | expression} ) @(c) v |=> (w ##1 @(d) x) and (y ##1 z)
endsequence [ : identifier ] (17.14) Declares an event or event expression to use for not property_expr
(17.6) Declares a sequence expression that can be used sampling assertion variable values. Multiple clocks (17.11) Returns the opposite of the value returned by the
in property declarations. Local variables are permitted. (17.12), and clocks inferred from an always block property_expr. Example:
Example: containing only assertions, are supported. Examples:
property abcd;
sequence BusReq (bit REQ=0, bit ACK=0); assert property @(posedge clk1) (a ##1 b) |=> @(posedge clk) a |-> not (b ##1 c ##1 d);
REQ ##[1:3] ACK; @(posedge clk2) (c ##1 d)); endproperty
endsequence endproperty
if (expression) property_expr1 [ else property_expr2]
property identifier [ argument_list ] ; assert property ( @(posedge clk1) (a ##1 b) |=>
[ clock_expr ] [ disable_clause ] property_expr ; @(posedge clk2) (c ##1 d) ); (17.11) If expression is true, property_expr1 must
endproperty [ : identifier ] hold; property_expr1 does not need to hold when
always @(posedge clk) begin expression is false. If expression is false,
(17.11) Declares a condition or sequence to be verified assert property ( (a ##1 b) |=> (c ##1 d) ); property_expr2 must hold, if it exists. Example:
during simulation. Local variables are permitted. assert property ( (a[*3]) |=> ~c );
Example: cover property ( (a ##1 b ##1 c) |=> property P2;
(d[*2:4]) ); @ (negedge clk)
property P6 (bit AA, BB=‘true, EN=1); end if (a)
@(negedge clk) b |=> c;
else
EN -> (BB ##1 c) |=> (AA ##[1:2] (d||AA)); Default Clocking Blocks d |=> e;
endproperty endproperty
default clocking [clk_identifier]
[ identifier: ] [ (argument_list) ] {identifier | clk_expression} ; Sequence Operators
clocking_items
(17.11) Creates an instance of a property declaration. end clocking sequence_expr1 and sequence_expr2
Example: default clocking clk_identifier
(17.7.4) Both sequences must occur, but the end times of
property P1; (17.14) Specifies the clock or event that controls property
@(event) a && b ##1 !a && !b; the operands can be different. Example:
endproperty evaluation. Example:
default clocking master_clk @(posedge clk); (a ##2 b) and (c ##2 d ##2 e) ;
property P2; property p4; (a |=> ##2 b); endproperty
@(posedge clk) rst |-> P1; assert property (p4);
endproperty endclocking
Sequence Operators (cont’d) Repetition $countones (bit_vector)
(17.10) Returns the number of bits in a vector that have
first_match (sequence_expr[, seq_match_item]) [* const_or_range_expression ] the value 1. Example:
(17.7.7) Evaluation of one or more sequences stops (17.7.2) Consecutive repetition. Example: property p4(Arg)
when the first match is found. Example: @(posedge clk) $countones(Arg) == 4;
(a[*2] ##2 b[*2]) |=> (d) endproperty
sequence s1;
first_match(a ##1 b[->1]:N] ## c); [-> const_or_range_expression ]
endsequence Sampled-Value Functions
(17.7.2) Goto repetition. Example:
sequence_expr1 intersect sequence_expr2 $sampled(expression)
a ##1 b[->5] ##1 c (17.7.3) Returns the sampled value of the expression at
(17.7.5) Both sequences must occur, and the start and
end times of the sequence expressions must be the [= const_or_range_expression ] the current clock cycle. Example:
same. Example: property propA
(17.7.2) Non-consecutive repetition. Example: @(posedge clk) (a ##1 b);
(a ##2 b) intersect (c ##2 d ##2 e) endproperty
s1 |=> (b [=5] ##1 c) p1: assert (propA)
sequence_expr1 or sequence_expr2 $display("%m passed");
Shortcuts else $warning("a == %s; b == %s",
(17.7.6) At least one of the sequences must occur. $sampled(test.inst.a),
Example: R[*] is the same as R[*0:$] $sampled(test.inst.b));
(b ##1 c) or (d[*1:2] ##1 e) or f[*2] ##[*] is the same as ##[0:$]
$rose(expression)
R[+] is the same as R[*1:$]
boolean_expr throughout sequence_expr (17.7.3) Returns true if the sampled value of
##[+] is the same as ##[1:S] expression changed to 1 during the current clock
(17.7.8) A condition must hold true for the duration of a
sequence. Example: cycle. Example:
Assertion Severity Tasks
(a ##2 b) throughout read_sequence Example:
$fatal ([ 0 | 1 | 2 , ] message [ , args ] ) ; (a ##1 b) |-> $rose(test.inst.sig4);
sequence_expr1 within sequence_expr2 (17.2) Fatal message task; messages can be strings or $fell(expression)
(17.7.9) sequence_expr1 must match at some point expressions. You can call this task from the action block
of an assertion. Example: (17.7.3) Returns true if the sampled value of
within the timeframe of sequence_expr2. Example: expression changed to 0 during the current clock
(a ##2 b ##3 c) within write_enable $fatal (0); cycle. Example:
$error (message [ , args ] ) ; (a ##1 b) |-> $fell(test.inst.c);
Sequence Methods $warning (message [ , args ] ) ;
$info (message [ , args ] ) ; $stable(expression)
sequence_instance.[ ended|matched|triggered]
(17.2) Non-fatal message tasks; messages can be (17.7.3) Returns true if the sampled value of
(17.12.6) Identifies the endpoint of a sequence. Example: expression remained the same during the current
strings or expressions. You can call these tasks from the
wait (AB.triggered) || BC.triggered); action block of an assertion. Example: clock cycle. Example:
if (AB.triggered) $display("AB triggered"); (a ##1 b) |-> $stable(test.inst.c);
$error("Unsupported memory task command %b",
m_task); $past(expression [ , n_cycles] )
Cycle Delays $warning("Enable is set during non-read op:
state=>%b", state); (17.7.3) Returns the sampled value of expression at
##integral_number the previous clock cycle or the specified number of clock
##Identifier System Functions ticks in the past. Example:
##(constant_expression) $onehot (bit_vector) (a == $past(test.inst.c, 5)
##[const_expr : const_expr] (17.10) Returns true if one and only one bit of the
##[const_expr : $] expression is high. Example: Assertion-Control System Tasks
(17.5) Specifies the number of clock ticks from the property p1(Arg) $assertoff [ ( levels [ , list_of_mods_or_assns ] ) ] ;
current clock tick until the next specified behavior occurs. @(posedge clk) $onehot(Arg); $asserton [ ( levels [ , list_of_mods_or_assns ] ) ] ;
endproperty $assertkill [ ( levels [ , list_of_mods_or_assns ] ) ] ;
Example:
$onehot0 (bit_vector) (22.8) Controls assertion checking during simulation.
property property P5 (AA);
@(negedge clk) (17.10) Returns true if no more than one bit of the Example:
(b ##1 c) |=> (AA ##[1:2] (d||AA)); expression is high. Example:
endproperty $assertoff (0, top.mod1, top.mod2.net1);
property p2(Arg)
Local Variables in Sequences and Properties @(posedge clk) $onehot0(Arg);
endproperty
(seq_expression {, seq_match_item}) [ repetition_op ]
$isunknown (bit_vector)
(17.8, 17.9) The seq_match_item is executed when
seq_expression is matched. The match item can be a (17.10) Returns true if any bit of the expression is X or Z.
subroutine call. Example: Example:
sequence data_check; property p3(Arg)
int x; @(posedge clk) $isunknown(Arg);
a ##1 (!a, x=data_in) ##1 !b[*0:$] endproperty
##1 b && (data_out=x);
endsequence © 2011 Cadence Design Systems, Inc.
All rights reserved.