W49V002FA

256K × 8 CMOS FLASH MEMORY

WITH FWH INTERFACE
GENERAL DESCRIPTION
The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49V002FA results in fast program/erase operations
with extremely low current consumption. This device can operate at two modes, Programmer bus
interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the
traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device
complies with the Intel FWH specification. The device can also be programmed and erased using
standard EPROM programmers.

FEATURES
• Single 3.3-volt operations: • Two 8K bytes Parameter Blocks
− 3.3-volt Read • Four main memory blocks (with 32K bytes, 64K
bytes, 64K bytes, 64K bytes each)
− 3.3-volt Erase
• Low power consumption
− 3.3-volt Program
− Active current: 40 mA (typ. for FWH)
• Fast program operation:
• Automatic program and erase timing with
− Byte-by-byte programming: 50 µS (typ.) internal VPP generation
• Fast erase operation: 150 mS (typ.) • End of program or erase detection
• Fast read access time: Tkq 11 nS
− Toggle bit
• Endurance: 10K cycles (typ.)
− Data polling
• Twenty-year data retention
• Latched address and data
• Hardware data protection
• TTL compatible I/O
− #TBL & #WP serve as hardware protection
• Available packages: 32L PLCC, 32L STSOP
• One 16K bytes Boot Block with lockout
protection

Publication Release Date: February 19, 2002

-1- Revision A2
 W49V002FA

PIN CONFIGURATIONS BLOCK DIAGRAM

#WP 3FFFF
BOOT BLOCK
#TBL 16K BYTES 3C000
CLK PARAMETER 3BFFF
Interface
FWH[3:0] BLOCK1
8K BYTES 3A000
FWH4
39FFF
IC PARAMETER
BLOCK2
8K BYTES 38000
#RESET
37FFF
A #INIT MAIN MEMORY
A A 1 BLOCK1
8 9 R 0 32K BYTES
^ ^ # ^ 30000
F F # C F R/#C 2FFFF
G G R ^ G MAIN MEMORY
P P E C P BLOCK2
I I S V L I A[10:0] 64K BYTES
2 3 E N D K 4 Program- 20000
v v T C D v v mer 1FFFF
DQ[7:0] Interface MAIN MEMORY
BLOCK3
4 3 2 1 32 31 30
#OE 64K BYTES
10000
MAIN MEMORY 0FFFF
A7(FGPI1) 5 29 IC #WE
BLOCK4
A6(FGPI0) 6 28 GND 64K BYTES 00000
A5(#WP) 7 27 NC
A4(#TBL) 8 32L 26 GND
A3(ID3) 9 PLCC 25 VDD
A2(ID2) 10 24 #OE(#INIT)
A1(ID1) 11 23 #WE(FWH4) PIN DESCRIPTION
A0(ID0) 12 22 NC
DQ0(FWH0) 13 21 DQ7(RSV) SYM. INTERFACE PIN NAME
PGM FWH
14 15 16 17 18 19 20

D
Q
D G D D
Q N Q Q
D
Q
D
Q
IC * * Interface Mode Selection
1 2 D 3 4 5 6
^
F
^
F
^ ^
F R
^
R
^
R
#RESET * * Reset
W W W S S S
H H H V V V
1 2 3 v v v #INIT * Initialize
v v v
#TBL * Top Boot Block Lock
#WP * Write Protect
CLK * CLK Input
FGPI[4:0] * General Purpose Inputs
ID[3:0] * Identification Inputs They
NC
NC
1
2
32
31
#OE(#INIT)
#WE(FWH4)
Are Internal Pull Down to
NC
GND
3
4
30
29
NC
DQ7(RSV)
VSS
IC 5 28 DQ6(RSV)
A10(FGPI4) 6
7 32L 27
26
DQ5(RSV) FWH[3:0] * Address/Data Inputs
R/#C(CLK) DQ4(RSV)
VDD 8 25
NC 9 TSOP 24
DQ3(FWH3)
GND FWH4 * FWH Cycle Initial
#RESET 10 23 DQ2(FWH2)
A9(FGPI3)
A8(FGPI2)
11
12
22
21
DQ1(FWH1)
DQ0(FWH0)
R/#C * Row/Column Select
A7(FGPI1) 13 20 A0(ID0)
A6(FGPI0) 14
15
19
18
A1(ID1)
A2(ID2)
A[10:0] * Address Inputs
A5(#WP)
A4(#TBL) 16 17 A3(ID3)
DQ[7:0] * Data Inputs/Outputs
#OE * Output Enable
#WE * Write Enable
VDD * * Power Supply
GND * * Ground
RSV * * Reserved Pins
NC * * No Connection

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 W49V002FA

FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is
FWH interface mode. The IC pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low
state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just
behaves like traditional flash parts with 8 data lines. But the row and column address inputs are
multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH
Interface Specification. Through the FWH[3:0] to communicate with the system chipset .

Read (Write) Mode

In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE
(#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0
& bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details.

Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 150 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains
as the same state before the chip erase operation). The entire memory array will be erased to FF(hex)
by the chip erase operation if the boot block programming lockout feature is not activated. The device
will automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

The seven sectors, one boot block and two parameter memory and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal
read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect
end of erase cycle.

Publication Release Date: February 19, 2002

-3- Revision A2
 W49V002FA

Program Operation
The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the byte-
program command is entered. The internal program timer will automatically time-out (100 µS max. -
TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.

Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. One is software command sequences method; the
other is hardware method. 16K-byte in the top location of this device can be locked as boot block,
which can be used to store boot codes. It is located in the last 16K bytes of the memory with the
address range from 3C000(hex) to 3FFFF(hex).
Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is
set, the data for the designated block cannot be erased or programmed (programming lockout), other
memory locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block
will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will
override the software method setting. That is, if #TBL is at low state, then top boot block cannot be
programmed/erased no matter how the software boot block lock setting.
Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The
enable of this pin will override the #TBL setting. That is, the top boot block cannot be
programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.

Hardware Data Protection

The integrity of the data stored in the W49V002FA is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 1.5V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5
mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W49V002FA includes a data polling feature to indicate the end of a program or erase cycle.
When the W49V002FA is in the internal program or erase cycle, any attempts to read DQ7 of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and
when erase cycle has been completed it becomes logical "1" or true data.

-4-
 W49V002FA

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49V002FA provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.

General Purpose Inputs Register

This register reads the FGPI[4:0] pins on the W49V002FA.This is a pass-through register which can
read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.
BIT FUNCTION
7−5 Reserved
4 Read FGPI4 pin status
3 Read FGPI3 pin status
2 Read FGPI2 pin status
1 Read FGPI1 pin status
0 Read FGPI0 pin status

Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software operation. In the software access
mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for
programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex).
A read from address 0001(hex) outputs the device code, 32(hex).” The product ID operation can be
terminated by a three-byte command sequence or an alternate one-byte command sequence (see
Command Definition table).
As for FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code,
DA(hex). A read from FFBC, 0001(hex) can output the device code 32(hex).

TABLE OF OPERATING MODES

Operating Mode Selection - Programmer Mode
(VHH = 12V ± 5%)
MODE PINS
#OE #WE #RESET ADDRESS DQ.
Read VIL VIH VIH AIN Dout
Write VIH VIL VIH AIN Din
Standby X X VIL X High Z
Write Inhibit VIL X VIH X High Z/DOUT
X VIH VIH X High Z/DOUT
Output Disable VIH X VIH X High Z

Publication Release Date: February 19, 2002

-5- Revision A2
 W49V002FA

Operating Mode Selection - FWH Mode

Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When
it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle
Definition".

TABLE OF COMMAND DEFINITION

COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
DESCRIPTION Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read 1 AIN DOUT
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN DIN
Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Product ID Entry 3 5555 AA 2AAA 55 5555 90
(1)
Product ID Exit 3 5555 AA 2AAA 55 5555 F0
Product ID Exit (1) 1 XXXX F0

Notes:
1. The cycle means the write command cycle not the FWH clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]
3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = 3C000h to 3FFFFh for Boot Block
SA = 3A000h to 3BFFFh for Parameter Block1
SA = 38000h to 39FFFh for Parameter Block2
SA = 30000h to 37FFFh for Main Memory Block1
SA = 2XXXXh for Main Memory Block2
SA = 1XXXXh for Main Memory Block3
SA = 0XXXXh for Main Memory Block4

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 W49V002FA

FWH CYCLE DEFINITION

FIELD NO. OF DESCRIPTION
CLOCKS
START 1 "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle.
IDSEL 1 This one clock field indicates which FWH component is being selected.
MSIZE 1 Memory Size. There is always show “0000b” for single byte access.
TAR 2 Turned Around Time
ADDR 7 Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and
Address[3:0] on FWH[3:0] last.)
SYNC N Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
DATA 2 Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then
DQ[7:4] on FWH[3:0] last.)

Publication Release Date: February 19, 2002

-7- Revision A2
 W49V002FA

Embedded Programming Algorithm

Start

Write Program Command Sequence

(see below)

#Data Polling/ Toggle bit Pause TBP

No
Increment Address Last Address
?

Yes

Programming Completed

Program Command Sequence (Address/Command):

5555H/AAH

2AAAH/55H

5555H/A0H

Program Address/Program Data

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 W49V002FA

Embedded Erase Algorithm

Start

Write Erase Command Sequence

(see below)

#Data Polling or Toggle

BitSuccessfully Completed Pause T EC /T SEC

Erasure Completed

Chip Erase Command Sequence Individual Sector Erase

Command Sequence
(Address/Command): (Address/Command):

5555H/AAH 5555H/AAH

2AAAH/55H 2AAAH/55H

5555H/80H 5555H/80H

5555H/AAH 5555H/AAH

2AAAH/55H 2AAAH/55H

5555H/10H Sector Address/30H

Publication Release Date: February 19, 2002

-9- Revision A2
 W49V002FA

Embedded #Data Polling Algorithm

Start

VA = Byte address for programming

Read Byte = Any of the sector addresses within
the sector being erased during sector
(DQ0 - DQ7) erase operation
Address = VA
= Valid address equals any sector group
address during chip erase

No
DQ7 = Data
?

Yes

Pass

Embedded Toggle Bit Algorithm

Start

Read Byte
(DQ0 - DQ7)
Address = Don't Care

Yes
DQ6 = Toggle
?

No

Pass

- 10 -
 W49V002FA

Software Product Identification and Boot Block Lockout Detection Acquisition

Flow

Product Product Product

Identification Identification Identification Exit(6)
and Boot Block
Entry (1) Lockout Detection
Load data AA Mode (3)
Load data AA
to to
address 5555 address 5555

Load data 55 (2)

Read address = 00000 Load data 55
to to
address 2AAA data = DA
address 2AAA

Load data 90 (2) Load data F0

Read address = 00001
to to
address 5555 data = 32 (Hex)
address 5555

(4)
Read address = 00002
Pause 10 µS Pause 10 µS
DQ0 of data outputs = 1/0

(5)
Normal Mode

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex)
(2) A1 − A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the
lockout feature is inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout
detection.

Publication Release Date: February 19, 2002

- 11 - Revision A2
 W49V002FA

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set Flow

Load data AA
to
address 5555

Load data 55
to
address 2AAA

Load data 80
to
address 5555

Load data AA
to
address 5555

Load data 55
to
address 2AAA

Load data 40
to
address 5555

Pause TBP

Exit

- 12 -
 W49V002FA

DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage to VSS Potential -0.5 to +4.1 V
Operating Temperature 0 to +70 °C
Storage Temperature -65 to +150 °C
D.C. Voltage on Any Pin to Ground Potential -0.5 to VDD +0.5 V
Transient Voltage (<20 nS) on Any Pin to Ground Potential -1.0 to VDD +0.5 V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

Programmer interface Mode DC Operating Characteristics

(VDD = 3.3V ± 5%, VGND= 0V, TA = 0 to 70° C)

PARAMETER SYM. TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.
Power Supply ICC In Read or Write mode, all DQs open - 20 30 mA
Current Address inputs = 3.0V/0V, at f = 3 MHz
Input Leakage ILI VIN = GND to VDD - - 10 µA
Current
Output Leakage ILO VOUT = GND to VDD - - 10 µA
Current
Input Low Voltage VIL - -0.3 - 0.8 V
Input High Voltage VIH - 2.0 - VDD +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.1mA 2.4 - - V

Publication Release Date: February 19, 2002

- 13 - Revision A2
 W49V002FA

FWH interface Mode DC Operating Characteristics

(VDD = 3.3V ±5 %, VGND = 0V, TA = 0 to 70° C)

PARAMETER SYM. TEST CONDITIONS LIMITS UNIT

MIN. TYP. MAX.
Power Supply ICC All Iout = 0A, CLK = 33 MHz, - 40 60 mA
Current in FWH mode operation.
Standby Current ISB1 FWH4 = 0.9 VDD, CLK = 33 MHz, - 20 100 µA
all inputs = 0.9 VDD/ 0.1 VDD, no
internal operation
Standby Current ISB2 FWH4 = 0.1 VDD, CLK = 33 MHz, - 3 10 mA
all inputs = 0.9 VDD/ 0.1 VDD,
no internal operation
Input Low Voltage VIL - -0.5 - 0.3 VDD V
Input High Voltage VIH - 0.5 VDD - VDD +0.5 V
Input Low Voltage for VILI - -0.5V - 0.2 VDD V
#INIT
Input High Voltage VIHI - 1.35V - VDD +0.5 V
for #INIT
Output Low Voltage VOL IOL = 1.5 mA - - 0.1 VDD V
Output High Voltage VOH IOH = -0.5 mA 0.9 VDD - - V

Power-up Timing
PARAMETER SYMBOL TYPICAL UNIT
Power-up to Read Operation TPU. READ 100 µS
Power-up to Write Operation TPU. WRITE 5 mS

CAPACITANCE
(VDD = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER SYMBOL CONDITIONS MAX. UNIT

I/O Pin Capacitance CI/O VI/O = 0V 12 pF
Input Capacitance CIN VIN = 0V 6 pF

- 14 -
 W49V002FA

PROGRAMMER INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 0.9 VDD
Input Rise/Fall Time < 5 nS
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 30 pF

AC Test Load and Waveform

+3.3V

1.8KΩ

DOUT
Input Output
30 pF 0.9V DD
(Including Jig and 1.3K Ω 1.5V 1.5V
Scope)
0V
Test Point Test Point

Publication Release Date: February 19, 2002

- 15 - Revision A2
 W49V002FA

Programmer Interface Mode AC Characteristics, continued

AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)

PARAMETER SYMBOL W49V002FA UNIT

MIN. MAX.
Read Cycle Time TRC 300 - nS
Row/Column Address Set Up Time TAS 50 - nS
Row/Column Address Hold Time TAH 50 - nS
Address Access Time TAA - 200 nS
Output Enable Access Time TOE - 100 nS
#OE Low to Active Output TOLZ 0 - nS
#OE High to High-Z Output TOHZ - 50 nS
Output Hold from Address Change TOH 0 - nS

Write Cycle Timing Parameters

PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Reset Time TRST 1 - - µS
Address Setup Time TAS 50 - - nS
Address Hold Time TAH 50 - - nS
R/#C to Write Enable High Time TCWH 50 - - nS
#WE Pulse Width TWP 100 - - nS
#WE High Width TWPH 100 - - nS
Data Setup Time TDS 50 - - nS
Data Hold Time TDH 50 - - nS
#OE Hold Time TOEH 0 - - nS
Byte programming Time TBP - 50 100 µS
Erase Cycle Time TEC - 0.15 0.2 S
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.

Data Polling and Toggle Bit Timing Parameters

PARAMETER SYMBOL W49V002FA UNIT
MIN. MAX.
#OE to Data Polling Output Delay TOEP - 40 nS
#OE to Toggle Bit Output Delay TOET - 40 nS

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 W49V002FA

TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE

Read Cycle Timing Diagram

#RESET
TRST
TRC

A[10:0] Column Address Row Address Column Address Row Address

TAS TAH TAS TAH

R/#C

VIH
#WE
TAA
#OE
TOH

TOE T OHZ
TOLZ
High-Z High-Z
DQ[7:0] Data Valid

Write Cycle Timing Diagram

TRST

#RESET

A[10:0] Column Address Row Address

TAS TAH TAS TAH

R/#C

TCWH TOEH

#OE

TWP TWPH
#WE

TDH
TDS

DQ[7:0] Data Valid

Publication Release Date: February 19, 2002

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 W49V002FA

Timing Waveforms for Programmer Interface Mode, continued

Program Cycle Timing Diagram

Byte Program Cycle

A[10:0]

(Internal A[17:0]) 5555 2AAA 5555 Programmed Address

DQ[7:0] AA 55 A0 Data-In

R/#C

#OE
T WPH TBP
#WE TWP

Byte 0 Byte 1 Byte 2 Byte 3 Internal Write Start

Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

#DATA Polling Timing Diagram

A[10:0]
(Internal A[17:0]) An An An An

R/#C

#WE

#OE

TOEP
DQ7 X X X
X
TBP or TEC

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 W49V002FA

Timing Waveforms for Programmer Interface Mode, continued

Toggle Bit Timing Diagram

A[10:0]

R/#C

#WE

#OE

TOET
DQ6

TBP or TEC

Boot Block Lockout Enable Timing Diagram

Six-byte code for 3.3V-only software chip erase

A[10:0]

(Internal A[17:0]) 5555 2AAA 5555 5555 2AAA 5555

DQ[7:0] AA 55 80 AA 55 40

R/#C

#OE
TWP TWC
#WE
TWPH

SB0 SB1 SB2 SB3 SB4 SB5

Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

Publication Release Date: February 19, 2002

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 W49V002FA

Timing Waveforms for Programmer Interface Mode, continued

Chip Erase Timing Diagram

Six-byte code for 3.3V-only software chip erase

A[10:0]

(Internal A[17:0]) 5555 2AAA 5555 5555 2AAA 5555

DQ[7:0] AA 55 80 AA 55 10

R/#C

#OE
TWP TEC

#WE TWPH

SB0 SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts

Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].

Sector Erase Timing Diagram

Six-byte code for 3.3V-only software

sector erase

A[10:0]

(Internal A[17:0]) 5555 2AAA 5555 5555 2AAA SA

DQ[7:0] AA 55 80 AA 55 30

R/#C

#OE
TWP TEC
#WE
TWPH

SB0 SB1 SB2 SB3 SB4 SB5 Internal Erase starts

Note: The internal address A[17:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[6:0] are mapped to the internal A[17:11].
SA = Sector Address, Please ref. to the "Table of Command Definition"

- 20 -
 W49V002FA

FWH INTERFACE MODE AC CHARACTERISTICS

AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0.6 VDD to 0.2 VDD
Input Rise/Fall Slew Rate 1 V/nS
Input/Output Timing Level 0.4 VDD / 0.4 VDD
Output Load 1 TTL Gate and CL = 10 pF

AC Test Load and Waveform

DOUT DOUT

Input Output
10 pF 10 pF V DD
25 Ω 25 Ω
0.6V DD
0.4V DD 0.4V DD
0.2VDD

Test Point Test Point

Test when output from low to high Test when output from high to low

Read/Write Cycle Timing Parameters

(VDD = 3.3V ± 5%, VGND = 0V, TA = 0 to 70° C)

PARAMETER SYMBOL W49V002FA UNIT

MIN. MAX.
Clock Cycle Time TCYC 30 - nS
Input Set Up Time TSU 7 - nS
Input Hold Time THD 0 - nS
Clock to Data Valid TKQ - 11 nS

Reset Timing Parameters

PARAMETER SYM. MIN. TYP. MAX. UNIT
VDD stable to Reset Active TPRST 1 - - mS
Clock Stable to Reset Active TKRST 100 - - µS
Reset Pulse Width TRSTP 100 - - nS
Reset Active to Output Float TRSTF - - 50 nS
Reset Inactive to Input Active TRST 1 - - µS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.

Publication Release Date: February 19, 2002

- 21 - Revision A2
 W49V002FA

TIMING WAVEFORMS FOR FWH INTERFACE MODE

Read Cycle Timing Diagram

TCYC

CLK

#RESET TSU THD

FWH4
TSU THD TKQ

Start
FWH IDSEL Address M Size TAR Sync Data Next Start
Read
FWH[3:0] TAR
1101b 0000b XXXXb XA[22]XXb XXA[17:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b] 1111b Tri-State 0000b D[3:0] D[7:4] 0000b

1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data out 2 Clocks 1 Clock

Note: When A22 = high, the host will read the BIOS code from the FWH device.
While A22 = low, the host will read the GPI (Add = FFBC0100) or
Product ID (Add = FFBC0000/FFBC0001) from the FWH device

Write Cycle Timing Diagram

TCYC

CLK

#RESET

FWH4
TSU THD

Start
FWH
IDSEL Address M Size Data TAR Sync Next Start
Write
FWH[3:0]
1110b 0000b XXXXb XXXXb XXA[17:16]b A[15:12] A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b TAR 0000b

1 Clock 1 Clock Load Address in 7 Clocks Load Data in 2 Clocks 2 Clocks 1 Clock 1 Clock

- 22 -
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

Program Cycle Timing Diagram

CLK

#RESET

FWH4

Data TAR Start next

1st Start IDSEL Address M Size Sync TAR command
FWH[3:0 ] XXXXb XXXXb XXXXb 0101b 0101b 0101b 1111b 0000b
1110b 0000b X101b 0000b 1010b 1010b Tri-State 1111b Tri-State

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" in 2 Clocks 2 Clocks 1 Clock 2 Clocks 1 Clock

Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
2nd Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0 ] 1110b XXXXb XXXXb XXXXb X010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b 1111b Tri-State
0000b

Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clock

1 Clock 1 Clock in 2 Clocks 2 Clocks 1 Clock

Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
3rd Start IDSEL Address M Size Data TAR Sync TAR command

FWH[3:0 ] 1110b 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 0000b 1010b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "A0" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks

Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4 Internal
program start

IDSEL Address M Size Data TAR Sync TAR

4th Start

FWH[3:0 ] 1110b 0000b XXXXb XXXXb XXA[17:16]b A[15:12] A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State Internal
program start
1 Clock 1 Clock Load Ain in 7 Clocks Load Din in 2 Clocks 2 Clocks 1 Clock 2 Clocks

Write the 4th command(target location to be programmed) to the device in FWH mode.

Publication Release Date: February 19, 2002

- 23 - Revision A2
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

#DATA Polling Timing Diagram

CLK

#RESET

FWH4

Start IDSEL Address M Size Data TAR Sync TAR Next Start
FWH[3:0] XXXXb
1110b 0000b XXXXb XXA[17:16]b An[15:12] An[11:8] An[7:4] An[3:0] 0000b Dn[3:0] Dn[7:4] 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "An" in 7 Clocks Load Data "Dn" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the last command(program or erase) to the device in FWH mode.

CLK

#RESET

XXXXb
FWH4

Start IDSEL Address M Size TAR Sync Data TAR Next Start
FWH[3:0]
1101b 0000b XXXXb XXXXb An[15:12] An[11:8] An[7:4] An[3:0] 0000b 1111b Tri-State 0000b 1111b Tri-State
XXA[17:16]b XXXXb Dn7,xxx

1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data out 2 Clocks 2 Clocks 1 Clock

Read the DQ7 to see if the internal write complete or not.

CLK

#RESET

FWH4

Start IDSEL Address M Size TAR Sync Data TAR Next Start
FWH[3:0]
1101b 0000b XXXXb XXXXb XXA[17:16]b An[15:12] An[11:8] An[7:4] An[3:0] 0000b 1111b Tri-State 0000b XXXXb Dn7,xxx 1111b Tri-State

1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data out 2 Clocks 2 Clocks 1 Clock

When internal write complete, the DQ7 will equal to Dn7.

- 24 -
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

Toggle Bit Timing Diagram

CLK

#RESET

FWH4

Start IDSEL Address M Size Data TAR Sync TAR Next Start
FWH[3:0] XXXXb XXXXb
1110b 0000b XXA[17:16]b A[15:12] A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "An" in 7 Clocks Load Data "Dn" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the last command(program or erase) to the device in FWH mode.

CLK

#RESET

FWH4

Start IDSEL Address M Size TAR Sync Data TAR Next Start
FWH[3:0]
1101b 0000b XXXXb XXXXb XXXXb XXXXb XXXXb XXXXb XXXXb 0000b 1111b Tri-State 0000b XXXXb X,D6,XXb 1111b Tri-State

1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data out 2 Clocks 2 Clocks 1 Clock

Read the DQ6 to see if the internal write complete or not.

CLK

#RESET

FWH4

Start IDSEL Address M Size TAR Sync Data TAR Next Start
FWH[3:0]
1101b XXXXb XXXXb XXXXb XXXXb XXXXb XXXXb XXXXb 0000b 1111b Tri-State 0000b XXXXb X,D6,XXb 1111b Tri-State
0000b

1 Clock 1 Clock Load Address in 7 Clocks 2 Clocks 1 Clock Data out 2 Clocks 2 Clocks 1 Clock

When internal write complete, the DQ6 will stop toggle.

Publication Release Date: February 19, 2002

- 25 - Revision A2
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

Boot Block Lockout Enable Timing Diagram

CLK

#RESET

FWH4

Data TAR Start next

1st Start IDSEL Address M Size Sync TAR command
FWH[3:0]
XXXXb XXXXb XXXXb 0101b 0101b 0000b 1111b Tri-State 0000b 1111b Tri-State
1110b 0000b X101b 0101b 1010b 1010b

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
2nd Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0] XXXXb
1110b 0000b XXXXb XXXXb X010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clocks 2 Clocks 1 Clock
in 2 Clocks
Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
3rd Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0] 1110b XXXXb XXXXb XXXXb 0101b 0000b 1000b 1111b Tri-State 0000b 1111b Tri-State
0000b X101b 0101b 0101b 0000b

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "80" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
4th Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0] XXXXb
1110b XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
0000b

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
5th Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0] XXXXb XXXXb
1110b 0000b XXXXb X010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4
Internal
program start

IDSEL Address M Size Data TAR Sync TAR

6th Start
FWH[3:0]
1110b 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 0000b 0100b 1111b Tri-State 0000b 1111b Tri-State Internal
program start
1 Clock 1 Clock Load Address "5555" 7 Clocks Load Data "40" 2 Clocks 1 Clock 2 Clocks
in 2 Clocks
Write the 6th command to the device in FWH mode.

- 26 -
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

Chip Erase Timing Diagram

CLK

#RESET

FWH4

Data TAR Start next

1st Start IDSEL Address M Size Sync TAR command

FWH[3:0] XXXXb XXXXb XXXXb X101b 1111b Tri-State 0000b 1111b

1110b 0000b 0101b 0101b 0101b 0000b 1010b 1010b Tri-State

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
2th Start IDSEL Address M Size Data TAR Sync TAR command

FWH[3:0] 1110b 0000b XXXXb XXXXb XXXXb X010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
IDSEL Address M Size Data TAR Sync TAR command
3th Start

FWH[3:0] XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 0000b 1000b 1111b Tri-State 0000b 1111b
1110b 0000b Tri-State

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "80" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
4th Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0]
1110b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State
0000b

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
5th Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0] XXXXb XXXXb
1110b 0000b XXXXb X010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4
Internal
erase start

Address Data TAR Sync TAR

6th Start IDSEL M Size
FWH[3:0]
1110b 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 0000b 0001b 1111b Tri-State 0000b 1111b Tri-State Internal
erase start
1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "10" 2 Clocks 1 Clock 2 Clocks
in 2 Clocks
Write the 6th command to the device in FWH mode.

Publication Release Date: February 19, 2002

- 27 - Revision A2
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

Sector Erase Timing Diagram

CLK

#RESET

FWH4

Start next
Address M Size Data TAR Sync TAR command
1st Start IDSEL

FWH[3:0] 1110b 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 1st command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
2nd Start IDSEL Address M Data TAR Sync TAR command
Size
FWH[3:0] 1110b XXXXb XXXXb XXXXb 0000b 1111b 0000b 1111b Tri-State
0000b X010b 1010b 1010b 1010b 0101b 0101b Tri-State

1 Clock 1 Clock Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 2nd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
3rd Start IDSEL Address M Size Data TAR Sync TAR command

FWH[3:0] 1110b 0000b XXXXb XXXXb X101b 0000b Tri-State 0000b

XXXXb 0101b 0101b 0101b 0000b 1000b 1111b 1111b Tri-State

1 Clocks1 Clocks Load Address "5555" in 7 Clocks Load Data "80" 2 Clocks 1 Clocks 2 Clocks 1 Clocks
in 2 Clocks
Write the 3rd command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
4th Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0]
1110b 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 1010b 1010b 1111b Tri-State 0000b 1111b Tri-State

1 Clock 1 Clock Load Address "5555" in 7 Clocks Load Data "AA" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 4th command to the device in FWH mode.

CLK

#RESET

FWH4

Start next
5th Start IDSEL Address M Size Data TAR Sync TAR command
FWH[3:0] 1111b
1110b 0000b XXXXb XXXXb XXXXb X010b 1010b 1010b 1010b 0000b 0101b 0101b 1111b Tri-State 0000b Tri-State

1 Clock 1 Clock Load Address "2AAA" in 7 Clocks Load Data "55" 2 Clocks 1 Clock 2 Clocks 1 Clock
in 2 Clocks
Write the 5th command to the device in FWH mode.

CLK

#RESET

FWH4
Internal
erase start

IDSEL Address M Size Data TAR Sync TAR

6th Start
FWH[3:0]
1110b 0000b XXXXb XXXXb XXA[17:16]b SA[15:12] XXXXb XXXXb XXXXb 0000b 0000b 0011b 1111b Tri-State 0000b 1111b Tri-State Internal
erase start

1 Clock 1 Clock Load Sector Address in 7 Clocks Load Din 2 Clocks 1 Clock 2 Clocks
in 2 Clocks
Write the 6th command(target sector to be erased) to the device in FWH mode.

- 28 -
 W49V002FA

Timing Waveforms for FWH Interface Mode, continued

FGPI Register/Product ID Readout Timing Diagram

CLK

#RESET

FWH4

Start IDSEL Address M Size TAR Sync Data TAR Next Start
FWH[3:0] 1101b 0001b 0000b
0000b A[27:24] A[23:20] A[19:16] 0000b 0000b 0000b Tri-State 1111b 0000b D[3:0] D[7:4] Tri-State 1111b
/0000b /0001b

1 Clock 1 Clock Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register 2 Clocks 1 Clock Data out 2 Clocks 2 Clocks 1 Clock
& "FFBC0000(hex)/FFBC0001(hex) for Product ID

Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins.

Reset Timing Diagram

VDD TPRST

CLK

TKRST

TRSTP
#RESET

TRST
TRST
F

FWH[3:0]

FWH4

Publication Release Date: February 19, 2002

- 29 - Revision A2
 W49V002FA

ORDERING INFORMATION
PART NO. ACCESS POWER SUPPLY STANDBY VDD PACKAGE
TIME CURRENT MAX. CURRENT MAX.
(nS) (mA) (µA)
W49V002FAP 11 25 20 32L PLCC
W49V002FAQ 11 25 20 32L STSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.

HOW TO READ THE TOP MARKING

Example: The top marking of 32L-PLCC W49V002FA

W49V002FAP
2123055C-082
132GHSA

st
1 line: winbond logo
nd
2 line: the part number: W49V002FAP
rd
3 line: the lot number
th
4 line: the tracking code: 132 G H SA

132: Packages made in ’01, week 32

G: Assembly house ID: A means ASE, G means Greatek, ...etc.

H: IC revision; A means version A, H means version H, ...etc.

SA: Process code

- 30 -
 W49V002FA

PACKAGE DIMENSIONS
32L PLCC

Dimension in Inches Dimension in mm

Symbol
Min. Nom. Max. Min. Nom. Max.
HE

E
A 0.140 3.56

A1 0.020 0.50
4 1 32 30
A2 0.105 0.110 0.115 2.67 2.80 2.93

b1 0.026 0.028 0.032 0.66 0.71 0.81

0.016 0.022 0.41 0.56

b 0.018 0.46
5 29 0.008 0.014 0.20 0.35
c 0.010 0.25

D 0.547 0.550 0.553 13.89 13.97 14.05

E 0.447 0.450 0.453 11.35 11.43 11.51

e 0.044 0.050 0.056 1.12 1.27 1.42

GD 0.490 0.510 0.530 12.45 12.95 13.46

D HD
GD GE 0.390 0.410 0.430 9.91 10.41 10.92

HD 0.585 0.590 0.595 14.86 14.99 15.11

HE 0.485 0.490 0.495 12.32 12.45 12.57

L 0.075 0.090 0.095 1.91 2.29 2.41

y 0.004 0.10

θ 0° 10° 0° 10°
13 21

Notes:
1. Dimensions D & E do not include interlead flash.
14 20 c
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
L
visual inspection sepc.
A2 A

θ e b A1
Seating Plane b1

y
GE

32L STSOP (8 x 14 mm)

HD

D Dimension in Inches Dimension in mm

Symbol
c
Min. Nom. Max. Min. Nom. Max.

A 0.047 1.20

e A1 0.002 0.006 0.05 0.15

A2 0.035 0.040 0.041 0.95 1.00 1.05

E b 0.007 0.009 0.010 0.17 0.22 0.27

c 0.004 ----- 0.008 0.10 ----- 0.21

b
D 0.488 12.40

E 0.315 8.00

HD 0.551 14.00

e 0.020 0.50
L 0.020 0.024 0.028 0.50 0.60 0.70

L1 0.031 0.80

Y 0.000 0.004 0.00 0.10

£c
A1 θ 0 3 5 0 3 5
L A2 Y
A
L1

Publication Release Date: February 19, 2002

- 31 - Revision A2
 W49V002FA

VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 April 2001 - Initial Issued
A2 Feb. 19, 2002 4 Modify VDD Power Up/Down Detection in Hardware
Data Protection
6 Modify the description on start in TABLE OF
COMMAND DEFINITION
7 − 10 Delete old flow chart and add embedded algorithm
13 Add in Input High Voltage for #INIT (VIHI) parameter
Change VIL (max.) from 0.2 VDD to 0.3 VDD; VIH (min.)
from 0.6 VDD to 0.5 VDD.
Add the VIHI/ VILI for the #INIT pin input spec.
29 Add HOW TO READ THE TOP MARKING

Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III, 2727 North First Street, San Jose, 27F, 2299 Yan An W. Rd. Shanghai,
Science-Based Industrial Park, CA 95134, U.S.A. 200336 China
Hsinchu, Taiwan TEL: 1-408-9436666 TEL: 86-21-62365999
TEL: 886-3-5770066 FAX: 1-408-5441798 FAX: 86-21-62365998
FAX: 886-3-5665577
http://www.winbond.com.tw/

Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd., 7F Daini-ueno BLDG, 3-7-18 Unit 9-15, 22F, Millennium City,
Neihu Chiu, Taipei, 114, Shinyokohama Kohoku-ku, No. 378 Kwun Tong Rd.,
Taiwan, R.O.C. Yokohama, 222-0033 Kowloon, Hong Kong
TEL: 886-2-8177-7168 TEL: 81-45-4781881 TEL: 852-27513100
FAX: 886-2-8751-3579 FAX: 81-45-4781800 FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

- 32 -