3D IC’s

INTRODUCTION

There is a saying in real estate; when land get expensive, multi-storied

buildings are the alternative solution. We have a similar situation in the chip industry.
For the past thirty years, chip designers have considered whether building integrated
circuits multiple layers might create cheaper, more powerful chips.

Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is being
increasingly dominated by the interconnects due to increasing wire pitch and increasing
die size. Additionally, heterogeneous integration of different technologies on one single
chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.

The three dimensional (3-D) chip design strategy exploits the vertical dimension to
alleviate the interconnect related problems and to facilitate heterogeneous integration of
technologies to realize system on a chip (SoC) design. By simply dividing a planar chip
into separate blocks, each occupying a separate physical level interconnected by short
and vertical interlayer interconnects (VILICs), significant improvement in performance
and reduction in wire-limited chip area can be achieved. In the 3-Ddesign architecture,
an entire chip is divided into a number of blocks, and each block is placed on a separate
layer of Si that are stacked on top of each other.

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of

active devices, have the potential to dramatically enhance chip performance,
functionality, and device packing density. They also provide for microchip architecture
and may facilitate the integration of heterogeneous materials, devices, and signals.
However, before these advantages can be realized, key technology challenges of 3D ICs
must be addressed. More specifically, the processes required to build circuits with
multiple layers of active devices must be compatible with current state-of-the-art silicon
processing technology. These processes must also show manufacturability, i.e.,
reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM
has introduced a scheme for building 3D ICs based on the layer transfer of functional
circuits, and many process and design innovations have been implemented.

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LITERATURE SURVEY
1. Kaustav Banerjee, “3D ICs”
A novel chip design for improving deep sub micro meter interconnect performance and
SoC integration” analysed the limitations of the existing interconnect technologies and
design methodologies and presents a novel three- dimensional (3-D) chip design
strategy that exploits the vertical dimension to alleviate the interconnect related
problems and to facilitate heterogeneous integration of technologies to realize a system-
on-a-chip (SoC) design.

2. Gael Pillonnet, “3D ICs”

An Opportunity for Fully-Integrated, Dense and Efficient Power Supplies” have
evaluated the achievable power efficiency between on- die and in-package converters
using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM,
vertical capacitor) layers.

3. Debabani Choudhury, “3D Integration Technologies for

Emerging Microsystems”
Work is focused on overview of the various 3D integration and enabling
technologies as well as the associated challenges that exist for SFF wireless system
implementation with optimum cost and performance.

4. M.Chrzanowska-Jeske and Mohammad A. Ahmed, “Power

efficiency of 3D v/s 2D ICs”
Here used floor planning tools to evaluate power consumption related to inter- block
connections for digital ICs implemented as 2D and 3D systems & work is focused on 3D
stacking using through-silicon-vias (TSVs).

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BLOCK DIAGRAM AND EXPLANATION

3D integration is the foundation of heterogeneous integration, where more diverse features

are incorporated into a single package. These 3D integrated circuits will make their way
into high-compute processors The advantages of 3D integrated circuits have proven
themselves to the point where three-dimensional structures are used in modern chips.

3D integration is now considered to be a new paradigm for the semiconductor industry.

There are various ways to vertically interconnect devices, with most advanced technology
based on through-silicon vias (TSV). Within wafer level packaging (WLP), the platforms
using TSVs are 3D IC integration and interposers (“2.5 D”). Silicon interposer
technologies
are already mature and used in several production lines. The situation is different when it
comes to “true” 3D ICs. The first companies are just beginning to take the step to
production
of 3D integrated products. This also provides a motivation to investigate the 3D IC patent
  situation.
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3D IC ROADMAP

Like every Semicon West show in the past, where many experts are brought together for
showing the latest and greatest semiconductor manufacturing equipment and bringing
numerous seminar/panel discussions, this Semicon West of 2013 was no different. Two
major issues were discussed, which on the face of it look unrelated, that caught my
attention: Progress in
1.3D - TSV technology, and
2.EUV
Obviously these two issues are very different, but they are quite similar in respect to the
following:
1. As the advanced node progresses to smaller and smaller feature size we are getting
closer to the "end of the road map" or the "end of Moore's law".

Going to EUV does alleviate some of the problems related to the current solution of
double patterning (or quadruple in the future assuming, EUV doesn't come to fruition
soon enough).

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As well, utilizing 3D devices with TSV has, in the grand scheme, a similar outcome;
namely, advancing the integration via 3D structures rather than continued scaling.
Though in the future, 3D devices and advanced nodes could go hand in hand.

2. The big miss of the road map. When one looks at some old road maps from a few
years ago, one can ask how did we, the industry, miss by so much?

This actually reminds me of another miss from a few years ago-the low k inter-metal
dielectric. Fig. 1 shows the low k dielectric roadmap trend of various ITRS published
roadmaps and the prediction in 1999 that by 2004 we would be using k<2 !! Obviously
we know what happened and even today 14 years later it is hard to breakthrough
a k value of 2.5.

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ARCHITECTURE OF 3D IC
3D integration is generally defined as fabrication of stacked and vertically interconnected
device layers. Here, an entire(2-D) chip is divided into a number of blocks, and each
block
is placed on a separate layer of Si that is stacked on top of each other. The cross-sectional
structure of a 3D-IC with stacking thin chips is illustrated in Fig 1. Thin IC chips are
stacked on a thick IC chip in the figure; the thick chip also acts as a supporting material.
A thick chip is indispensable for a mechanical support of thin chips in a 3D-IC shown in
Fig 1. Three methods of wafer-to-wafer bonding, chip-to-wafer bonding and chip-to-chip
bonding are used for the fabrication n of such 3D-IC.

Figure 1: 3D IC architecture

The 3-D architecture offers extra flexibility in system design, placement, and
routing.The
3-D integration would significantly alleviate many of the problems outlined in the
previous
section for SoCs fabricated on a single Si layer. Three - dimensional integration can
reduce
the wiring, thereby reducing the capacitance, power dissipation, and chip area and
therefore improve chip performance.

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A. Through-Silicon Vias (TSV) technology in 3D ICs

A 3D integrated circuit is a single integrated circuit built by stacking silicon wafers
and/or dies and interconnecting them vertically so that they behave as a single device. By
using TSV technology, 3D ICs can pack a great deal of functionality into a small
"footprint." In addition, critical electrical paths through the device can be drastically
shortened, leading to faster operation. The advantage of TSVs over wire-bonding is the
ability to route the connection through the chip, rather than being constrained to the
perimeter. Likewise, the advantage of TSVs over flip-chip construction is the ability to
stack more than two die in a configuration.

Figure 2: Through Silicon Via

Figure 2 illustrates a TSV construction. The amount of space taken up by vias depends
on the number of vias and their cross-section area. The circuit design determines the
number of vias implemented. The TSV is a vertical electrical connection that passes
completely through a silicon wafer or die to produce multilevel chips with an optimum
combination of cost, functionality, performance, and power consumption. By using TSV

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technology, 3D ICs can pack greater functionality into a smaller size and realize shorter
critical electrical paths, resulting in faster operation.

B. 3D IC Bonding topologies

Figure 3:3D-IC Bonding Topologies

3D-IC with TSV can be categorized as face to face (F2F), face to back (F2B), back to
back (B2B) and back to face (B2F). The four topologies are illustrated in Fig. 3. For
F2B, B2B and B2F topology, TSV is necessary for IC to IC communications. For F2F
topology, TSV is optional For two-layer chip stacks, both integration schemes have some
advantages and disadvantages F2B configuration uses standard process for test, assembly
and packaging, however F2F do not have a standard process [8]. For multi-layer stacks,
F2B has the advantage that after each bonding step, the top device layer is face up so that
the stacking unit process can be repeated multiple times. However, for F2B integration,
the die wafer has to have the final thickness already during stacking, as subsequent
thinning is not possible. In F2F stacking configuration wafer thinnung is not a required.

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MANUFACTURUING PROCESSES

Different manufacturing processes of 3D IC’s are:

1. MONOLITHIC
2. WAFER-TO-WAFER
3. DIE-TO-WAFER
4. DIE-TO-DIE

1. MONOLITHIC

 A technology breakthrough allows the fabrication of semiconductor devices with

multiple thin tiers (<1um) of copper-connected active devices utilizing
conventional fab equipment.

 Electronic components and their connections (wiring) are built in layer on single
semiconductor wafer, which is then diced into 3D IC’s.

 There is only one substrate, hence no need for aligning, thinning.bonding, or

through-silicon via.

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2. WAFER-TO-WAFER

 Wafer-to-wafer technique is a way to build electronic components on two or more

semiconductor wafers that are then aligned, bonded and then diced into 3D ICs.

 Vertical connections can be stacked after Wafers Sequentially Op align, bond.

thin and Interconnection bonding but, they are preferably built into the wafer
before bonding. Wafer can be thinned before or after bonding.

 Wafer-to-wafer bonding can reduce yields, since if any 1 of N chips in a 3DIC

are defective, the entire 3D IC will be defective.

 The wafers must be the same size, but many exotic materials (e.g. III-Vs) are
manufactured on much smaller wafers than CMOS logic or DRAM (typically 300
mm). This complicates heterogeneous integration.

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3. DIE-TO-WAFER

 Electronic components are built on two semiconductor wafers.

 One wafer is diced; the simulated dice are aligned and bonded onto die sites
of the second wafer.

 As in the wafer-on-wafer method, thinning and TSV creation are performed

either before or after bonding.

 Additional die may be added to the stacks before dicing.

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4. DIE-TO-DIE

 Electronic components are built on multiple die, which are then aligned and
bonded.

 Thinning and TSV creation may be done before or after bonding. One
advantage of die-to-die is that each component die can be tested first, so that
one bad die does not ruin an entire stack.

 Moreover, each die in the 3D IC can be binned beforehand, so that they can
be mixed and matched to optimize power consumption and performance

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PHYSICAL DESIGNS

Physical designs of 3D-IC which needs to be done meticulously to get the optimum
result are:

1) Architecture exploration

2) Floor Planning

3) Placement

4) Routing

5) Layout Editing

PERFORMANCE CHARACTERISTICS
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1) Timing

2) Energy

ADVANTAGES AND DISADVANTAGES

The 3D IC’s have many advantages and some disadvantages which are listed below.

ADVANTAGES OF 3D IC’s

The general structure of a 3D integrated circuit in VLSI design is relatively simple, as

displayed in the graphic below. In this type of system, an integrated circuit is constructed
by stacking feature layers on top of each other. By stacking individual die/wafer layers
vertically, the length of the connection required to route an electrical signal between two
circuits is shorter. This shorter interconnect provides the advantages of 3D integrated

circuits.

There are four advantages of 3D integrated circuits:

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 Lower Power Consumption
Lower power consumption has motivated smaller package sizes, and novel interconnect
designs since the late 1990s. At some point, the only way to get to smaller package sizes
in an integrated circuit was to stack the design in 3D. The smaller interconnect length
allows for reduced power consumption due to lower DC resistive losses over the length
of an interconnect. This is important as designs have scaled to smaller technology nodes,
requiring thinner interconnects with larger DC resistance.

 Faster Signal Transitions

Because shorter interconnects are used in these designs, the total capacitance of a vertical
interconnect is smaller than a horizontal interconnect. This means signals in
interconnects will see a lower RC time constant and make faster transitions between ON
and OFF states. Additionally, there is a lower signal delay on an interconnect as the total
parasitic capacitance is lower, ensuring faster propagation of switching from inputs to
outputs. These factors enable higher serial data rates with digital signals.

 Analog and Digital Integration

3D integration enables the integration of analog and digital circuit blocks into the same
package with fewer signal integrity concerns and without significantly increasing the
package size. In these packages, the digital and analog blocks can be separated in a
planar arrangement. Still, more features can be added to each block vertically without
unduly increasing the package size. By isolating blocks into their regions, crosstalk and
noise coupling is easier to control and will not create major signal problems in these
designs.

 Space Savings
Finally, the most obvious benefit is space savings as package sizes are smaller.
Vertically stacked 3D integrated circuits can be kept very thin, which is advantageous
compared to spreading circuit blocks out over the expanse of a semiconductor die. As a

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result, more components and features can be packed onto a PCB to enable higher-density
designs with advanced packages.

Although these packages have many practical and signal integrity advantages, simulation
tools are needed to ensure designs operate as intended. At the circuit level, reliability is
assessed with SPICE simulations, while physical layout and package level simulations
are performed with a field solver application. Advanced packaging should be treated
using a multiphysics approach to assess thermal reliability. Integrated circuit designers
can ideally identify packaging problems before prototyping and make design
modifications early.

DISADVANTAGES OF 3D IC’s

While 3D integrated circuits (3D ICs) offer many advantages over traditional 2D ICs,
there are also some disadvantages that need to be considered. Some of the main
disadvantages of 3D ICs are:

 Complexity
3D ICs are more complex than traditional 2D ICs, which makes the design,
manufacturing, and testing processes more challenging. This complexity can also result
in higher costs and longer development times.

 Thermal management
Because of their vertical stacking, 3D ICs can generate more heat than 2D ICs, which can
affect their performance and reliability. Managing the heat generated by 3D ICs can be
challenging, requiring advanced cooling techniques such as microfluidic cooling or
thermoelectric cooling.
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 Interconnect reliability
The vertical interconnects in 3D ICs, such as through-silicon vias (TSVs), can be more
prone to defects and failures than the interconnects in 2D ICs. This can be due to issues
such as stress-induced defects or mismatched thermal coefficients of expansion between
the different layers.

 Yield
The manufacturing yield of 3D ICs can be lower than that of 2D ICs, meaning that a
higher percentage of the produced chips may be defective or non-functional. This can be
due to the increased complexity of the manufacturing process, the higher density of the
circuits, and the greater likelihood of defects in the vertical interconnects.
Standards: Because 3D ICs are a relatively new technology, there are currently no
established standards for their design, manufacturing, or testing. This lack of standards
can make it more difficult to ensure interoperability between different components and
systems, and can also limit the availability of specialized tools and equipment for 3D IC
development.

APPLICATIONS OF 3D IC’s
Some of the applications of the 3D IC’s are:

 Portable electronic digital cameras.

 Digital audio players.
 Smart cellular phones.
 handheld gaming devices are among the fastest growing technology market for both
business and consumers.
 Portable devices all require small form factors ,battery efficiency, robustness, and
reliability. And that is achieved by these circuits.
 For designing efficient memories.

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 These circuits are used to design PLDs(programmable logic devices).

FUTURE SCOPE

3D integrated circuits evolved from planar processes to create multilayer semiconductor

packages with multiple feature levels. As 3D IC’s are good in power consumption, signal
timing, and mixed signal integration so it is a good technology which we can build the
VLSI circuits with good features like memory efficient, good lifespan and overall in the
IC industry these circuits will take the world into the newer version of efficient circuits
for upcoming years.

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CONCLUSION

3D-IC is one of the most promising candidates for realizing superior performance
computing including AI, IoT, and so on. Several reliability issues still exist in 3D-ICs
caused by lots of TSVs and micro bumps, thinned wafer/chip, and under-fill materials. In
this paper, the most potent reliability issues such as Cu contamination and
thermomechanical stress were evaluated by new methods. Cu diffusion behaviours were
measured with C-t method and it was indicated that the generation lifetime significantly
decreased with the Cu diffusion into the device region from the sidewall scallop of
TSVs. As for local mechanical stresses, it was found that the mechanical stress
distributions induced around micro bump joining were very complicated and it was
necessary for 3D-ICs to optimize fabrication process and circuit layout including TSVs

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and micro bumps. It was also found that the in-plane local stress distributions in 3D-ICs
can be precisely evaluated using retention time changes of the DRAM cell array. Using
these evaluation methods, design guidelines for 3D-ICs can be optimized and highly
reliable 3D ICs will be successfully fabricated.

The 3 D memory will just the first of a new generation of dense, inexpensive chips that
promise to make digital recording media both cheap and convenient enough to replace
the photographic film and audio tape. We can understand that 3-D ICs are an attractive
chip architecture, that can alleviate the interconnect related problems such as delay and
power dissipation and can also facilitate integration of heterogeneous technologies in one
chip. The multilayer chip building technology opens up a whole new world of design like
a city skyline transformed by skyscrapers, the world of chips may never look at the same
again.

BIBILOGRAPHY

 Kaustav banerjee, shukri j souri, pawan kapur and krishna c saraswath, “3-d ics: a
novel chip design for improving deep sub micrometer interconnect performance
and soc integration” at page 602. 2. Electronics today june 2002.

 Gael Pillonnet, Nicolas Jeannioe, Pascal Vivee, “3D ICs: An Opportunity for
Fully
Integrated,Dense and Efficient Power Supplies” , IEEE 2015 International
3D
Systems Integration Conference.

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 Debabani Choudhury, “3D Integration Technologies for Emerging

Microsystems”,
IEEE,2010.

 M. Chrzanowska-Jeske and Mohammad A. Ahmed, “Power efficiency of 3D

vs 2D ICs”, 2013 IEEE.

 W. TOPOL ET AL., “Three-dimensional integrated circuits”, IBM J. RES. &

DEV.
VOL. 50 NO. 4/5 JULY/SEPTEMBER 2006.

 Aashana Pancholi, “3-Dimensional Integrated Circuits”, International Journal

of Scientific & Engineering Research, Volume 4, Issue 6, June-2013.

 Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat, “3-D
Heterogeneous ICs: A Technology for the Next Decade and Beyond”, 5th IEEE
Workshop on Signal Propagation On Interconnects, Venice, Italy May, 13-16,
2001.

 Chien-Lin Huang, Nian-Shyang Chang, Chi-Shi Chen, Chun-Pin Lin, Chien-

Ming Wu, and Chun-Ming Huang, “A Novel Design Methodology for Hybrid
Process :3D-IC”, International Symposium On VLSI Design, Automation and
Test,2012.

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