MICROCONTROLLER

Precision
Measurement Central (4)
Part 4: RS485, or networking the MSC1210 micro
Design by J. Wickenhäuser www.wickenhaeuser.com

The RS485 port on the MSC1210 board provides great opportunities for
communication with other systems. For example, it allows a number of
MSC1210 boards to be connected up into a network and talk to one
another over distances of several kilometres.

This fourth instalment in the series on the

MSC1210-based Precision Measurement Cen-
tral (kicked off in the July/August 2003 issue)
is entirely devoted to the RS485 interface.
This month we will cover the theory and
hardware. The December 2003 issue, finally,
will discuss the practical use of the RS485
interface in a small project that goes to show
how up to 255 MSC1210 boards can commu-
nicate with a single PC through an RS485
link. The converter required for the job is dis-
cussed in this article instalment.

RS485
Although the RS485 interface has been
around virtually since the earliest days of the the two wires designated ‘A’ and ‘B’ OUT over a long cable. An oscillo-
PC era, it is rarely seen in real life, that is, on are required, although it is recom- scope is connected to the bus at the
the PC’s connector panel. That’s why we take mended to implement potential can- indicated position. Any cable will
this opportunity to present a suitable con- cellation using a third wire and an have a more or less distinctive
verter for RS232 to RS485, which has been tai- optional resistor. Another popular impedance — values of 60 to 200 Ω
lored for use in combination with the variant has four wires and allows the being typical. The signal on the
MSC1210 board. First, however, we need to devices to be powered over the bus. cable will remain undistorted only if
wade though some theory. The digital information conveyed the cable is terminated with a resis-
over the RS485 bus comprises the tor whose value is approximately
Bus topology voltage difference between line ‘A’ equal to the cable impedance. Wrong
Normally an RS485 network consists of a long and ‘B’. If the difference is positive, termination values cause signal dis-
cable (bus) of which the ends are terminated the bus is said to convey a logic 1. In tortion that can lead to data corrup-
with resistors. Up to 32 devices may be con- the other case, a logic 0 is conveyed. tion and increased susceptibility of
nected to the bus, or even 256 if a suitable The use of differential voltages the bus to noise.
driver chip is used. Ideally, all devices are makes the bus rather immune to Fortunately, correct cable termi-
connected to form a long thread. In practice, noise, provided a number of condi- nation is really critical only in those
however, individual bus participants may tions are satisfied. Figure 2 shows a cases where signals with a high
also be connected via branches of several bus with two devices on it, where data rate (> 57,600 bits/s) are con-
metres (Figure 1). In ‘minimum’ cases only the signal is to be carried from IN to veyed over cable lengths exceeding

42 Elektor Electronics 11/2003

 MICROCONTROLLER
RX/TX- RE/DE +5V optional resistors. These resistors serve to
CTRL MAX485, MAX487, MAC487E, LT485
and functional equivalents in DIL8 case. pull the bus to a fixed logic level when there is
Attention: RX/TX-CTRL = High activates transmitter
8
(invert for 8051) no traffic (that is, all devices are receiving and
none is putting data on the bus). Unfortu-
RX 1 A
RXD
2 R nately, this variant is rather wasteful in terms
6
to µC 7 RS485 bus of energy usage and at the same time likely
3

TXD
TX 4 D B to cause problems with long cables.
A better alternative is shown in Figure 4.
5
In this configuration, the initial level of the
bus is not known. If a device wants to put a
+5V Device Device Device to individual Device data block on the bus, it has to activate its
devices <10m
#1 #2 #3 #x
transmitter section first. However, as a result
of improper termination as illustrated in Fig-
560Ω
ure 2, it may happen that activation of the
default level
transmitter alone is sufficient for receiving
ZI (120Ω) ZI (120Ω)
optionally
2 x 560Ω devices on the bus to recognise data, when
in fact no valid data has been sent as yet (see
optionally 0–100Ω
560Ω to ground block marked ???).
This leads to the absolute requirement for
length up to 4 km at 115.2 kbits/s a pause to be inserted immediately after acti-
030060 - 4 - 12
vation of each transmitter section. This ‘dead’
period needs to be much longer than pre-
Figure 1. RS485 topology. scribed for the transmission of a single byte
(t_byte). The time needed to convey a byte
over the bus is roughly ten times the recipro-
500 m, when the propagation times enough, but longish cables in partic- cal of the baud rate, or about 1 ms per byte
start to approach the bit rates (the ular are prone to pick up (by induc- when a rate of 9,600 bits/s is used.
signal travels 100-300 m in 1 µs). tion) much higher peak voltages The data packet proper always starts with
With cable lengths under 50 m and caused by electrostatic fields, dis- a special marker byte (START). Note, how-
bit rates under 57,600, a cheap cable charges, EMI transients and so on. ever, that START may never occur within the
with no specified impedance but ter- Consequently it makes sense to pro- actual data (more about this in the next
minated with 120 Ω at both ends tect all RS485 against voltage surges. instalment).
should be adequate. With suitable protection, short and Because only one device can transmit at a
not too powerful transients can not time (‘half duplex’) a strict protocol is needed
Overvoltage Protection ‘lite’ harm the drivers ICs (Figure 3). describing who’s allowed to transmit what
An RS485 driver must be capable of and when. If the protocol is not observed,
withstanding line voltages between Data traffic data contention, collision and corruption is
–7 V and +12 V at its input(s). Fair The drawing in Figure 1 includes all imminent. The practical application dis-

oscilloscope

long cable to RS485 driver

ZI
with Zi (120Ω) 50Ω A
B

50Ω B
transmitter receiver

termination correct: Z i = 120 Ω

A B
9V6 9V6

termination too low: Z i approx. 60 Ω

5V1 5V1

device GND
RS485 (not network!)
030060 - 4 - 14

termination too high: Z i approx. 250 Ω

030060 - 4 - 13

Figure 3. Surge protection by means of two

Figure 2. Why terminate? zener diodes.

11/2003 Elektor Electronics 43

MICROCONTROLLER
cussed in next month’s instalment employs a
transmitter ON data
simple but effective protocol.

??? START ... ...

A PC on the RS485 bus
time
If the two 560-Ω resistors shown in Figure 1
are used, the risk of ‘undesired databytes’ is > t_byte t_byte
greatly reduced. Problems may only occur
030060 - 4 - 15
with long cables (>50 m) and higher baud
rates (>57,600 bits/s), particularly when the
transmitting junction and the resistors are rel- Figure 4. Transmit timing.
atively far apart. Unfortunately, a PC can not
exercise exact control over the pulse timing
on its serial interface and so activate the bit rates. The design consists of an used to include the terminator resis-
transmitting device using an appropriate RS232 and an RS485 converter sepa- tor, and/or S1.2/3 (operate at the
delay. After all, most PCs employ a UART rated by good old TTL levels. same time) for the 560-Ω resistors to
(RS232 driver) with an internal transmitter Bits arriving at the RS485 bus are set the default level on the bus.
FIFO. This prevents the PC from ‘knowing’ copied directly to the PC irrespective These provisions on the converter
whether or not a databyte was actually sent or of the bit rate. Once the PC sends a allow several PCs or a combination
not. Consequently it is the task of the PC con- character, the converter immediately of PCs and MSC1210 boards to be
verter to ensure that the RS485 bus is at a switches on its transmitter via a included in a network.
valid logic level when there is no traffic. retriggerable monostable (IC1.A). The construction of the converter
The transmitter remains active for on the printed circuit board shown in
the time its takes to convey the byte. Figure 6 should be an uncomplicated
The converter In the case of our circuit, two times affair as there are no pitfalls with
The converter, of which the circuit diagram is may be selected: 20 ms for regard to soldering etc. The introduc-
given in Figure 5, operates largely as a 1200 bits/s (S1 opened) or 2 ms for tory photograph shows the author’s
’dumb’ extension which has the benefit of it 9600 bits/s and higher (S1 closed). prototype. The converter operates
supporting different protocols and, of course, In addition, switch S1.4 may be from an external supply voltage of

IC3
+5V +5V 7805 D1

1N4001
C2 16
C11 C9 C12 C10
IC4
100n 8
10µ 100n 100n 10µ
16V 35V

+5V +5V +5V +5V

C6
10µ
7
D6 D7 C7
S1.2

16V PullUp
2
RECEIVE READY/TRANSMIT 100n
V+ 2
1 16
K1 C5 C1+ R6 R7 IC2 R4
8 5 K2
560Ω
1k

1k

S1.4

1 DCD 3 IC1 Term. 1

10µ C1– (+)7-30V
6 DSR 16V 14 11 1
T1OUT T1IN 4
R9
2 RXD 7 10 2 R 2
T2OUT T2IN 6 47Ω RS485-A
7 RTS 13 12
R1IN R1OUT 7 R8
3 TXD 8 9 3 3
R2IN R2OUT 47Ω RS485-B
8 CTS 4 C8 4 D
C3 C2+ +5V D2 D3 R3 R5
4 DTR 4
560Ω

120Ω

MAX232 GND
9 100n
RI 10µ 5 15
8
C2– 5
16V V- LTC485
S1.1

5 GND 9V1 9V1

Delay MAX487E
6 D5 D4 6
C1 1
S1.3

SUB-D9 R2 R1 PullDn.
22k

220k

10µ 4V7 4V7 3

16V
C4

220n
15 14 7 6
RX/CX CX RX/CX CX
1 13 9 5
2 & 10 & IC4 = 74HCT123
3 IC4.A 4 11 IC4.B 12
+5V
030060 - 4 - 11

Figure 5. Circuit diagram of the RS232/RS485 converter.

44 Elektor Electronics 11/2003

 MICROCONTROLLER
COMPONENTS LIST
Resistors:
R1 = 220kΩ D4,D5 = 4V7 zener diode
R2 = 22kΩ D6 = LED, low current, green, 3mm
R3,R4 = 560Ω D7 = LED, low current, red, 3mm
R5 = 120Ω IC1 = MAX232 (DIL case)
R6,R7 = 1kΩ IC2 = LTC485 or MAX487E
R8,R9 = 47Ω (ESD/EMI-optimised) (DIL case)
IC3 = 7805 (TO220 case)
Capacitors: IC4 = 74HCT123 (DIL case) (Philips
C1,C3,C5,C6,C11 = 10µF 16V radial preferred)
C2,C7,C8,C9,C12 = 100nF
C4 = 220nF (10% tolerance) Miscellaneous:
C10 = 10µF 35V radial K1 = 9-way sub-D socket, PCB
mount, angled pins
Semiconductors: K2 = 4-way PCB terminal block, 5mm
D1 = 1N4001 (DO41 case) lead pitch
D2,D3 = 9V1 zener diode S1 = 4-way DIL switch

between 7 V and 30 V and draws a

modest 20 mA or so. In case the sup-
ply voltage is not obtained from the
bus, the RS485 ground is connected
to the circuit ground using a 100-Ω
resistor for potential equalisation. Figure 6. PCB design for the
(030060-4) RS232/RS485 converter.

11/2003 Elektor Electronics 45

030060-4

non reflected

030060-4

reflected
 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

D Bidirectional Transceivers D OR P PACKAGE

D Meet or Exceed the Requirements of ANSI

(TOP VIEW)

Standards TIA/EIA-422-B and TIA/EIA-485-A R 1 8 VCC

and ITU Recommendations V.11 and X.27 RE 2 7 B
D Designed for Multipoint Transmission on DE 3 6 A
Long Bus Lines in Noisy Environments D 4 5 GND
D 3-State Driver and Receiver Outputs
D Individual Driver and Receiver Enables
D Wide Positive and Negative Input/Output
Bus Voltage Ranges
D Driver Output Capability . . . ± 60 mA Max
D Thermal Shutdown Protection
D Driver Positive and Negative Current
Limiting
D Receiver Input Impedance . . . 12 kΩ Min
D Receiver Input Sensitivity . . . ± 200 mV
D Receiver Input Hysteresis . . . 50 mV Typ
D Operate From Single 5-V Supply

description
The SN65176B and SN75176B differential bus transceivers are monolithic integrated circuits designed for
bidirectional data communication on multipoint bus transmission lines. They are designed for balanced
transmission lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations
V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ,
an input sensitivity of ± 200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B is characterized for operation from – 40°C to 105°C and the SN75176B is characterized for
operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

Function Tables

DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z

RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
A–B RE R
VID ≥ 0.2 V L H
– 0.2 V < VID < 0.2 V L ?
VID ≤ – 0.2 V L L
X H Z
Open L ?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

logic symbol† logic diagram (positive logic)

3
3 DE
DE EN1
2 4
RE EN2 D
2
RE
6 6
4 1 A 1 A
D 7 R 7 Bus
1 B B

1
R 2

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT

VCC VCC VCC

85 Ω
R(eq) NOM

16.8 kΩ 960 Ω
Input NOM NOM

960 Ω
NOM Output

GND
Driver input: R(eq) = 3 kΩ NOM Input/Output
Enable inputs: R(eq )= 8 kΩ NOM Port
R(eq) = equivalent resistor

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10 V to 15 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

recommended operating conditions

MIN TYP MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
12
Voltage at any bus terminal (separately or common mode),
mode) VI or VIC V
–7
High-level input voltage, VIH D, DE, and RE 2 V
Low-level input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 3) ± 12 V
Driver – 60 mA
High level output current,
High-level current IOH
Receiver – 400 µA
Driver 60
Low level output current,
Low-level current IOL mA
Receiver 8
SN65176B – 40 105
free air temperature,
Operating free-air temperature TA °C
SN75176B 0 70
NOTE 3: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
VIK Input clamp voltage II = – 18 mA – 1.5 V
VO Output voltage IO = 0 0 6 V
|VOD1| Differential output voltage IO = 0 1.5 3.6 6 V
1/2 VOD1
RL = 100 Ω, See Figure 1 V
|VOD2| g
Differential output voltage or 2¶
RL = 54 Ω, See Figure 1 1.5 2.5 5 V
VOD3 Differential output voltage See Note 4 1.5 5 V
Change
g in magnitude
g of differential output
∆|VOD| ± 0.2
02 V
voltage§
+3
VOC Common mode output voltage
Common-mode RL = 54 Ω or 100 Ω
Ω, See Figure 1 V
–1
Change
g in magnitude
g of common-mode
∆|VOC| ± 0.2
02 V
output voltage§
Output disabled,, VO = 12 V 1
IO Output current mA
See Note 5 VO = – 7 V – 0.8
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V – 400 µA
VO = – 7 V – 250
VO = 0 150
IOS Short circuit output current
Short-circuit mA
VO = VCC 250
VO = 12 V 250
Outputs enabled 42 70
ICC Supply current (total package) No load mA
Outputs disabled 26 35
† The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡ All typical values are at VCC = 5 V and TA = 25°C.
§ ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
¶ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTES: 4. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
5. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.

switching characteristics, VCC = 5 V, RL = 110 kΩ, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time 15 22 ns
RL = 54 Ω
Ω, See Figure 3
tt(OD) Differential-output transition time 20 30 ns
tPZH Output enable time to high level See Figure 4 85 120 ns
tPZL Output enable time to low level See Figure 5 40 60 ns
tPHZ Output disable time from high level See Figure 4 150 250 ns
tPLZ Output disable time from low level See Figure 5 20 30 ns

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A
VO Voa, Vob Voa, Vob
|VOD1| Vo Vo
|VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
(
Vt (Test Termination
|VOD3|
Measurement 2)
∆|VOD| | |Vt| – |Vt| | | |Vt – |Vt| |
VOC |Vos| |Vos|
∆|VOC| |Vos – Vos| |Vos – Vos|
IOS |Isa|, |Isb|
IO |Ixa|, |Ixb| Iia, Iib

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIT + Positive-going input threshold voltage VO = 2.7 V, IO = – 0.4 mA 0.2 V
VIT – Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA – 0.2‡ V
Vhys Input hysteresis voltage (VIT + – VIT –) 50 mV
VIK Enable Input clamp voltage II = – 18 mA – 1.5 V
VID = 200 mV,, IOH = – 400 µ
µA,,
VOH High level output voltage
High-level 27
2.7 V
See Figure 2
VID = – 200 mV,, IOL = 8 mA,,
VOL Low level output voltage
Low-level 0 45
0.45 V
See Figure 2
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ± 20 µA
Other input = 0 V,, VI = 12 V 1
II Line input current mA
See Note 6 VI = – 7 V – 0.8
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V – 100 µA
rI Input resistance VI = 12 V 12 kΩ
IOS Short-circuit output current – 15 – 85 mA
Outputs enabled 42 55
ICC Supply current (total package) No load mA
Outputs disabled 26 35
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 6: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 21 35 ns
VID = 0 to 3 V
V, See Figure 6
tPHL Propagation delay time, high- to low-level output 23 35 ns
tPZH Output enable time to high level 10 20 ns
See Figure 7
tPZL Output enable time to low level 12 20 ns
tPHZ Output disable time from high level 20 35 ns
See Figure 7
tPLZ Output disable time from low level 17 25 ns

PARAMETER MEASUREMENT INFORMATION

RL VID
2 VOH
VOD2
+IOL – IOH
RL VOL
VOC
2

Figure 1. Driver VOD and VOC Figure 2. Receiver VOH and VOL
3V
Input 1.5 V 1.5 V
CL = 50 pF 0V
(see Note A)
RL = 54 Ω
Generator td(OD) td(OD)
50 Ω Output
(see Note B)
90% ≈ 2.5 V
Output 50% 50%
3V 10% 10%
≈ – 2.5 V
tt(OD) tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 3. Driver Test Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

Output 3V
S1 Input 1.5 V 1.5 V
0 V or 3 V 0V
tPZH 0.5 V
CL = 50 pF RL = 110 Ω VOH
Generator (see Note A)
(see Note B) 50 Ω Output 2.3 V
tPHZ Voff ≈ 0 V

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 4. Driver Test Circuit and Voltage Waveforms

5V
3V
Input 1.5 V 1.5 V
RL = 110 Ω
S1 0V
Output
3 V or 0 V
tPZL tPLZ
CL = 50 pF
(see Note A) 5V
Generator
50 Ω 2.3 V 0.5 V
(see Note B) Output
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 5. Driver Test Circuit and Voltage Waveforms

3V
Output Input 1.5 V 1.5 V
Generator
(see Note B) 51 Ω
0V
1.5 V
CL = 15 pF tPLH tPHL
(see Note A) VOH
0V
Output 1.3 V 1.3 V
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 6. Receiver Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

PARAMETER MEASUREMENT INFORMATION

1.5 V S1

2 kΩ S2
–1.5 V 5V

CL = 15 pF 5 kΩ 1N916 or Equivalent
(see Note A)

Generator
(see Note B) 50 Ω

S3

TEST CIRCUIT

3V 3V
Input 1.5 V Input 1.5 V
S1 to 1.5 V S1 to –1.5 V
0V S2 Open 0V S2 Closed
tPZH S3 Closed S3 Open
tPZL
VOH
1.5 V ≈ 4.5 V
Output
Output 1.5 V
0V
VOL

3V 3V
S1 to 1.5 V S1 to – 1.5 V
Input 1.5 V S2 Closed Input 1.5 V S2 Closed
S3 Closed S3 Closed
0V 0V
tPHZ
tPLZ
VOH ≈ 1.3 V
0.5 V
Output Output 0.5 V
≈ 1.3 V VOL

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.

Figure 7. Receiver Test Circuit and Voltage Waveforms

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

TYPICAL CHARACTERISTICS

DRIVER DRIVER
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
5 5
VCC = 5 V VCC = 5 V
4.5 TA = 25°C 4.5 TA = 25°C
VOH – High-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

4 4

3.5 3.5

3 3

2.5 2.5

2 2

1.5 1.5
VOH

1 1

0.5 0.5

0 0
0 – 20 – 40 – 60 – 80 – 100 – 120 0 20 40 60 80 100 120
IOH – High-Level Output Current – mA IOL – Low-Level Output Current – mA

Figure 8 Figure 9
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
VCC = 5 V
3.5 TA = 25°C
VOD – Differential Output Voltage – V

2.5

1.5

1
VOD

0.5

0
0 10 20 30 40 50 60 70 80 90 100
IO – Output Current – mA

Figure 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER vs
HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE†
vs
HIGH-LEVEL OUTPUT CURRENT 5
VCC = 5 V
5 4.5
VID = 200 mV

VOH – High-Level Output Voltage – V

VID = 0.2 V IOH = – 440 µA
4.5 4
TA = 25°C
VOH – High-Level Output Voltage – V

4 3.5

3.5 3

3 2.5

2.5 2
VCC = 5.25 V
2 VCC = 5 V 1.5

1.5 1
VCC = 4.75 V
VOH
1 0.5
VOH

0.5 0
– 40 – 20 0 20 40 60 80 100 120
0 TA – Free-Air Temperature – °C
0 – 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40 – 45 – 50
IOH – High-Level Output Current – mA † Only the 0°C to 70°C portion of the curve applies to the
SN75176B.
Figure 11 Figure 12
RECEIVER RECEIVER
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
LOW-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE
0.6 0.6
VCC = 5 V VCC = 5 V
TA = 25°C VID = – 200 mV
VOL – Low-Level Output Voltage – V

VOL – Low-Level Output Voltage – V

0.5 0.5 IOL = 8 mA

0.4 0.4

0.3 0.3

0.2 0.2
VOL

VOL

0.1 0.1

0 0
0 5 10 15 20 25 30 – 40 – 20 0 20 40 60 80 100 120
IOL – Low-Level Output Current – mA TA – Free-Air Temperature – °C

Figure 13 Figure 14

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101B – JULY 1985 – REVISED JUNE 1999

TYPICAL CHARACTERISTICS

RECEIVER RECEIVER
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
ENABLE VOLTAGE ENABLE VOLTAGE
5 6
VID = 0.2 V VID = – 0.2 V
VCC = 5.25 V
Load = 8 kΩ to GND Load = 1 kΩ to VCC
TA = 25°C 5 TA = 25°C
4 VCC = 5.25 V
VCC = 4.75 V

VO – Output Voltage – V
VCC = 5 V
VO – Output Voltage – V

4
VCC = 5 V
3 VCC = 4.75 V

2
2

VO
VO

1
1

0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
VI – Enable Voltage – V VI – Enable Voltage – V

Figure 15 Figure 16

APPLICATION INFORMATION
SN65176B SN65176B
SN75176B SN75176B

RT RT

Up to 32
Transceivers

NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.

Figure 17. Typical Application Circuit

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

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