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17-Parity Generator and Checker-08-02-2023 PDF

The document discusses parity bits, which are an additional bit added to binary data to detect errors during transmission. A parity generator adds the parity bit to make the total number of 1s either even or odd. A parity checker at the receiving end counts the number of 1s to check if it matches what was transmitted, detecting errors. Even parity generators and checkers use XOR gates to generate a parity bit that results in an even total of 1s.

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614 views12 pages

17-Parity Generator and Checker-08-02-2023 PDF

The document discusses parity bits, which are an additional bit added to binary data to detect errors during transmission. A parity generator adds the parity bit to make the total number of 1s either even or odd. A parity checker at the receiving end counts the number of 1s to check if it matches what was transmitted, detecting errors. Even parity generators and checkers use XOR gates to generate a parity bit that results in an even total of 1s.

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Parity Bit

• The parity generating technique is one of the most widely used error detection
techniques for the data transmission.

• In digital systems, when binary data is transmitted and processed, data may be subjected
to noise so that such noise can alter 0s (of data bits) to 1s and 1s to 0s.

• Hence, parity bit is added to the word containing data in order to make number of 1s
either even or odd.

• Thus it is used to detect errors, during the transmission of binary data.The message
containing the data bits along with parity bit is transmitted from transmitter node to
receiver node.

• At the receiving end, the number of 1s in the message is counted and if it doesn’t match
with the transmitted one, then it means there is an error in the data.
Parity Generator and Checker
• A parity generator is a combinational logic circuit that generates the parity bit in
the transmitter.

• A circuit that checks the parity in the receiver is called parity checker.

• A combined circuit of parity generators and parity checkers are commonly used in
digital systems to detect the single bit errors in the transmitted data word.

• The sum of the data bits and parity bits can be even or odd. In even parity, the
added parity bit will make the total number of 1s an even amount whereas in odd
parity the added parity bit will make the total number of 1s odd amount.
Even Parity Generator
• The basic principle involved in the implementation of parity circuits is that sum of odd
number of 1s is always 1 and sum of even number of 1s is always zero.

• Such error detecting and correction can be implemented by using Ex-OR gates (since Ex-
OR gate produce zero output when there are even number of inputs).

• Even parity generator is a combinational circuit that accepts an n-1 bit stream data and
generates the additional bit that is to be transmitted with the bit stream. This additional
or extra bit is termed as a parity bit.

• In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data
stream and the parity bit is ‘1’ if there are odd number of 1s in the data stream.
Even Parity Generator
• Let us assume that a 3-bit message is to be transmitted with an even parity bit.

• Let the three inputs A, B and C are applied to the circuits and output bit is the
parity bit P.

• The total number of 1s must be even, to generate the even parity bit P.

• To produce two bits sum, one Ex-OR gate is sufficient whereas for adding three
bits two Ex-OR gates are required.
• Truth Table: K- map simplification:
Logic circuit Diagram:
To generate the even parity bit for a 3-bit data, two Ex-OR gates are required to add
the 3-bits and their sum will be the parity bit.
Parity Checker
• It is a logic circuit that checks for possible errors in the transmission.

• This circuit can be an even parity checker or odd parity checker depending on the
type of parity generated at the transmission end.

• When this circuit is used as even parity checker, the number of input bits must
always be even.

• When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output
goes high.

• If this logic circuit is used as an odd parity checker, the number of input bits
should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum
even’ output goes high.
Even Parity Checker
• Consider that three input message along with even parity bit is generated at the
transmitting end. These 4 bits are applied as input to the parity checker circuit which
checks the possibility of error on the data.

• Since the data is transmitted with even parity, four bits received at circuit must have an
even number of 1s.

• If any error occurs, the received message consists of odd number of 1s. The output of the
parity checker is denoted by PEC (parity error check).

• The truth table for the even parity checker is shown in the next slide. In which PEC = 1 if
the error occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no
error occurs, i.e., if the 4-bit message has even number of 1s.
• Truth Table:
• K- map Simplification:
• Logic Circuit Diagram:

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