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Tutorial10 26042023

This document contains 15 multiple choice questions about analog to digital converters and digital to analog converters. It is a tutorial from BITS Pilani, K K Birla Goa Campus. The questions cover topics like offset error, resolution, monotonicity, resistance ladder DACs, conversion time, comparator usage, and integral nonlinearity and differential nonlinearity. For each question there is an answer provided.

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Anirudh Singh
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44 views18 pages

Tutorial10 26042023

This document contains 15 multiple choice questions about analog to digital converters and digital to analog converters. It is a tutorial from BITS Pilani, K K Birla Goa Campus. The questions cover topics like offset error, resolution, monotonicity, resistance ladder DACs, conversion time, comparator usage, and integral nonlinearity and differential nonlinearity. For each question there is an answer provided.

Uploaded by

Anirudh Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Analog Electronics

Tutorial -10
26-04-2023

BITS Pilani, K K Birla Goa Campus


Q1. A binary input 000 is fed to a 3bit DAC/ADC. The
resultant output is 101. Find the type of error?
a) Settling error
b) Gain error
c) Offset error
d) Linearity error

Ans: C

BITS Pilani, K K Birla Goa Campus


Q2: How many equal intervals are present in a 14-bit D-A converter?

Ans: A 14-bit D-A converter has 2n-1 equal interval =214-1=16384-1=16383.

BITS Pilani, K K Birla Goa Campus


Q3: Find the resolution of a 10-bit D/A converter for an input range of 10V?

Ans: Resolution (in volts) VFS /2n= 10 /210 =10/1024 =9.77mv.

BITS Pilani, K K Birla Goa Campus


Q4: A monotonic DAC is one whose analog output increases for
a) Decreases in digital input
b) An increases in analog input
c) An increases in digital input
d) Decreases in analog input

Ans: C

BITS Pilani, K K Birla Goa Campus


Q5: Which of the following resistance networks can be used as 3 bit
R-2R ladder DAC? Assume Vo corresponds to LSB.

Ans: iii
BITS Pilani, K K Birla Goa Campus
Q6: Match the following ADC’s with their Maximum conversion time for
8 bit digital output.

Ans: A-2, B-5,C-1

BITS Pilani, K K Birla Goa Campus


Q7: A 12 bit ADC is operating with a 1 µsec clock period and the
total conversion time is seen to be 14 µsec. the ADC must be of
the
a. Flash type
b. Counting type
c. Integrating type
d. Successive Approximation type
Answer: D

BITS Pilani, K K Birla Goa Campus


Q8: The advantage of using a dual slope ADC in a digital voltmeter is
that
a. Its conversion time is small
b. Its accuracy is high
c. It gives output in BCD format
d. It does not require a comparator
Answer: B

BITS Pilani, K K Birla Goa Campus


Q9: The current I flowing through resistance ‘r’ in the circuit shown is

a. -V/12R
b. V/12R
c. V/6R
d. V/3R
Answer: B
BITS Pilani, K K Birla Goa Campus
Q10: The resolution of a 4 bit counting ADC is 0.5 volts. For an analog input of 6.6 volts,
the digital output of the ADC will be
a. 1011
b. 1101
c. 1100
d. 1110
Answer: D

BITS Pilani, K K Birla Goa Campus


Q11: The number of comparators in a 4 bit flash ADC is
a. 4
b. 5
c. 15
d. 16
Answer: C

BITS Pilani, K K Birla Goa Campus


Q12: An 8 bit successive approximation analog to digital converter has full
scale reading of 2.55 volts and its conversion time for an anlog input of 1
volt is 20 µs. The conversion time for a 2 volts input is
a. 10 µs
b. 20 µs
c. 40 µs
d. 50 µs
Answer: B

BITS Pilani, K K Birla Goa Campus


Q13: For the 4 bit DAC shown, the output voltage Vo is

a. 10 volts
b. 5 volts
c. 4 volts
d. 8 volts
Answer: B

BITS Pilani, K K Birla Goa Campus


Q14: In the Digital to analog converter circuit shown in the figure below,
VR = 10 volts and R = 10 kΩ.

1. The current i is
a. 31.25 µA
b. 62.5 µA
c. 125 µA
d. 250 µA
Answer: B

BITS Pilani, K K Birla Goa Campus


The voltage Vo is
a. – 0.781 volts
b. – 1.562 volts
c. – 3.125 volts
d. – 6.250 volts
Answer: C

BITS Pilani, K K Birla Goa Campus


Q15. Find the INL and DNL of the 3-bit DAC shown in Fig.

BITS Pilani, K K Birla Goa Campus


Ans:
000 001 010 011 100 101 110 111
INL 0 0 -1/2 ½ -1 ½ -1/2 0
DNL 0 0 -1/2 1 -3/2 3/2 -1 1/2

Maximum INL = 1LSB


Maximum DNL = 1.5 LSB

BITS Pilani, K K Birla Goa Campus

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