Application Information

STR-W6200D Series PWM Off-Line Switching Regulator ICs

General Description
The STR-W6200D series are power ICs for switching
power supplies, incorporating a power MOSFET and a
current mode PWM controller IC in one package. Includ-

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ing a startup circuit and a standby function in the controller,
the product achieves low power consumption, low standby

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power, and high cost-effectiveness in power supply systems,
while reducing external components.

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Features and Benefits

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▪ TO-220 fully-molded package with 6 pins
▪ Current mode PWM control
▪ PWM and frequency modulation functions: reduces EMI
noise, simplifies EMI filters, and cuts cost by external part
reduction
▪ Built-in Slope Compensation circuit: avoids subharmonic
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Figure 1. STR-W6200 series packages are fully molded TO-220
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oscillation package types. Pin 2 is deleted for greater isolation. A flange is
▪ Automatic Standby Mode function (Input Power < 40 provided for heatsink mounting.
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mW at no load)
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▫ Normal operation: PWM mode

▫ Light load operation: Standby mode (burst oscillation) Applications
▪ Built-in Audible Noise Suppression function during
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Switching power supplies for electronic devices such as:

Standby mode • White goods
▪ Built-in startup circuit: reduces power consumption in • Consumer electronics
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standby operation, and eliminates external components • Office automation

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▪ Bias-Assist function: improves startup operation, • Industrial equipment

suppresses VCC pin voltage drop in operation, and allows • Communications equipment
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use of smaller VCC capacitor

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▪ Built-in Leading Edge Blanking function

▪ Protection Functions:
The product lineup for the STR-W6200D series provides
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▫ Overcurrent Protection function (OCP); pulse-by-pulse,

the following options:
built-in compensation circuit to minimize OCP point
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POUT*
variation on AC input voltage MOSFET RDS(on)
fOSC (W)
▫ Overload Protection function (OLP); auto restart, built-in Part Number VDSS(min) (max)
(kHz)
N

(V) (Ω) 85 to
timer, reduces heat during overload condition, and few 230 VAC
265 VAC
external components required STR-W6251D 3.95 45 30
▫ External Latch Protection function (ELP): latched STR-W6252D 67 650 2.8 60 40
shutdown by external signal
STR-W6253D 1.9 90 60
▫ Overvoltage Protection function (OVP): latched
shutdown *The listed output power is based on the thermal ratings, and the
peak output power can be 120% to 140% of the value stated here.
▫ Thermal Shutdown function (TSD); latched shutdown At low output voltage and short duty cycle, the output power may
be less than the value stated here.

STRW6200D-AN Rev.2.0
SANKEN ELECTRIC CO., LTD.
http://www.sanken-ele.co.jp/en/
 VCC STARTUP D/ST
7.1 V
UVLO REG VREG
OVP RESET
Istartup
28.5 V =1.6 mA
15.5 V / 8.9 V R
ELP SQ
7.1 V

TSD

ns
RQ
Dmax 75%
S
PWM OSC DRV

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SQ
R

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S2 Q

D
Frequency OLP
FM /ELP Modulation CK Drain Peak Current
S1 Compensation
tDLY =

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tFM ×16 R OCP

7.8 V

FB
160 μA
rN Feedback
Control LEB S/OCP
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Slope
Compensation GND
d
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Pin List Table

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Number Name Function

1 D/ST MOSFET drain and input of the startup current
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2 – (Pin removed)
3 S/OCP MOSFET source and input of Overcurrent Protection (OCP) signal
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Power supply voltage input for Control Part and input of Overvoltage
4 VCC
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Protection (OVP) signal

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5 GND Ground
6 FB Input for constant voltage control signal
R

Capacitor connection pin for frequency modulation and input of

7 FM/ELP
External Latch Protection
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Table of Contents
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General Description 1 Constant Output Voltage Control 10

Fault Latch 11
Product Lineup 1 External Latch Protection Function (ELP) 11
Functional Block Diagram 2 Overload Protection Function (OLP) 12
Overvoltage Protection Function (OVP) 12
Package Diagram 3
Overcurrent Protection Function (OCP) 12
Electrical Characteristics 4 Thermal Shutdown Function (TSD) 13
Typical Application Circuit 6 Design Notes 14
Functional Description 7 Peripheral Components 14
Startup Operation 7 Phase Compensation 14
Frequency Modulation Function 9 Capacitance of External Capacitor at FM/ELP Pin14
Automatic Standby Mode Function 10 Secondary Diode EMI Measure 15
PCB Trace Layout and Component Placement 15

STRW6200D-AN Rev.2.0 2
SANKEN ELECTRIC CO., LTD.
Package Diagram
TO-220F-6L package
Leadform: 2003

10.0 ±0.2
4.2 ±0.2
Gate Burr 2.8 ±0.2

0.5

4.0 ±2

ns
7.9 ±0.2

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16.9 ±0.3

Ø3.2 ±0.2

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D
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2.6 ±0.1
(At base of pin)

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2.8

5.0 ±0.5

6X0.74 ±0.15

10.4 ±0.5
+0.2 (2
6X0.65 –0.1 End of bend R1
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)
d (5.4)

View A View B
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1.27 ±0.15 +0.2

6×1.27 ±0.15 = 7.62 ±0.15 0.45 –0.1
(At base of pin)
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5.08 ±0.6
3 5 7

(At tip of pin)

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1 2 4 6
m

0.5 0.5 0.5 0.5

o
ec

View A View B
Bottom View

Unit: mm
R

Dashed line at Gate Burr indicates

protrusion of 0.3 mm (max)
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STR
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W62xx
Part Number
YMDDR
Lot Number
Y is the last digit of the year (0 to 9)
M is the month (1 to 9, O, N, or D)
DD is a period of day (01 to 31)
R is the Sanken Registration Number
Pin treatment Pb-free. Device composition
compliant with the RoHS directive.

STRW6200D-AN Rev.2.0 3
SANKEN ELECTRIC CO., LTD.
Electrical Characteristics
• This section provides separate sets of electrical characteristic
data for each product.
• The polarity value for current specifies a sink as "+ ," and a
source as “−,” referencing the IC.

Absolute Maximum Ratings Unless specifically noted, valid at TA = 25°C

ns
Characteristic Symbol Note Pin Rating Unit
STR-W6251D 2.6 A

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Drain Peak Current IDPEAK STR-W6252D Single Pulse 1-3 3.2 A

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STR-W6253D 10 A
STR-W6251D 2.6 A

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Maximum Switching Current IDMAX STR-W6252D TA = –20°C to 125°C 1-3 3.2 A
STR-W6253D 10 A

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STR-W6251D ILPEAK = 2 A Single Pulse, 47 mJ
Avalanche Energy EAS STR-W6252D ILPEAK = 2.3 A VDD = 99 V, 1-3 62 mJ
STR-W6253D ILPEAK = 2.7 A L = 20 mH
S/OCP Pin Voltage
FM/ELP Pin Voltage
VOCP
VFM
rN 3-5
7-5
86
–6 to 6
–0.3 to 12
mJ
V
V
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FM/ELP Pin Sink Current IFM 7-5 3 mA
FB Pin Voltage VFB FB pin is open 6-5 –0.3 to 9 V
Controller Part Input Voltage VCC 4-5 0 to 32 V
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STR-W6251D 25 W
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STR-W6252D With infinite heatsink 26 W

MOSFET Power Dissipation PD1 1-3
STR-W6253D 27.5 W
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Without heatsink 1.3 W

Controller Part Power Dissipation PD2 4-5 0.8 W
m

Recommended operating temperature is

Internal Frame Temperature in Operation TF – –20 to 115 °C
TF = 105°C (max)
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Operating Ambient Temperature Top – –20 to 115 °C

Storage Temperature Tstg – –40 to 125 °C
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Channel Temperature Tch – 150 °C

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R
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STRW6200D-AN Rev.2.0 4
SANKEN ELECTRIC CO., LTD.
Electrical Characteristics of Control Part Unless specifically noted, TA is 25°C, VCC = 18 V
Characteristic Symbol Pin Min. Typ. Max Unit
Power Supply Startup Operation
Operation Start Voltage VCC(ON) 4-5 13.9 15.5 17.1 V
Operation Stop Voltage VCC(OFF) 4-5 8.0 8.9 9.8 V
Circuit Current in Operation ICC(ON) 4-5 – 1.4 2.8 mA
Circuit Current in Non-Oscillation ICC(STOP) 4-5 – 0.8 1.3 mA
Circuit Current in Non-Operation ICC(OFF) 4-5 – 5 20 μA
Startup Current ISTARTUP 4-5 –0.9 –1.6 –2.3 mA

ns
Bias Assist Voltage VCC(BIAS) 4-5 13.6 15.2 16.8 V
Normal Operation

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FM/ELP Pin High Threshold Voltage VFM(H) 7-5 4.0 4.5 5.0 V

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FM/ELP Pin Low Threshold Voltage VFM(L) 7-5 2.4 2.8 3.2 V

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FM/ELP Pin Voltage Difference ∆VFM 7-5 1.4 1.7 1.8 V
FM/ELP Pin Source Current IFM(SRC) 7-5 –17.4 –13 –8.6 μA

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FM/ELP Pin Sink Current IFM(SNK) 7-5 8.6 13 17.4 μA
Average Switching Frequency fOSC(AVG) 1-5 60 67 74 kHz
Frequency Modulation Deviation
Maximum Duty Cycle (On-duty)
FB Pin Maximum Feedback Current
∆f
DMAX
IFB(MAX)
1-5
1-5
6-5
rN4.8
71
–220
6.9
75
–160
9
79
–100
kHz
%
μA
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Standby Operation Startup Voltage VSTBY 6-5 0.99 1.10 1.21 V
Slope Compensation Startup Duty Cycle DSLP 6-5 – 27 – %
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Slope Compensation Rate SLP 6-5 –22 –17 –12 mV/μs

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Protection Operation
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OCP Threshold Voltage at Zero Duty Cycle

VOCP1 3-5 0.71 0.78 0.86 V
(0% On-duty)
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Drain Peak Current Compensation Coefficient DPC – 1.5 1.9 2.3 mV/D%
OCP Threshold Voltage After Compensation VOCP2 3-5 0.82 0.93 1.04 V
m

LEB Time tBW 1-5 280 400 520 ns

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OLP Delay Time* tDLY 1-5 – 200 – ms

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Circuit Current in OLP-Operation ICC(OLP) 4-5 – 410 700 μA

OVP Threshold Voltage VCC(OVP) 4-5 27 28.5 30 V
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Latch Circuit Holding Current ICC(La.H) 4-5 – 140 220 μA

Latch Circuit Release Voltage VCC(La.OFF) 4-5 6.4 7.1 7.8 V
ot

ELP Threshold Voltage VELP 7-5 6.4 7.1 7.8 V

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Sink Current in ELP Operation IELP 7-5 – 55 100 μA

Thermal Shutdown Activating Temperature TJ(TSD) – 135 – – °C
*Reference value of 47 nF capacitor between FM/ELP and GND Pins.

STRW6200D-AN Rev.2.0 5
SANKEN ELECTRIC CO., LTD.
 Electrical Characteristics of MOSFET Unless specifically noted, TA is 25°C
Characteristic Symbol Note Pin Min. Typ. Max. Unit
Drain-to-Source Breakdown Voltage VDSS 1-3 650 – – V
Drain Leakage Current IDSS 1-3 – – 300 μA
STR-W6251D – – 3.95 Ω
On-Resistance RDS(ON) STR-W6252D 1-3 – – 2.8 Ω
STR-W6253D – – 1.9 Ω
Switching Time tr 1-3 – – 400 ns
STR-W6251D Between – – 2.23 °C/W
STR-W6252D channel
Thermal Resistance Rθch-F – – – 2.04 °C/W
and internal

ns
STR-W6253D frame – – 1.75 °C/W

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Typical Application Circuit

D
Clamp Snubber Circuit D3 L2 V OUT

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T1
VAC
C10 R9 PC1
R3 R6
P
C1
D4
rN S C5
R4
C6 R5
R7
C7
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U1 U2
R8

GND
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D1 R2
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STR-W6200D C2
D
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FM/ELP
S/OCP
D/ST

GND
VCC

FB
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1 3 4 5 6 7

External Latch Circuit

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CV (Optional)
C4
ROCP
C3 C8
PC1
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Damper Snubber
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The following design feature should be observed: In applications having a power supply specified such that VDS
has large transient surge voltages, a clamp snubber circuit of a capacitor-resistor-diode (CRD) combination should
be added on the primary winding, P, or a damper snubber circuit of a capacitor (C) or a resistor-capacitor (CR)
N

combination should be added between the D/ST pins and the S/OCP pin.

STRW6200D-AN Rev.2.0 6
SANKEN ELECTRIC CO., LTD.
Functional Description
With regard to current direction, "+" indicates sink current Figure 3 shows the relationship of VCC and ICC. When the VCC
(toward the IC) and "–" indicates source current (from the IC). pin voltage increases to VCC(ON), the control circuit starts opera-
tion and the circuit current, ICC , increases. In operation, when
Startup Operation the VCC pin voltage decreases to VCC(OFF) (8.9 V typical), the
Figure 2 shows the VCC pin peripheral circuit. The built-in control circuit stops operation, by the UVLO (Undervoltage
startup circuit is connected to the D/ST pin, and it generates a Lockout) circuit, and reverts to the state before startup.
constant current, ISTARTUP (–1.6 mA typical) to charge capaci-
The rectified voltage from the auxiliary winding, D (figure 2),
tor C2 connected to the VCC pin. During this process, when the
becomes a power source to the control circuit after the operation
VCC pin voltage reaches VCC(ON) (15.5 V typical), the control
start.
circuit starts operation. After that, the startup circuit stops auto-
matically, in order to eliminate its own power consumption. The VCC pin voltage should become as follows within the

ns
specification of input voltage range and the output load range
The startup time is determined by the C2 capacitance, and a
of power supply, taking account of the winding turns of the D
value of 10 to 47 μF is generally recommended. The approxi-

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winding; the target voltage of the VCC pin voltage is about
mate startup time, tSTART , can be calculated as follows:
15 to 20 V:

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VCC(ON) (V) – VCC(INT) (V)
tSTARTUP (s) = C2 (µF) × (1) VCC(OFF) = 9.8 V (max) < VCC

D
|ISTARTUP |(mA) (2)
< VCC(OVP) = 27.0 V (min)
where VCC(INT) is the initial voltage on the VCC pin.

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Figure 4 shows the VCC pin voltage behavior during the startup
period. When the VCC pin voltage reaches VCC(ON) , the control
circuit starts operation, the circuit current, ICC , increases, and

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thus the VCC pin voltage begins dropping. At the same time,
the auxiliary winding voltage, VD , increases in proportion to the
output voltage rise. Thus, the VCC pin voltage is set by the bal-
C1
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P
ance between dropping by the increase of ICC and rising by the
increase of the auxiliary winding voltage, VD .
d

Just at the turning-off of the power MOSFET, a surge voltage

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1
occurs at the output winding. If the feedback control is activated
D/ST D1 R2 by the surge voltage on light load condition at startup, and the
en

VCC 4 VCC pin voltage decreases to VCC(OFF) , a startup failure can

STR-W6200D
C2 D occur, because the output power is restricted and the output volt-
m

GND 5 age decreases.

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In order to prevent this, when the VCC pin voltage falls to

Figure 2. VCC pin peripheral circuit
the Bias Assist Voltage, VCC(BIAS) (15.2 V typical), the Bias
o
ec
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VCC (V) Bias Assist Period

ICC
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Target Operation Voltage

1.4 mA
(Typ.) 15.5 (typ)
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15.2 (typ) Bias Assist Voltage

Stop Star t 8.9 (typ) Operation Stop Voltage

Startup Failure Event

5 μA
(Typ.)
8. 9 V VCC
15. 5 V VIN(AC) Start of normal time
(Typ.) operation
13.8 V (Typ.) turn on
(Typ.)

Figure 3. VCC versus ICC Figure 4. VCC during startup period

STRW6200D-AN Rev.2.0 7
SANKEN ELECTRIC CO., LTD.
Assist function is activated. While this function is operating, In actual power supply circuits, there are cases in which the
the decrease of the VCC pin voltage is suppressed by provid- VCC pin voltage fluctuates in proportion to the output of the
ing the startup current, ISTARTUP , from the startup circuit. By SMPS (see figure 5), and the Overvoltage Protection (OVP)
this function, the use of a small value C2 capacitor is allowed, on the VCC pin may be activated. This happens because C2 is
resulting in shortened startup time. Also, because the increase charged to a peak voltage on the auxiliary winding D, which is
caused by the transient surge voltage coupled from the primary
of VCC pin voltage becomes faster when the output runs with
winding when the power MOSFET turns off.
excess voltage, the response time of the OVP function can also
be shortened. For alleviating C2 peak charging, it is effective to add some
value R2, of several tenths of ohms to several ohms, in series

ns
After the IC starts switching operation, the Bias Assist function with D1 (see figure 6). The optimal value of R2 should be deter-
is available until the FM/ELP pin voltage reaches the FM/ELP mined using a transformer matching what will be used in the

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pin High Threshold Voltage, VFM(H) (4.5 V typical), and at this actual application, because the variation of the auxiliary winding
voltage, this function stops. voltage is affected by the transformer structural design.

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D
Bobbin
Barrier

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VCC
P1 S1 P2 S2 D

With
out R
2 rN Barrier
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With R2
d

P1 ,P2 Primary winding

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S1 Secondary output winding

controlled to constant voltage
IOUT S2 Secondary output winding
en

D Auxiliary winding for VCC

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Figure 5. VCC versus IOUT with and without resistor R2 Figure 7. Winding structural example (a)
o m
ec

Bobbin
R

D1 R2 Barrier

4
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VCC Added D P1 S1 D S2 S1 P2
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STR-W6200D
C2 Barrier
GND
5
P1 ,P2 Primary winding
S1 Secondary output winding
controlled to constant voltage
S2 Secondary output winding
D Auxiliary winding for VCC

Figure 6. VCC pin peripheral circuit with R2 Figure 8. Winding structural example (b)

STRW6200D-AN Rev.2.0 8
SANKEN ELECTRIC CO., LTD.
The variation of VCC pin voltage becomes worse if: • Winding structural example (b): Placing the auxiliary wind-
ing D within the secondary winding S1 in order to improve the
• The coupling between the primary and secondary windings of
coupling of those windings.
the transformer gets worse and the surge voltage increases (low
output voltage, large current load specification, for example). The output winding S1 is a stabilized output winding, con-
trolled to constant voltage.
• The coupling of the auxiliary winding, D, and the secondary
side stabilization output winding (winding of the output line
Frequency Modulation Function
which is controlling constant voltage) gets worse and it is subject
The frequency modulation is superposed on the PWM frequency,
to surge voltage.
helping to reduce the conductive EMI noise, and simplify noise

ns
In order to reduce the influence of surge voltages on the VCC filtering on input lines.
pin, alternative structures of the auxiliary winding, D, can be

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Figure 9 shows the VDS and ID waveforms at an average fre-
used; as examples of transformer structural designs see figures 7
quency of 67 kHz and an internally-fixed fluctuation width, Δf,
and 8.

es
of 6.9 kHz typical. Figure 10 shows the relationship between the
• Winding structural example (a): Separating the auxiliary wind- FM/ELP pin voltage and the frequency modulation period.

D
ing D from the primary side windings P1 and P2.
The C3 connected to the FM/ELP pin is charged by the con-

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The primary side winding is divided into two windings, P1 and stant source current, IFM(SRC) (–13 μA typical), until its volt-
P2. age increases to about 4.5 V. After that, it is discharged by the

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d
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Frequency modulation signal

4.5 V
FM/ELP (typ)
Voltage
en

∆f = 6.9 kHz 2.8 V

VDS (typ)
m

Drain
Current, ID
m

ID f(max) ≈ 70.45 kHz

f(min) ≈ 63.55 kHz
o

tFM = (2 × C3 × 1.7) /13 μA (s)

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R

Figure 9. VDS and ID waveforms in frequency modulation Figure 10. FM/ELP pin voltage and frequency modulation period
ot
N

Output Current, IOUT Burst Oscillation Mode

Less than a few kilohertz

Drain Current, ID

Normal Load Standby Load Normal Load

Figure 11. Automatic-Standby mode operation

STRW6200D-AN Rev.2.0 9
SANKEN ELECTRIC CO., LTD.
constant sink current, IFM(SNK) (13 μA typical), until its voltage Automatic Standby Mode Function
decreases to about 2.8 V, and then the mode is reverted to the The Automatic Standby mode is activated automatically when
constant charge by IFM(SRC). The repetition of this makes the fre- the drain current, ID , reduces under light load conditions, at
quency modulation signal a triangle waveform on the FM/ELP which ID is less than 15% of the maximum drain current (it is in
pin. By inputting this signal to the PWM oscillation circuit, the the Overcurrent Protection state).
frequency modulation occurs.
The operation mode becomes burst oscillation, as shown in fig-
The frequency modulation period, tFM , can be adjusted by the ure 11. Burst oscillation reduces switching losses and improves
value of C3. The tFM can be calculated as follows. power supply efficiency because of periodic non-switching

ns
intervals. Generally, to improve efficiency under light load con-
tFM (s) = 2 × C3 × ∆VFM ditions, the frequency of the burst oscillation becomes just a few
(3)

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13 (μA)
kilohertz. When the burst oscillation frequency is in the human
where ∆VFM is 1.7 V typical.

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audible range (20 Hz to 20 kHz), audible noise may occur from
In general, a C3 value in the range of 0.01 to 0.047 μF is recom- the transformer.

D
mended, and should be determined based on actual operation in
This IC keeps the peak drain current low during burst oscillation
the application.
mode, and suppresses the audible noise of the transformer.

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Constant Output Voltage Control

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The constant output voltage control function uses current-mode
control (peak current mode), which enhances response speed
and provides stable operation. This IC compares the voltage,
fo
STR-W6200D VROCP , of the current detection resistor with the target voltage,
VSC , by the internal FB comparator, and controls the peak value
d

of VROCP so that it gets close to VSC. VSC is internally generated

by inputting the FB pin voltage to the feedback control (see the
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S/OCP GND FB Functional Block diagram) and adding the slope compensation
3 5 6 value (refer to figures 12 and 13).
en

PC1
VROCP RROCP IFB • Light load conditions When load conditions become lighter,
m

C4 the output voltage, VOUT, rises, and the feedback current from
the error amplifier on the secondary side also increases. The
m

feedback current is sunk at the FB pin, transferred through a

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Figure 12. FB pin peripheral circuit

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Target voltage without Slope Compensation

R

Target voltage including

Slope Compensation
VSC
–
ot

VROCP
N

+
S/OCP signal
FB Comparator voltage across ROCP

ton1
Drain ton2
Current,
ID
T T T

Figure 13. Drain current, ID, and FB comparator operation in Figure 14. Drain current, ID, waveform in subharmonic oscillation
steady operation

STRW6200D-AN Rev.2.0 10
SANKEN ELECTRIC CO., LTD.
photo-coupler, PC1, and the FB pin voltage decreases. Thus, VSC tions caused by surge voltage in turning-on the power MOSFET.
decreases, the peak value of VROCP is controlled to be low, and
the peak drain current of ID decreases. This control prevents the Fault Latch
output voltage from increasing. When the OVP, ELP, and TSD functions are activated, the latch
• Heavy load conditions When load conditions become greater, circuit is also activated, and then the IC stops switching opera-
the control circuit performs the inverse operation to that tion, in latch mode.
described above. Thus, VSC increases and the peak drain current After that, the VCC pin voltage decreases to VCC(OFF) (8.9 V
of ID increases. This control prevents the output voltage from typical), and then the startup circuit is activated. When the VCC
decreasing. pin voltage increases to VCC(ON) (15.5 V typical), the circuit

ns
In the current-mode control method, when the drain current current increases, and the VCC pin voltage decreases again. As a
waveform becomes trapezoidal in continuous operating mode, result, the VCC pin voltage fluctuates between 8.9 V typical and

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even if the peak current level set by the target voltage is con- 15.5 V typical as shown in figure 15, and it prevents the VCC

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stant, the on-time fluctuates based on the initial value of the pin voltage from increasing.
drain current. This results in the on-time fluctuating in multiples
Releasing the latched state is done by turning off the input volt-

D
of the fundamental operating frequency as shown in figure 14.
age and allowing the VCC pin voltage to drop below VCC(La.OFF)
This is called the subharmonics phenomenon.

ew
(7.1 V typical).
In order to avoid this, the IC incorporates the Slope Compensa-
tion function. Because the target voltage is added, a down-slope External Latch Protection Function (ELP)
compensation signal that reduces the peak drain current as the
on-duty gets wider relative to the FB pin signal to compensate
VSC , the subharmonics phenomenon is suppressed.
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This function forces a latched shutdown if more than the ELP
Threshold Voltage, VELP (7.1 V typical), is applied between
the FM/ELP and the GND pins. The applied voltage should
fo
Even if subharmonic oscillations occur when the IC has some be within –0.3 to 12 V (the Absolute Maximum Rating of the
excess supply being out of feedback control, such as during FM/ELP pin voltage).
d

startup and load shorted, this does not affect performance during The Typical Application Circuit shows an example, whereby a
de

normal operation. current limitation resistor and a latch trigger switch (that is, a
photocoupler), are inserted between the VCC and FM/ELP pins.
en

In the current-mode control method, the FB comparator and/or

the OCP comparator may respond to the surge voltage resulting Because the FM/ELP pin has a built-in Zener diode, the current
from the drain surge current in turning-on the power MOSFET, limitation resistor value should be such that the current going
m

and may turn off the power MOSFET irregularly. Leading Edge into the FM/ELP pin would be below the Absolute Maximum
m

Blanking, tBW (400 ns typical), is built-in to prevent malfunc- Rating of 3 mA for IFM .
o
ec
R
ot

Vcc
STR-W6200D
N

15.5 V (typ)
FM/ELP
GND

8.9 V (typ)
FB

Circuit current is small 7 5 6

Circuit current is large
PC1

C3 C4 IFB
time
Figure 15. VCC pin voltage at fault latch Figure 16. FB pin and FM/ELP pin peripheral circuit

STRW6200D-AN Rev.2.0 11
SANKEN ELECTRIC CO., LTD.
Overload Protection Function (OLP) Overvoltage Protection Function (OVP)
When the peak drain current of ID is limited by OCP operation, When the voltage between the VCC pin and the GND pin
the output voltage, VOUT , decreases and the feedback current increases to VCC(OVP) (28.5 V typical) or more, the OVP function
from the secondary photo-coupler, IFB (see figure 16), becomes is activated and stops switching operation. When the auxiliary
zero. When this state remains for the OLP Delay Time, tDLY , the winding supplies the VCC pin voltage, the OVP function is able
OLP function is activated, and the IC stops switching operation. to detect an excessive output voltage, such as when the detection
circuit for output control is open on the secondary side, because
When the VCC pin voltage decreases to VCC(OFF) , the control the VCC pin voltage is proportional to the output voltage.
circuit stops its operation by the UVLO circuit, and reverts to the
The secondary side output voltage, which initiates OVP opera-
state before startup. After that, the VCC pin voltage increases to

ns
tion, is calculated approximately as follows:
VCC(ON) because the startup circuit is activated. As a result, the
V (normal operation)
operation becomes the intermittent oscillation mode by UVLO VOUT(OVP) = OUT × 28.5 (V) (typ.) (5)

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VCC(normal operation)
as shown in figure 17, during OLP operation.

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Overcurrent Protection Function (OCP)
This operation reduces stresses on the power MOSFET and on
The OCP function detects each peak drain current level of a

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the secondary rectifier diode, furthermore, it reduces power
power MOSFET on a pulse-by-pulse basis, by monitoring the
consumption because it reduces the frequency of the intermittent
voltage across the current detection resistor ROCP between the S/

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oscillation and the ratio of the switching period, by lowering the OCP pin and the GND pin, and limits the output power accord-
circuit current to ICC(OLP) (410 μA typical) during OLP opera- ingly. When the voltage drop on both sides of ROCP increases to
tion. The approximate value of tDLY is equal to 16 times the
charge-discharge cycle of C3, connected to the FM/ELP pin (see
figure 16), and its equation is:
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the OCP threshold voltage, the power MOSFET is turned off.
ICs with PWM control usually have some detection delay time
on OCP detection. The steeper the slope of the actual drain cur-
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tDLY (s) = tFM × 16 rent at a high AC input voltage is, the later the actual detection
2 × C3 (µF) × 1.7 (V) point is, compared to the internal OCP threshold voltage, VOCP.
d

(4)
= × 16 Thus, the actual OCP point limiting the output current usually
13 (µA) (typ)
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has some variation depending on the AC input voltage, as shown

where tFM is determined by equation 3. in figure 18.
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The Delay Time, tDLY , should be longer than the period from a The IC incorporates a built-in AC Input Compensation function
that superposes a signal with a defined slope into the detection
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point where the VCC pin voltage increases to VCC(ON) , to other

where the output voltage reaches its target value, in order to signal from the S/OCP pin as shown in figures 19 and 20. When
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prevent startup failure caused by OLP operation. the AC input voltage is lower and the duty cycle is higher, the
OCP compensation level of this function is increased. Therefore,
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In general, a C3 value is recommended to be about the OCP point in low AC input voltage is increased to minimize
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0.01 to 0.047 μF, and the optimal value should be determined the difference of OCP points between low AC input voltage and
based on actual operation in the application. high AC input voltage, without additional external components.
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Switching stopped
interval
VOUT Variance resulting from
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Swtiching
turns off
propagation delay
VCC pin voltage

VCC(OFF)= 8.9 V typical

t
npu
ACi
t
Low npu
ACi
h
Hig
FM/ELP pin voltage

Delay Time, tDLY

Drain Current, ID
IOUT

Figure 17. Waveforms during OLP operation Figure 18. Output current at OCP without input compensation

STRW6200D-AN Rev.2.0 12
SANKEN ELECTRIC CO., LTD.
Because the compensation signal level is designed to depend DPC is the OCP compensation coefficient (mV/D%),
upon the duty cycle, the OCP threshold voltage after compensa- 1.9 mV/D% typical, and
tion, VOCP(D%) , is calculated as follows: D is the duty cycle.
Assuming an AC input voltage of 85 V, if the transformer is
VOCP(D%) (V) = VOCP1 (V) + DPC (mV/duty%) × D (%) (6)
designed so the duty cycle, D, at a maximum load is 50%, then,
where according to equation 6, VOCP(50%) = 0.875 V typical.

VOCP1 is the OCP threshold voltage at zero duty cycle (V), Thermal Shutdown Function (TSD)
0.78Vtypical,

ns
When the controller chip temperature increases to 135°C (min)
or more, the IC stops switching operation, in latch mode.

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1.05

1.00 Max.
Typ.
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0. 90
0. 85
≈ 0.875
≈ 0.923
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Min. ≈ 0.809
0.95 0. 80
VOCP2(D%) Typical (V)
VOCP(D%) (V)

0. 75
0.90
d

0. 70
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0.85
0. 60
0.80
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0.75 0. 50 265 VAC 85 VAC

(as an example) (as an example)
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0.70 0
0 10 20 30 40 50 60 70 80 0 15. 5 50 75
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Duty Cycle, D (%) Duty Cycle, D (%)

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Figure 19. Duty Cycle versus OCP Threshold Voltage After Figure 20. Duty Cycle versus typical value of OCP Threshold Voltage
Compensation
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After Compensation relative to input voltage, for examaple

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STRW6200D-AN Rev.2.0 13
SANKEN ELECTRIC CO., LTD.
Design Notes

Peripheral Components • Current detection resistor, ROCP

Take care to use the proper rating and proper type of compo- ▫ A high frequency switching current flows to ROCP , and may
nents. cause poor operation if a high inductance resistor is used.
▫ Choose a low inductance and high surge tolerant type.
• Input and output electrolytic capacitors
▫ Apply proper design margin to accommodate ripple current, Phase Compensation
voltage, and temperature rise. A typical phase compensation circuit with a secondary shunt
regulator (U2) is shown in figure 21. The value for C6 is recom-
▫ Use of high ripple current and low impedance types, designed

ns
mended to be about 0.047 to 0.47 μF, and should be selected
for switch-mode power supplies, is recommended, depending
based on actual operation in the application.
on their purposes.

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• Transformer Place C4 between the FB pin and the GND pin, as shown in

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▫ Apply proper design margin to core temperature rise by core figure 22, to perform high frequency noise reduction and phase
loss and copper loss. compensation. The value for C4 is recommended to be about

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2200 pF to 0.01 μF, and should be selected based on actual
▫ Because the switching circuits contain high frequency
operation in the application.
currents, the skin effect may become a consideration.

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▫ In consideration of the skin effect, choose a suitable wire Capacitance of External Capacitor at FM/ELP Pin
gauge in consideration of the rms current and a current The capacitor C3 at the FM/ELP pin determines the frequency
density of about 3 to 4 A/mm2.
▫ If measures to further reduce temperature are still necessary,
use paralleled wires or litz wires to increase the total surface
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of frequency modulation, fFM , and the OLP delay time tDLY . Fig-
ure 23 shows the relationship between them and the C3 value.
A C3 value of 0.01 to 0.047 μF is recommended, and should be
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area of the wiring. selected based on actual operation in the application.
d
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D3 L2
T1 OUTPUT
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R3 PC1 Frequency of Frequency Modulation versus C3 Value

R6
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10.00
R4 R7
C7
S C5
C6
R5
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1.00
fFM (kHz)
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U2 R8
0..10
R

GND

0.01
Figure 21. Peripheral circuit around secondary shunt regulator (U2)
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0.001 0.01 0.1

C3 (μF)
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D1 T1
R2 OLP Delay Time versus C3 Value
1000

STR-W6200D
C2 D
100
FM/ELP

tDLY (ms)
S/OCP
D/ST

GND
VCC

FB

10
1 3 4 5 6 7

1
R1 C4 0.001 0.01 0.1
C3 (μF)
C3
PC1

Figure 22. FB pin peripheral circuit Figure 23. The relationship between tFM, tDLY , and C3 (calculated values)

STRW6200D-AN Rev.2.0 14
SANKEN ELECTRIC CO., LTD.
Secondary Diode EMI Measure nent layouts should be done to comply with all safety guidelines.
A ceramic capacitor, CDI , parallel to the secondary rectifier as Furthermore, because the incorporated power MOSFET has a
shown in figure 24, may become necessary in some cases to positive thermal coefficient of RDS(ON) , consider it when prepar-
reduce EMI noise reduction. If ringing occurs on the drain cur- ing a thermal design.
rent, it is recommended to connect a damper resistor, RDI , in
Figure 27 shows a circuit layout design example for the IC
series with CDI , as shown in figure 25, in order to reduce ringing
peripheral circuit and secondary smoothing circuit.
waveforms, and to stabilize switching operation. Note: The val-
ues chosen for RDI and CDI should take those temperature rises • S/OCP Trace Layout: S/OCP pin to ROCP to C1 to T1 (wind-
into consideration, based on actual operation in the application. ing P) to D/ST pin. This is the main trace containing switching

ns
currents, and thus it should be as wide and short as possible.
PCB Trace Layout and Component Placement If C1 and the IC are distant from each other, an electrolytic

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PCB circuit trace design and component layout significantly capacitor or film capacitor (about 0.1 μF and with proper voltage
affect operation, EMI noise, and power dissipation. Therefore, rating) near the IC or the transformer is recommended to reduce

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pay extra attention to these designs. In general, where high fre- impedance of the high frequency current loop.
quency current traces form a loop, as shown in figure 26, wide,

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• GND Trace Layout: GND pin to C2 (negative pin) to T1
short traces, and small circuit loops are important to reduce line
(winding D) to R2 to D1 to C2 (positive pin) to VCC pin. This
impedance. In addition, earth ground traces affect radiated EMI

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trace also must be as wide and short as possible. If C2 and the IC
noise, and the same measures should be taken into account.
are distant from each other, placing a capacitor (approximately
Switch-mode power supplies consist of current traces with high 0.1 to 1.0 μF film capacitor) close to the VCC pin and the GND
frequency and high voltage, and thus trace design and compo-
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pin is recommended.

CDI
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T1
d

D3
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ID
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P C5
S
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D1 R2
C2
D
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Figure 24. Rectifier measure example

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R

RDI CDI
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T1
N

D3

ID
Figure 26. High-frequency current loops (hatched areas)
P C5
S

D1 R2
C2
D

Figure 25. Damper resistor example

STRW6200D-AN Rev.2.0 15
SANKEN ELECTRIC CO., LTD.
• ROCP Trace Layout: ROCP should be placed as close as possible
to the S/OCP pin. The connection between the power ground
of the main trace and the control circuit ground should be at a
single point ground (A in figure 27) to remove common imped-
ance, and to avoid interference from switching currents to the
control circuit.
• Secondary Smoothing Circuit Trace Layout: T1 (winding S)

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to D3 to C5. This trace should be as wide and short as possible.
If the loop distance is lengthy, leakage inductance resulting from

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the long loop may increase surge voltage at turning off the incor-

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porated power MOSFET. Proper secondary trace layout helps to
increase margin against the power MOSFET breakdown voltage,

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and reduces stress on the clamp snubber circuit and losses in it.

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D3
fo
C10 R9
P
d

D4
C1 C5
S
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D1 R2
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U1
C2
D
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STR-W6200D
FM/ELP
S/OCP
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D/ST

GND
VCC

FB
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1 3 4 5 6 7 Main power circuit trace

GND trace for the IC
R

CV
C4
ROCP
C3
PC1
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A
N

C8

Figure 27. Peripheral circuit example around the IC

STRW6200D-AN Rev.2.0 16
SANKEN ELECTRIC CO., LTD.
 ns
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• The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the
latest revision of the document before use.

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• Application and operation examples described in this document are quoted for the sole purpose of reference for the use of the prod-
ucts herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights or

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any other rights of Sanken or any third party which may result from its use.
• Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semicon-
ductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures
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including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device
failure or malfunction.
d

• Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equip-
de

ment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.).
When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and
en

its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever
long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales
m

representative to discuss, prior to the use of the products herein.

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The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required
(aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited.
o

• In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the
ec

degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the
load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general,
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derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such
as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses,
ot

instantaneous values, maximum values and minimum values must be taken into consideration.
N

In addition, it should be noted that since power devices or IC's including power devices have large self-heating value, the degree of
derating of junction temperature affects the reliability significantly.
• When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically
or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance
and proceed therewith at your own responsibility.
• Anti radioactive ray design is not considered for the products listed herein.
• Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken's distribu-
tion network.
• The contents in this document must not be transcribed or copied without Sanken's written consent.

STRW6200D-AN Rev.2.0 17
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