NAME : SYED MOHD MUSTAFA

ROLL NO : 21BCS003

Q) Write in detail about RISC-V architecture.

RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on
established reduced instruction set computer (RISC) principles. Unlike most other ISA designs,
RISC-V is provided under royalty-free open-source licenses. A number of companies are offering or
have announced RISC-V hardware, open source operating systems with RISC-V support are
available, and the instruction set is supported in several popular software toolchains.

As a RISC architecture, the RISC-V ISA is a load–store architecture. Its floating-point instructions
use IEEE 754 floating-point. Notable features of the RISC-V ISA include instruction bit field
locations chosen to simplify the use of multiplexers in a CPU, a design that is architecturally
neutral, and most-significant bits of immediate values placed at a fixed location to speed sign
extension.

ISA base and extensions

RISC-V has a modular design, consisting of alternative base parts, with added optional extensions.
The ISA base and its extensions are developed in a collective effort between industry, the research
community and educational institutions. The base specifies instructions (and their encoding),
control flow, registers (and their sizes), memory and addressing, logic (i.e., integer) manipulation,
and ancillaries. The base alone can implement a simplified general-purpose computer, with full
software support, including a general-purpose compiler.
A small 32-bit computer for an embedded system might be RV32EC. A large 64-bit computer might
be RV64GC; i.e., shorthand for RV64IMAFDCZicsr_Zifencei. With the growth in the number of
extensions, the standard now provides for extensions to be named by a single "Z" followed by an
alphabetical name and an optional version number. For example, Zifencei names the instruction-
fetch extension. Zifencei2 and Zifencei2p0 name version 2.0 of the same.
Extensions specific to supervisor privilege level are named in the same way using "S" for prefix.
Extensions specific to hypervisor level are named using "H" for prefix. RISC-V developers may
create their own non-standard instruction set extensions. These follow the "Z" naming convention,
but with "X" as the prefix.
RV32IMAC, shown in figure , means:

• RV32I: A 32-bit CPU with the Base Integer ISA

• M: The Integer Multiplication and Division extension
• A: The Atomic Instruction extension
• C: The Compressed Instruction extension
Register sets
RISC-V has 32 (or 16 in the embedded variant) integer registers, and, when the floating-point
extension is implemented, separate 32 floating-point registers. Except for memory access
instructions, instructions address only registers.
The first integer register is a zero register, and the remainder are general-purpose registers. A store
to the zero register has no effect, and a read always provides 0. Using the zero register as a
placeholder makes for a simpler instruction set.
“move rx to ry becomes add immediate 0 to rx and store in ry.”

Memory access
Like many RISC designs, RISC-V is a load–store architecture: instructions address only registers,
with load and store instructions conveying data to and from memory. Memory is addressed as 8-bit
bytes, with instructions being in little-endian order and with data being in the byte order defined by
the execution environment interface in which code is running.
Most load and store instructions include a 12-bit offset and two register identifiers. One register is
the base register. The other register is the source (for a store) or destination (for a load).
RISC-V manages memory systems that are shared between CPUs or threads by ensuring a thread of
execution always sees its memory operations in the programmed order. A fence instruction
guarantees that the results of predecessor operations are visible to successor operations of other
threads or I/O devices.

Atomic memory operations

RISC-V supports computers that share memory between multiple CPUs and threads. RISC-V's
standard memory consistency model is release consistency. The atomic memory operation extension
supports two types of atomic memory operations for release consistency. First, it provides general
purpose load-reserved lr and store-conditional sc instructions. lr performs a load, and tries to
reserve that address for its thread. A later store-conditional sc to the reserved address will be
performed only if the reservation is not broken by an intervening store from another source. If the
store succeeds, a zero is placed in a register. If it failed, a non-zero value indicates that software
needs to retry the operation. In either case, the reservation is released.
The second group of atomic instructions perform read-modify-write sequences: a load (which is
optionally a load-acquire) to a destination register, then an operation between the loaded value and a
source register, then a store of the result (which may optionally be a store-release).\

Compressed subset
To compensate, RISC-V's 32-bit instructions are actually 30 bits; 3⁄4 of the opcode space is reserved
for a recommended variable-length compressed instruction set, RVC, that includes 16-bit
instructions. The compressed instructions are simply aliases for a subset of the larger instructions.
The researcher intended to reduce the code's binary size for small computers, especially embedded
computer systems. The prototype included 33 of the most frequently used instructions, recoded as
compact 16-bit formats using operation codes previously reserved for the compressed set.

Embedded subset
An instruction set for the smallest embedded CPUs (set E) is reduced in other ways: Only 16 of the
32 integer registers are supported. All current extensions may be used; a floating-point extension to
use the integer registers for floating-point values is being considered. The privileged instruction set
supports only machine mode, user mode and memory schemes that use base-and-bound address
relocation. There are also vector set and bit manipulation extensions.
Q2) What do you mean by Hardware Description Language? Also compare Verilog and chisel
HDL.

In computer engineering, a hardware description language (HDL) is a specialized computer

language used to describe the structure and behaviour of electronic circuits, and most commonly,
digital logic circuits. A hardware description language looks much like a programming language
such as C or ALGOL; it is a textual description consisting of expressions, statements and control
structures.
Using the proper subset of hardware description language, a program called a synthesizer, or logic
synthesis tool, can infer hardware logic operations from the language statements and produce an
equivalent netlist of generic hardware primitives to implement the specified behaviour.

(I) Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model
electronic systems. It is most commonly used in the design and verification of digital circuits at the
register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-
signal circuits, as well as in the design of genetic circuits.

a) Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the language available
for open standardization. Cadence transferred Verilog into the public domain under the Open
Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted
to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

b) System-Verilog
The advent of hardware verification languages such as OpenVera, and Verisity's e
language encouraged the development of Superlog by Co-Design Automation Inc (acquired
by Synopsys). The foundations of Superlog and Vera were donated to Accellera, which later became
the IEEE standard P1800-2005: System-Verilog.

c) Code (2 Flip Flops)

module toplevel(clock,reset);
input clock;
input reset;

reg flop1;
reg flop2;

always @ (posedge reset or posedge clock)

if (reset)
begin
flop1 <= 0;
flop2 <= 1;
end
 else
begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule

(II) Chisel
The Constructing Hardware in a Scala Embedded Language is an open-source hardware description
language (HDL) used to describe digital electronics and circuits at the register-transfer level. Chisel
is based on Scala as an embedded domain-specific language (DSL). Chisel inherits the object-
oriented and functional programming aspects of Scala for describing digital hardware. Using Scala
as a basis allows describing circuit generators. High quality, free access documentation exists in
several languages.

a) Code

class Add extends Module {

val io = IO(new Bundle {
val a = Input(UInt(8.W))
val b = Input(UInt(8.W))
val y = Output(UInt(8.W))
})

io.y := io.a + io.b

}