Scribd
Upload
33 views2 pages

Be Winter 2022

This document is an exam for a Computer Organization and Architecture course. It contains 5 questions assessing various topics: 1) Question 1 covers combinational circuits, registers, and the role of the sequence counter in the control unit. 2) Question 2 covers computer registers, addressing modes, instruction cycles, and microinstructions. 3) Question 3 covers assembly instructions, the control unit determining instruction type, CPU-IOP communication, and cache memory. 4) Question 4 covers memory hierarchy, assembly programming, assembler flowcharts, and direct memory access. 5) Question 5 covers hazards in pipelining, data dependency conflicts, microinstruction formats, cache types, and Flynn's classification scheme

Uploaded by

shah manan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
33 views2 pages

Be Winter 2022

This document is an exam for a Computer Organization and Architecture course. It contains 5 questions assessing various topics: 1) Question 1 covers combinational circuits, registers, and the role of the sequence counter in the control unit. 2) Question 2 covers computer registers, addressing modes, instruction cycles, and microinstructions. 3) Question 3 covers assembly instructions, the control unit determining instruction type, CPU-IOP communication, and cache memory. 4) Question 4 covers memory hierarchy, assembly programming, assembler flowcharts, and direct memory access. 5) Question 5 covers hazards in pipelining, data dependency conflicts, microinstruction formats, cache types, and Flynn's classification scheme

Uploaded by

shah manan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Seat No.: ________ Enrolment No.

___________

GUJARAT TECHNOLOGICAL UNIVERSITY


BE - SEMESTER–IV(NEW) EXAMINATION – WINTER 2022
Subject Code:3140707 Date:15-12-2022
Subject Name:Computer Organization & Architecture
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1 (a) Draw the block diagram of 4-bit combinational circuit shifter. 03
(b) Construct diagram of common bus system of four 4-bits registers with 04
diagram.
(c) What is the role of sequence counter(SC) in control unit? Interpret its 07
concept with the help of its three inputs using diagram.

Q.2 (a) List out names of eight main registers of basic computer with their 03
symbolic name and purpose.
(b) Summarize following addressing modes with example. 04
1) Implied mode 2) Register mode
(c) Which are the different phases of Instruction Cycle? Describe Register 07
transfer for fetch phase with its diagram.
OR
(c) Define: microinstruction; Identify different types of 16 bits instruction 07
formats for basic computer using figure.

Q.3 (a) Use BSA and BUN instruction with example and diagram. 03
(b) Criticize Three-Address Instructions and Zero address instruction with 04
common example.
(c) Describe how control unit determine instruction type after the 07
decoding using flowchart for instruction cycle.
OR
Q.3 (a) Prepare flowchart of CPU-IOP communication. 03
(b) Differentiate RISC and CISC architecture. 04
(c) What is cache memory? Interpret direct addressing mapping with 07
diagram.

Q.4 (a) Draw and criticize memory hierarchy in a computer system. 03


(b) Write an Assembly level program for addition of 50 numbers. 04
(c) Draw the flowchart of first pass of the assembler and explain working 07
of the same.
OR
Q.4 (a) Interpret the following instructions: INP, ISZ and LDA 03
(b) Write an Assembly level program to move one block of data to another 04
location.
(c) List out modes of transfer. Formulate direct memory access technique 07
in detail.

Q.5 (a) Summarize major hazards in pipelined execution. 03

1
(b) What is a data dependency conflict in instruction pipeline? 04
Recommend solutions for data dependency conflicts.
(c) Demonstrate four-segment instruction pipeline in detail 07
OR
Q.5 (a) Sketch Microinstruction code format. Quote BR and CD field in brief. 03
(b) Compare following terms: 04
1. Write through-cache and Write back cache.
2. Spatial locality and Temporal locality
(c) Elaborate flynn’s classification scheme with proper diagram. 07

*************

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy