ARM EMBEDDED

SYSTEM

Learning Objectives
1.1 Introduction

1.2 Microprocessors versus Microcontrollers

1.3 The RISC design philosophy

1.4 The ARM Design Philosophy

1.5 Embedded System Hardware

1.5.1 ARM Bus Technology

1.5.2 AMBA BUS Protocol

1.5.3 Memory

1.6 Embedded System Software

1.6.1 Initialization (BOOT) Code

1.7 ARM Processor Fundamental

1.7.1 Registers

1.7.2 Current Program Status Register

1.7.3 Pipeline
1.8 Exceptions, Interrupts, and the Vector Table

1.9 Core Extensions

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1.1 INTRODUCTION
An Embedded System is a special purpose computer system designed to perform
one or more dedicated functions, often with computing constraints. Embedded
systems controls many of the common devices in use today. Physically Embedded
systems range from portable devices such as digital watches automobiles, planes,
trains, GPS, robotics toys and so on.
All modern general-purpose computers employ the principles of the stored-
program digital computer. The stored-program concept originated from the
Princeton Institute of Advanced Studies in the 1940s and was first implemented in
the 'Baby' machine which first ran in June 1948 at the University of Manchester in
England.
A general-purpose processor is a finite-state automaton that executes instructions
held in a memory. The state of the system is defined by the values held in the
memory locations together with the values held in certain registers within the
processor itself. Each instruction defines a particular way the total state should
change and it also defines which instruction should be executed next.
A processor executes an individual instruction in a sequence of steps:-
A typical sequence might be:
a. Fetch the instruction from memory (fetch).
b. Decode it to see what sort of instruction it is (dec).
c. Access any operands that may be required from the register bank (reg).
d. Combine the operands to form the result or a memory address (ALU).
e. Access memory for a data operand, if necessary (mem).
f. Write the result back to the register bank (res).
The first ARM processor was developed at Acorn Computers Limited, of Cambridge,
England, between October 1983 and April 1985. At that time, in 1990, ARM stood
for Acorn RISC Machine. Later, after a judicious modification of the acronym
expansion to Advanced RISC Machine, it lent its name to the company formed to
broaden its market beyond Acorn's product range. Later it is reframed as simply
ARM Limited. (Advanced RISC Machines Limited)
ARM limited does not directly produce semiconductor ICs, but rather provides
licenses for microprocessor cores with 32-bit RISC architecture. ARM based chip
designs are used in the iPhone, iPad and also by many others in smartphone and
mobile hardware. To give an idea of the position of this designer on this market,
95% of mobile telephones in 2008 were made with ARM-based processors. It should
also be noted that the A4 and A5 processors, produced by Apple and used in their
iPad graphics tablets, are based on ARM Cortex-Type A processors. For the iPhone
6s and iPhone 6s Plus there actually two different ARM "A9" processors used in
these models.
 Arm Embedded 1
ARM processor families
 A series (Application) Application Processors are defined by the processor’s
ability to execute complex operating systems, including Linux, Android, Chrome
OS, Tizen, Microsoft Windows (CE/Embedded) and others. Applications include
smartphones, Feature Phones, Tablets/e-Readers, Advanced Personal Media
Players, Digital Television, Set-top Boxes/Satellite Receivers, High-End Printers,
Personal Navigation Devices, Server/Enterprise, Wear ables and Home
Networking.
 R series (Real-time) processors facilitates high performance and reliability for
real-time applications. Applications include automotive braking system, power
trains
 M series (Microcontroller) processors are the optimal solution for low-power
embedded computing applications. The 32-bit Cortex-M processor family is the
key to transforming all sorts of embedded systems into smart and connected
systems. Applications include microcontrollers, smart sensors, Merchant MCUs,
Automotive Control Systems, Motor Control Systems, White Goods controllers,
Smart Meters, Sensors and Internet of Things.
F igure 1 .1 shows the development stages of ARM versions

Figure 1.1: The evolution of ARM Processor Architecture

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1.2 MICROPROCESSORS VERSUS MICROCONTROLLERS
Sl.No Microprocessor Microcontroller
1. Contains ALU, General purpose In addition, it contains inbuilt ROM,
registers, SP, PC, clock, timing RAM, I/O device, timers/counters etc
circuit and interrupts
2. Many instruction to move data One or two instruction to move data
between memory and CPU between memory and CPU
13. One or two bit handling More number of bit handling
instructions are available instructions are available
4. Access time for memory and I/O Less access time for inbuilt memory
devices are more and I/O devices
5. Requires more hardware, increase Requires less hardware, reduced PCB
in PCB size size and increased reliability
6. More flexible from design point of Less flexible
view
7. Single memory map for data and Separate memory map for data and
code code
8. Few pins are multi functional More pins are multi functional
9. MP based computers are normally MC based systems are normally
operated with general purpose OS operated with RTOS like tiny RTOS, Vx
like Win, UNIX etc. works, PSOS, UC LINUX etc
Comparison between Harvard and Von-Neumann Architecture
Harvard Von – Neumann

Defines separate memory banks for Uses only one memory for storage of both
data and program storage. data and program.
Provides instruction parallelism. This The memory fetch operation must take
means that fetching of next and place first and this is followed by execution
execution of next instruction can of next instruction. The fetching of next
take place simultaneously instruction can take place only after
completion of execution of present
instruction. Hence the program execution
requires more time.
The design of chip provides The chip design is simplified as only one
additional hardware to identify the memory is to be identified.
program and data memory.
The instructions will take same The execution time varies widely.
number of cycles
Execution of instruction requires Large numbers of cycles are required for
fewer cycles. execution.
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1.3 RISC DESIGN PHILOSOPHY
(RISC: Reduced Instruction Set Computing)
RISC is a design Philosophy where you reduce the COMPLEXITY of the instruction
set, which will reduce the amount of space, time, cost, power, heat and other
things it takes to implement the instruction set part of a processor. It is aimed at
delivering simple but powerful instructions that execute within a single cycle at a
high clock speed. There are a number of factors which have transformed RISC
technology into a success in the marketplace.
 The RISC philosophy concentrates on reducing the complexity of instructions
performed by the between because it is easier to provide greater flexibility and
intelligence in software rather than hardware.
 RISC design places greater demands on the complier.
 CISC instruction more on hardware.
 The figure 1.2 shows emphasize of RISC and CISC

Figure 1.2: CISC Versus RISC

 The RISC philosophy is implemented with 4 major design rules.
4 major design rules for RISC
RISC: One cycle to execute

1. Instructions CISC :Many cycles to execute

RISC: Possible
2.Pipelines
(Parallel CISC: Not possible
Execution)
Many GPRS in RISC
3. Register
Few GPRS in CISC

RISC: Using GPR

4. Load/store Architecture
CISC: Direct memory
1 Microprocessors and
Instructions
RISC processors provide simple operations that can execute in a single cycle.
 The complier or programmer synthesizes complicated operations by combining
several simple instructions by combining several simple instructions
 Each instruction is a fixed length to allow the pipeline to fetch future
instructions before decoding the current instruction.
Pipelines: The processing of instruction is broken down into smaller units that can
be executed in parallel by pipelines.
 Ideally the pipeline advances by one step on each cycle for maximum throughout
Resistors: RISC machines have a large general-purpose register set. Any register
can contain either data or on address.
 Registers act as the fast local memory store for all data processing operations.
Load-store Architecture
The processor operates on data held in registers. Separate load and store
instructions transfer data between the register bank and external memory.

1.4 THE ARM DESIGN PHILOSOPHY

The ARM architecture has been designed to allow very small, yet high-performance
implementations. The architectural simplicity of ARM processors leads to very small
implementations, and small implementations allow devices with very low power
consumption.
There are a number of physical features that have driven the ARM processor design.
ARM design philosophy

Low-Battery
High code Less Compact Hardware Core
Power
Density Price in Size Debug Enhanced
Technology RISC
Architecture
 High code density is another major requirement since embedded system has
limited memory due to cost and physical size restrictions.
 ARM processor has been specifically designed to reduce power consumption and
extended battery operation-essential for applications such as mobile phones and
personal digital assistants.
 Embedded systems are price sensitive and use slow and low cost memory
devices.
1 Microprocessors and
 ARM processor demand to reduce the area of the die taken up the embedded
processor, the more available space for specialized peripherals.
 ARM has incorporated between debug technologies with in the processor so that
between engineers can view what is happening while the processor is executing
code.
 ARM Code is not a pure RISC architecture because of the constraints of its
primary application - the embedded system.
Comparison between RISC and CISC :
RISC CISC
Lesser no. of instructions Greater no. of Instructions
Instruction Pipelining and Generally no instruction pipelining feature
increased execution speed

Orthogonal Instruction Set Non Orthogonal Instruction Set (All

(Allows each instruction to instructions are not allowed to operate on any
operate on any register and use register and use any addressing mode. It is
any addressing mode) instruction specific)

Operations are performed on Operations are performed on registers or

registers only, the only memory memory depending on the instruction
operations are load and store

Large number of registers are Limited no. of general purpose registers

available

Programmer needs to write more Instructions are like macros in C language. A

code to execute a task since the programmer can achieve the desired
instructions are simpler ones functionality with a single instruction which in
turn provides the effect of using more simpler
single instructions in RISC

Single, Fixed length Instructions Variable length Instructions

Less Silicon usage and pin count More silicon usage since more additional
decoder logic is required to implement the
complex instruction decoding.

With Harvard Architecture Can be Harvard or Von-Neumann Architecture

1 Microprocessors and
Instruction Set for Embedded systems
The ARM instruction set differs from the pure RISC definition is several ways that
make the ARM instruction set suitable for embedded applications.

Features of ARM Instruction set

Variable cycle execution (Improves code density)

Inline barrel shifter (Improves performance)

Thumb 16-bit Instruction set (30% improve in density)

Conditional Execution (Reduction in Branch instruction)

Enhanced Instructions (DSP and XY)

1. Variable cycle execution for certain instructions: Not every ARM instruction
execution a single cycle for example: load-store multiple instructions vary in the
number of execution cycle depending upon the number of registers being
transferred.
2. Inline barrel shifter leading to more complex instructions: The line barrel
shifter is a hardware component that preprocesses one of the input register
before it is used by an instruction.
3. Thumb 16-bit instruction set: ARM enhanced the processor core by adding a
second 16-bit instruction set called thumb that permits the ARM code to execute
either 16 or 32 bit instructions.
The Thumb instruction set addresses the issue of code density. It may be viewed
as a compressed form of a subset of the ARM instruction set. Thumb
instructions map onto ARM instructions, and the Thumb programmer's model
maps onto the ARM programmer's model. Implementations of Thumb use
dynamic decompression in an ARM instruction pipeline and then instructions
execute as standard ARM instructions within the processor.
Thumb properties
 The Thumb code requires 70% of the space of the ARM code.
 The Thumb code uses 40% more instructions than the ARM code.
 With 32-bit memory, the ARM code is 40% faster than the Thumb code.
 With 16-bit memory, the Thumb code is 45% faster than the ARM code.
 Thumb code uses 30% less external memory power than ARM code.
4. Conditional execution: An instruction only executed when a specific
condition has been satisfied. This feature improves performance and code
density by reducing branch instructions.
5. Enhanced instructions: The enhanced digital signal processor (DSP)
1 Microprocessors and
instructions were added to the standard ARM instruction set to support fast
16  16 bit multiplier operations and saturation.

1.5 EMBEDDED SYSTEM HARDWARE

Embedded system can control many different devices from small sensors found on a
production line, to the real-time control systems used on a NASA space probe.
The below figure 4.3 shows a typical embedded device based on an ARM core. Each
box represents a feature or function.

External
ARM RAM
Memory control
External
Intr.contr ROM
AHB External Bus
AHB Extension
orbitrar
AHB-APB
Bridge

RTC Ethernet Physical Drive

Etherne t Counter/
Timer
Serial UART

Figure 4.3: ARM based embedded

system The ARM Architecture
 Arithmetic Logic Unit
 Booth multiplier
 Barrel shifter
 Control unit
 Register file
This article covers the below mentioned components.
The ARM processor conjointly has other components like the Program status
register, which contains the processor flags (Z, S, V and C). The modes bits
conjointly exist within the program standing register, in addition to the interrupt
and quick interrupt disable bits.
Some special registers: Some registers are used like the instruction, memory data
read and write registers and memory address register.
Priority encoder: The encoder is used in the multiple load and store instruction
to point which register within the register file to be loaded or kept .
Multiplexers: Several multiplexers are accustomed to the management operation
1 Microprocessors and
of the processor buses. Because of the restricted project time, we tend to implement
these components in a very behavioral model. Each component is described with an
entity. Every entity has its own architecture, which can be optimized for certain
necessities depending on its application. This creates the design easier to construct
and maintain.

Arithmetic Logic Unit (ALU)

The ALU has two 32-bits inputs. The primary comes from the register file, whereas
the other comes from the shifter. Status registers flags modified by the ALU
outputs. The V-bit output goes to the V flag as well as the Count goes to the C flag.
Whereas the foremost significant bit really represents the S flag, the ALU
output operation is done by NORed to get the Z flag. The ALU has a 4-bit
function bus that permits up to 16 opcode to be implemented.

Booth Multiplier Factor

The multiplier factor has three 32-bit inputs and the inputs return from the register
file. The multiplier output is barely 32-Least Significant Bits of the merchandise.
The entity representation of the multiplier factor is shown in the above block
diagram. The multiplication starts whenever the beginning 04 input goes active.
Fin of the output goes high when finishing.
Booth algorithm is a noteworthy multiplication algorithmic rule for 2’s complement
numbers. This treats positive and negative numbers uniformly. Moreover, the runs
of 0’s or 1’s within the multiplier factor are skipped over without any addition or
subtraction being performed, thereby creating possible quicker multiplication. The
figure 4.4 shows the simulation results for the multiplier test bench. It’s clear that
the multiplication finishes only in16 clock cycle.

Barrel Shifter
The barrel shifter features a 32-bit input to be shifted. This input is coming back
from the register file or it might be immediate data. The shifter has different
control inputs coming back from the instruction register. The Shift field within the
instruction controls the operation of the barrel shifter. This field indicates the
kind of shift to be performed (logical left or right, arithmetic right or rotate
right). The quantity by which the register ought to be shifted is contained in an
immediate field within the instruction or it might be the lower 6 bits of a register
within the register file.
The shift_val input bus is 6-bits, permitting up to 32 bit shift. The shifttype
indicates the needed shift sort of 00, 01, 10, 11 are corresponding to shift left, shift
 Arm Embedded 1
right, an arithmetic shift right and rotate right, respectively. The barrel shifter is
especially created with multiplexers.

Control Unit
For any microprocessor, control unit is the heart of the whole process and it is
responsible for the system operation, so the control unit design is the most
important part within the whole design. The control unit is sometimes a pure
combinational circuit design. Here, the control unit is implemented by easy state
machine. The processor timing is additionally included within the control unit.
Signals from the control unit are connected to each component within the processor
to supervise its operation.
The final thing that must be explained is how the ARM will be used and the way in
which the chip appear. The various signals that interface with the processor are
input, output or supervisory signals which will be used to control the ARM
operation.
An example of an ARM-based embedded device, a microcontroller.
The lines connecting the boxes are the buses carrying data. We can separate the
device into 4 main hardware components.
 The ARM processor controls the embedded device.
Different versions of the ARM processor are available to suit the desired
operating characteristics. An ARM processor comprises a core plus the
surrounding components that interface it with a bus.
 Controllers coordinate important functional blocks of the system. Two commonly
found controllers are interrupt and memory controllers.
 The peripherals provide all the input-output capability external to the chip and
are responsible for the uniqueness of the embedded device.
 A bus is used to communicate between different-parts of the device.

1.5.1 Arm Bus Technology

Embedded system use different bus technologies than those designed for X86 PCs.
The most common PC bus technology, the peripheral component-Interconnect (PCI)
bus, connects such devices as video cards and hard disk controllers to the X86
processor bus. The figure 1.4 represents the architecture of ARM bus technology.
1 Microprocessors and

Figure 1.4: ARM Bus Technology

 The contrast, embedded devices use on chip i.e, internal to the chip and that
allows different peripheral devices to be interconnected with an ARM core.
 There are two different classes of devices attached to the bus
1. ARM processor core is a bus master.
o A logical device capable of initiating a data transfer with another device
across the same bus.
2. Peripherals tend to be bus slaves
o Logical devices capable only of responding to a transfer request from a
bus master device.
A bus has two architecture levels
1. Physical level that covers the electrical characteristics and bus width.
2. Second level deals with protocol-the logical roles that govern the
communication between the processor and a peripheral.

1.5.2 AMBA Bus Protocol

AMBA stands for Advanced Microcontroller Bus Architecture. AMBA specification
specifies an on chip communication standard. This is used to design embedded
microcontrollers with high performance. The Advanced Microcontroller Bus
Architecture (AMBA) was introduced in 1996 and has been widely adopted as the on
chip bus architecture used for ARM processors.
 Arm Embedded 1
Bus Architecture

Physical level Protocol level (ARM)

ASB AHB
(ARM System APB
(ARM Peripheral Bus) (ARM High
Bus) Performance Bus)

Multilayer AHB AHB Lite

(mutlilayer) (single master)
High rate Low rate
 The first AMBA buses introduced were the ARM system Bus (ASB) and ARM
peripheral Bus (APB)
 Later ARM introduced another bus design, called ARM high performance Bus
(AHB)
 Introduction of ARM provides plug and play interface for hardware developers
improves availability and time to market.
 AHB provides higher data throughout tan ASB because it is based on centralized
multiplexed bus scheme rather than the ASB bidirectional bus design.
 ARM has introduced two variations on the AHB bus
3. Multi-layer AHB
4. AHB Lite
Multi-layer AHB bus allows multiple active bus masters, AHB Lite is a subset of
the AHB bus and it is limited to a single bus master.
 AHB and multi-layer AHB support the same protocol for master and slave but
have different interconnects.

1.5.3 Memory
Memory is any physical device capable of storing information temporarily or
permanently. For example, Random Access Memory (RAM), is a volatile memory
that stores information on an integrated circuit used by the operating system,
software, and hardware. Memory width is the number of bits the memory returns
on each access typically 8, 16, 32, or 64 bits.
The memory width has a direct effect on the overall performance and cost ratio. An
embedded system has to be have some form of memory to store and execute code.
 Arm Embedded 1
You have to compare price, performance and power consumption when deciding
upon specific memory characteristics such as hierarchy, width and type.
Hierarchy
All computer system have memory arranged in some form of hierarchy. There is an
option of a cache to improve memory performance.
 The figure 1.5 shows memory trade-off

Figure 1.5: Storage trade offs

 The fastest memory cache is physically located nearer the ARM processor core
and the slowest secondary memory is set further away. Generally the closer
memory is to the processor core, the more its costs and the smaller its capacity.
 The cache is placed between main memory and the core. It is used to speed up
data transfer between the processor and main memory.
A cache provides an overall increases in performance but with a loss of predictable
execution time. Although cache increases the general performance of the system.
WIDTH
The memory width is the number of bits the memory returns on each access-
typically 8, 16, 32 or 64 bits. The memory width has a direct effect on the overall
performance and cost ratio.
 If you have an uncached system using 32-bit ARM instruction and 16-bit wide
memory chips, then the processor will have to make two memory fetches per
instruction. Each fetch requires two 16-bit loads.
 In contrast, if the core executes 16-bit thumb instructions, it will achieve better
performance with a 16-bit memory.
Table 1.1 Fetching instructions from memory
Instruction 8-bit 16-bit 32-bit
size memory memory memory
ARM 32-bit 4 cycles 2 cycles 1 cycle
Thumb 16-bit 2 cycles 1 cycle 1 cycle
 Arm Embedded 1
Types of memory
There are many different-types of memory. Here are some of the more popular
memory devices found in ARM-Based embedded system.
Memory

Secondary
Primary ROM (Code
RAM (DATA memory)
memory)

ROM DRAM
Flash Rom SRAM SDRAM
(Boot code) (Refresh)
(Firm ware) (Faster) (High speed)
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ROM: Read-only memory (ROM) is the least flexible of all memory types because it
contains an image that is permanently set at production time and cannot be
reprogrammed. Devices use a ROM to hold boot code. Its main use is for holding
the device firmware or storing long-term data that needs to be preserved after power
is off.
Flash ROM : It can be written to as well as read, but it is slow to write so you
should not use it for holding dynamic data. Its main use is for holding the device
firmware or storing the long term data that needs to be preserved after power is off.
DRAM: Dynamic Random Access Memory (DRAM) is the most commonly used RAM
for devices. It has the lowest cost per megabyte compared with other types of RAM.
DRAM is dynamic- it needs to have its storage cells refreshed and given a new
electronic charge every few milliseconds, so you need to set up a DRAM controller
before using the memory.
SRAM: Static Random Access Memory (SRAM) is faster than the more traditional
DRAM, but requires more silicon area. SRAM is static-the RAM does not require
refreshing.
SDRAM: SDRAM stands for Synchronous Dynamic Random Access Memory. It is
one of the DRAM type. It runs at high clock speed compare to conventional memory.
It gets synchronize with processor bus as SDRAM is clocked.
 ARM PERIPHERALS
A peripheral device performs input and output functions for the chip by connecting
to other devices or sensors that are off-chip.
All ARM peripherals are memory mapped-the programming interface is a set of
memory- addressed registers. The address of these registers is an offset from a
specific peripheral base address.
Controllers are specialized peripherals that implement higher levels of
functionality within an embedded system.
 Peripherals range from a simple serial communication device to a more complex
802.11 wireless device.
 Controllers are specialized peripherals that implement higher levels
of functionality with in an embedded system.
 Two important types of controllers are memory controllers and interrupt
controllers.

Specialized Peripherals
1 Microprocessors and
Memory controller Interrupt controller

SIC VIC
Memory Controllers
Memory controllers connect different types of memory to the processor bus. On power-
up a memory controller is configured in hardware to allow certain memory devices to
be active. These memory devices allow the initialization code to be executed. Some
memory devices must be set up by software; for example, when using DRAM, you
first have to set up the memory timings and refresh rate before it can be accessed.

Interrupt Controllers
An interrupt controller provides a programmable governing policy that allows
software to determine which peripheral or device can interrupt the processor at any
specific time by setting the appropriate bus in the interrupt controller registers.
There are two types of interrupt controller available for the ARM processor.
1. The standard interrupt controller
2. Vector Interrupt controller (VIC)

1. Standard interrupt controller: The interrupt handler determines which device

requires servicing by reading a device bitmap register in the interrupt controller.
2. Vector interrupt controller (VIC): Prioritizes interrupts and simplifies the
determination of which device caused the interrupt. After associating a priority
and a handler address with each interrupt, the VIC only asserts an interrupt
signal to the core if the priority of a new interrupt is higher than the currently
executing interrupt handler.
 Arm Embedded 1
1.6 EMBEDDED SYSTEM SOFTWARE
An embedded system needs between to drive it. Figure 1.6 below shows 4 typical
software components required to control an embedded device

Application
OS
Initialization Device
Driver
Hardware device

Figure 1.6: Software abstraction layers executing on hardware

The initialization code is the first code executed on board and is specific to a
particular target or group of targets. It sets up the minimum parts of the board
before handling control over to the operating system.
 The operating system provides an infrastructure to control applications and
range between system resources.
 The device drivers are the third component. They provide a consistent between
interface to the peripherals on the hardware device.
Finally an application performs one of the tasks required for a device.
Initialization OS Device Driver
Applicatio
n
Booting

Initial Diagnostics
Hardware Platform OS (Linux)
Configuration RTOS
(VX works)

1.6.1 Initialization (BOOT) Code

Initialization code is basically a set of "instructions" that is run by a CPU while
starting up. The boot code helps the computer prepare the system for loading and
running an operating system, but boot code itself is typically not operating system
specific. Initialization code takes the processor from the reset state to a state where
the operating system can run.
 It usually configures the memory controller and processor caches and initializes
some device.
 The initialization code handles a number of administrative tasks prior to
handling control over to an operating system image.
 We can group these different tasks into three phases.
1 Microprocessors and
1. Initial hardware configuration
2. Diagnostics
3. Booting
Initial hardware configuration involves setting up the target platform so it can
boot an image. Although the target platform itself comes up in a standard
configuration, this configuration normally requires modification to satisfy the
requirements of the booted image. The figure 1.7 shows memory remapping.

Figure 1.7: Memory Remapping

Diagnostics are embedded in the initialization code. Diagnostic code tests the
system by exercising the hardware target to check if the target is in working order.
Booting involves loading an image and handling control over to that image. The
boot process itself can be complicated if the system must boot different operating
system or different versions at the same operating system.
Operating System
An operating system or OS is a software program that enables the
computer hardware to communicate and operate with the computer software. The
initialization process prepares the hardware for an operating system to take control.
 An operating system organizes the system resource the peripherals, memory
and processing time.
 ARM processors support over 50 operating system. We can divide operating
systems into two main categories: real-time operating system (RTOS) and
platform operating systems.
 Different operating system have different amounts of control over the system
response time. A hard real-time application requires a guaranteed response to
work at all. In contrast, a software real-time application requires a good
 Arm Embedded 1
response time, but the performance degrades more gracefully if the response
time over runs.
 Platform operating system requires a memory management unit to manage
large, non real-time applications and tend to have secondary storage.
Applications
The operating system schedules applications – code dedicated to hardling a
particular task. An operating implements a processing task; the operating system
controls the environment. An embedded system can have one active application or
several applications running simultaneously.
ARM processors are found in numerous market segments, including networking,
automotive, mobile and consumer devices, mass storage devices, mass-storage and
imaging within each segment ARM processors can be found in multiple
applications.
For example, the ARM processor is found in networking applications like home
gateways, DLS modems for high-speed internet communication, and 802.11
wireless communication

1.7 ARM PROCESSOR FUNDAMENTALS

The ARM processor has “load and store” architecture. Separate instructions
for Load( loading the registers from memory) & Store( storing the register
contents into memory) are available. No direct data processing in memory.
Architecture can be Harvard( separate instruction & data bus) or Von-Newman
(same instruction & data bus)
A programmer can think of an ARM core as functional units connected by data
buses as shown in figure 1.8 where, the arrows represent the flow of data, the lines
represent the buses and the boxes represent either an operation unit or a storage
area. The figure 1.8 shows not only the flow of data but also the abstract
components that make up an ARM core.
 Data enters the processor core through the data bus. The data may be an
instruction to execute or a data item. Figure 1.8 shows a Von Neumann
implementation of the ARM data items and instructions share the same bus.
In contrast, Harvard implementations of the ARM use two different buses.
 ARM processor, like all RISC processors, uses a load store architecture. This
means it has two instruction types for transforming data in and out of the
processor.
 Load instructions copy data from memory to registers in the core and
conversely the store instructions copy data from registers to memory.
1 Microprocessors and
 Data items are placed in the register file-a storage bank made up of 32-bit
registers. Since the ARM core is a 32-bit processor, most instructions treat the
registers as holding signed or unsigned 32-bit values.

Figure 1 .8: ARM Core dataflow model

 ARM instructions typically have two source registers R n and Rm and single result
or destination register R d. Source operands are read from the register file using
the internal buses A and B respectively.
 The ALU or MAC takes the register values Rn and Rm from the A and B buses
and computes a result. Data processing instructions write the result in Rd
directly to the register file.
 One important feature of the ARM is that register Rm alternatively can be
preprocessed in the barrel shifter before it enter the ALU.
 Rd is written back to the register file using the result bus.
 Arm Embedded 1
 The processor continues executing instructions until an exception or interrupt
changes the normal execution flow.
1.7.1 Registers
General-purpose registers hold either data or an address. They are identified with
the letter r prefixed to the register number. For example register 4 is given the label
r4.
 The figure 1.9 shows the active registers available in user mode – a protected
mode normally used when executing applications. The processor can operate in
seven different modes.
 There are upto 18 active registers 16 data register and 2 processor status
register. The data registers are visible to the programmer as r0 to r15.

Figure 1.9: Registers available in user mode

The ARM processor has 3 registers assigned to a particular task or special function:
r13, r14 and r15. They are frequently given different labels to differentiate them
from the other registers.
In figure 1.9 the shaded registers identify the assigned special purpose registers.
 Register r13 is traditionally used as the stack pointer (sp) and stores the head of
the stack in the current processor mode.
 Register r14 is called the link register (1r) and is where the core puts the return
address whenever it called a subroutine.
1 Microprocessors and
 Register r15 is the program counter (pc) and contains the address of the next
instruction to be fetched by the processor.
 Depending upon the contact, register r13 and r14 can also be used as general
purpose registers, which can be particularly useful since these registers are
banked during a processor mode change.
1.7.1 Current Program Status Registers
 The ARM core uses the CPSR to monitor and control internal operations. The
CPSR is a dedicated 32-bit register and resides in the register file. The figure
1.10 shows the basic layout of a generic program status register.

Figure .10 A generic program status register

 The CPSR is divided into four fields, each 8 bits wide flags, status, extension and
control. In current designs the extension and status fields are reserved for
future use
 The control field contains the processor mode, states and interrupt mark bits.
The flags field contains the condition flags.
 Some ARM processor cores have extra bits allocated. For example the J bit
which can be found in the flags field, is only available on Jazelle – enabled
processors, which execute 8 bit instructions.
 Address space model: The normal use of memory is illustrated . Where an
application can use the entire memory space (or where a memory management
unit can allow an application to think it has the entire memory space), the
application image is loaded into the lowest address, the heap grows upwards
from the top of the application and the stack grows downwards from the top of
memory. The unused memory between the top of the heap and the bottom of the
stack is allocated on demand to the heap or the stack, and if it runs out the
program stops due to lack of memory.
 Arm Embedded 1

Figure 1 .11: The standard ARM C program address space model

Processor Modes
The processor mode determines which registers are active and the access rights to
the CPSR register itself. Each processor mode is either privileged or non-privileged.
 A privileged mode allows full read-write access to the CPSR.
 A non privileged mode allows read access to the control field in the CPSR,
but still allows read and write access to the conditional flags.
 In total, there are seven processor modes & six privileged modes
Processor modes

Privileged Non-privileged mode

(Full R/W to CPSR) R  control field
R/W  conditional flags

Abort – memory Access fail (r13 & t14) (Abort)

User mode
Fast interrupt Request (r8-r14) (FIQ)
1 Microprocessors and
Interrupt Request (r13 and r14) IRQ

Supervisor – After rest (r13 and r14) Supervisor

System-Supervisor with R and W (r13 and r14) (System)

Undefined – No implementation (r13 and r14)

The ARM7TDMI processor has seven modes of operations:

1. Abort: Abort mode is used when there is a field attempt to access memory. It
implements virtual memory and/or memory protection
2. Fast interrupt request: Fast interrupt request and interrupt request modes
correspond to the two interrupt levels available on the ARM processor. It
supports a high-speed data transfer or channel process.
3. Interrupt request mode: it corresponds interrupts.
4. Supervisor mode :It is Protected mode for the operating system.
5. System mode: System mode is a special version of user mode that allows full
read write access to the CPSR.
6. Undefined mode: Undefined mode is used when the processor encounters an
instruction i.e., undefined or not supported by the implementation. supports a
software emulation of hardware coprocessors.
7. User mode: it is a Normal program execution mode. User mode is used for
programs and applications.
ƒ Note1 : When in a privileged mode, it is also possible to load ‐store the (banked
out) user mode registers to or from memory.
Note2: Except user mode, all are known as privileged mode
Banked Registers
The figure 1.12 shows 37 registers in the register file. In this register organisation ,
20 registers are hidden from a program at different times. These registers are called
Banked registers and are identified by the shaded part in the diagram.
1 Microprocessors and

Figure 1.12 Complete ARM Register set

 Arm Embedded 1
 Banked registers at a particular mode are denoted by an underline character
post-fixed to the mode mnemonic or mode.
 Every processor mode except user mode can change made by writing directly to
the mode bits of the CPSR.
 All processor modes except system mode have a set of associated banked that
are a subset of the main 16 registers. A banked register maps one-to-one onto a
user mode register.
For example: When the processor is in the interrupt register mode. The
instructions you execute still access registers named r13 and r14.
 The processor mode can be changed by a program that writes directly to the
CPSR or by hardware when the core responds to an exception or interrupt. The
following exceptions and interrupts cause a mode change: reset, interrupt
request, fast interrupt request, software interrupt, data abort, prefetch abort and
undefined instruction.
 The figure 1.13 shows the core changing from user mode to interrupt request
mode, which happens when an interrupt request occurs due to an external
device raising an interrupt to the processor core. This change causes user
register r13 and r14 to be banked.

Figure 1.13 Changing mode on an exception

 Arm Embedded 1
Figure 1.13 also shows a new register appearing in interrupt request mode: the saved
program status register (SPSR) which stores the previous mode’s CPSR.It can be
seen in the diagram and the CPSR being copied into spsr_irq.
The below table shows various modes and the associated binary patterns
Mode Abbreviation Privileged Mode [4.0]
Abort Abt Yes 10111
Fast interrupt request Fiq Yes 10011
Interrupt request Irq Yes 10010
Supervisor Svc Yes 10011
System Sys Yes 11111
Undefined Und Yes 11011
User Usr Yes 10000

State and Instruction Sets

The state of the core determines which instruction set is being executed. There are
three instruction sets.
Instruction set

ARM – 32 bit Thumb – 16 bit Jazzel – 8 bit

Conditional Execution (30% code density Reduction)

Unconditional
Execution

1. ARM: The ARM instructions are 32 bits long. ƒ Most instructions execute in a
single cycle. ƒ Most instructions can be conditionally executed.
2. Thumb: Thumb is a 16 ‐bit instruction set – Optimized for code density from C
code. also Improved performance form narrow memory and it is the subset of
the functionality of the ARM instruction set
3. Jazelle: The Jazelle J and Thumb T bits in the CPSR reflect the state of the
processor. When both J and T bits are 0, the processor is in ARM state and
executes ARM instructions. This is the case when power is applied to the
processor.
 Arm Embedded 1
The table compares the ARM and thumb instruction set features ARM
and thumb instruction set features

ARM (cpsr T = 0) Thumb (cpsr T = 1)

Instruction size 32 bit 16-bit
Core instruction 58 30
Conditional Most Only branch instructions
execution
Data processing Access to barrel shifter Separate barrel shifter and ALU
instructions and ALU instructions
Program status Red-write in privileged No direct access
register mode
Register usage 15 general- purpose 8 general-purpose registers +7
registers + pc high registers + pc
The ARM designers introduced a third instruction set called Jazelle. Jazelle
executes 8-bit instruction and is a hybrid mix of software and hardware designed to
speed up the execution of Java byte codes.
The Jazelle instruction are used to stop specific interrupt requests from
interrupting the processor. There are two interrupt request levels available on the
ARM processor core – Interrupt request (IRQ) and fast interrupt request (FIQ).
The CPSR has two interrupt mask bits 7 and 6 (I and F) which control the masking
of IRQ and FIQ respectively. The I bit makes IRQ when set to binary 1, and similarly
the F bit … masks FIQ when set to binary 1.
Note: When the processor is executing in ARM state, All instructions are 32 bits in
length and all instructions must be word aligned. Therefore the PC value is stored
in bits [31:2] with bits [1:0] equal to zero as instruction cannot be halfword or byte
aligned.
Condition Flags
Condition flags are updated by comparisons and the result of ALU operations that
specify the S instruction suffix.
 For example, if a SUBS subtract instruction results in a registers value of zero,
then the Z flag in the CPSR is set. This particular subtract instruction
specifically updates the CPSR.
 Most ARM instructions can be executed conditionally on the value of the
conditional flags.
 Arm Embedded 1
The table lists the conditional flags and a short description on what causes them to
be set.
Condition flags
Flag Flag Name Set when
Q Saturation The result causes an overflow and/or saturation
V Overflow The result causes a signed overflow
C Carry The result causes an unsigned carry
Z Zero The result is zero, frequently used to indicate equality
N Negative Bit 31 of the result is a binary 1
 The figure 1.14 shows a typical value for the CPSR with both DSP extensions
and Jazelle. The notation is used in CPSR is in a more human readable form.
When a bit is a binary 1, we use a capital letter, when a bit is a binary zero we
use a lower case letter.
 In the CPSR shown below, the C flag is the only flag set to 1. The rest nzvq flags
are all clear. The ARM processor is in ARM state because neither the Jazelle or
 Thumb t bits are set. The IRQ interrupts are executed and FIQ interrupts are
disabled as shown in the figure.

Figure 1.14: Example: cpsr = nzCvajiFt_SVC

Condition Mnemonics
Conditional execution controls whether or not the core will execution instruction.
Most instructions have a condition attribute that determines if the core will execute
it based on the setting of the condition flags.
 Prior to execution, the processor compares the condition attribute with the
condition flags in the CPSR.
 The condition attribute is post fixed to the instruction mnemonic, which is
encoded into the instruction. The below table lists the conditional execution
code mnemonics.
 Arm Embedded 1
Conditional mnemonics
Mnemonic Name Condition flags
EQ Equal Z
NE Not equal Z
CS HS Carry set/unsigned higher or same C
CC LO Carry clear/unsigned lower c
MI Minus/negative N
PL Plus/positive or zero N
VS Overflow V
VC No Overflow v
Mnemonic Name Condition flags
HI Unsigned higher zC
LS Unsigned lower or same Z or c
GE Signed greater than or equal NV or nv
LT Signed less than Nv or nV
GT Signed greater than NzV or nzv
LE Signed less than or equal Z or Nv or nV
AL Always (unconditional) ignored
 Arm Embedded 1
1.7.3 Pipeline

Figure 1 .15: ARM 7 Three-stage pipeline

A pipeline is the mechanisms a RISC processor uses to execute instructions using a
pipeline speeds up execution by fetching the next instruction while other
instructions are being decoded or executed.
 ARM 7 uses three stage pipeline. The figure 1.15 shows three stage pipeline.
 Fetch loads an instruction from memory.
 Decode identifies the instruction to be executed
 Execute processes the instruction and writes the result back to a register.

The figure 1.16 illustrates the pipeline using a simple example. It shows a sequence
at three instructions being fetched, decoded and executed by the processor. Each
instruction takes a single cycle to complete after the pipeline is filled.
1 Microprocessors and
The three instructions are placed into the pipeline sequentially. In the first cycle the
core fetches the ADD instructions from memory. In the second cycle the core
fetches the SUB instructions and decodes the ADD instruction.
In the third cycle, both the SUB and ADD instructions are moved along the
pipeline. The ADD instruction is executed the SUB instruction is decoded, and the
CMP instruction is fetched. This procedure is call filling the pipeline. The pipeline
allows the core to execute on instruction every cycle.
As the pipeline length increases, the amount of work done at each state is reduced,
which allows the processor to attain a higher operating frequency. This in turn
increases the performance. The system latency also increases because it takes more
cycles to fill the pipeline before the core can execute an instruction.
The pipeline design for each ARM family differs. For example, the ARM of 9 core
increases the pipeline length to five stages as shown in the figure 4.17 below.

Figure 1 .17: ARM 9 five pipeline

The ARM 9 adds a memory and write stage, which allows the ARM 9 to process on
average 1.1 Dhrystone MIPS/MHZ
The ARM 10 increases the pipeline length still further by adding a sixth stage as
shown in the figure 1.18 below
The ARM 10 can process on average 1.3 Dhrystone MIPS per MHZ

Figure 1.18: ARM10

1 Microprocessors and
Pipeline executing characteristics
The ARM pipeline has not processed an instruction until it passes completely
through the execute stage.
The figure 1.19 shows an instruction sequence on an ARM 7 pipeline

Figure 1.19: ARM instruction sequence

The MSR instruction is used to enable IRQ interrupts, which only occurs once the
MSR instruction completes the execution stage of the pipeline. It clears the I bit in

the CPSR to enable the IRQ interrupts, once the ADD instruction enters the execute
stage of the pipeline, IRQ interrupts are enabled.
The below figure 1.20 illustrates the use of the pipeline and the program counter PC

Figure 1.20: Example: pc = address + 8

In the execute stage, the PC always points to the address of the instruction being
executed plus two instructions ahead. This is important when the PC is used for
calculating a relative offset and is an architectural characteristic across all the
pipelines. Note: When the processor is in thumb state the PC is the instruction
address plus 4.
There are three other characteristics of the pipeline.
1. The execution of a branch instruction or branching by the direct modification of
the PC causes the ARM core to flush its pipeline.
2. ARM 10 uses branch prediction, which reduces the effect of a pipeline flush by
predicting possible branches and loading the new branch address prior to the
execution of the execution.
1 Microprocessors and
3. An instruction in the execution stage will complete even through an interrupt
has been raised.

1.8 EXCEPTIONS, INTERRUPTS AND THE VECTOR TABLE

When an exception or interrupt occurs, the processor sets the PC to a specific
memory address. The address is within a special address range called the vector
table.
 The entries in the vector table are instructions that branch to a specific routines
designed to handle a particular exception or interrupt.
 The memory map address 0X00000000 to 0X0000001C is reserved for vector
table.
 When an exception or interrupt occurs, the processor suspends normal
execution and starts loading instructions from the exception vector table.
 The figure shows vector table.

Exception/interrupt Shorthand Address High address

Reset RESET 0x00000000 0xffff0000
Undefined instruction UNDEF 0x00000004 0xffff0004
Software interrupt SWI 0x00000008 0xffff0008
Prefetch abort PABT 0x0000000c 0xffff000c
Data abort DABT 0x00000010 0xffff0010
Reserved - 0x00000014 0xffff0014
Interrupt request IRQ 0x00000018 0xffff0018
Fast interrupt request FIQ 0x0000001c 0xffff001c

Each vector table entry contains a form of branch instruction and points to the
start of a specific routine
 Reset vector is the location of the first instruction executed by the processor
when power is applied.
 Undefined instruction vector is used when the processor cannot decode an
instruction.
 Software interrupt vector is called when you execute SWI instruction. The SWI
instruction is frequently used as the mechanism to invoke an operating system
routine.
 Pre-fetch abort vector occurs when the processor attempts to fetch an
instruction from an address without the core-access permissions. The actual
abort occurs in the decode stage.
 Data abort vector is similar to a pre-fetch abort but is raised when an
instruction attempts to access memory without the correct access permission.
1 Microprocessors and
 Interrupt request vector is used by external hardware to interrupt the normal
flow of the processor.
 Fast interrupt request vector is reserved for hardware requiring faster response
times.

1.9 CORE EXTENSIONS

The hardware extensions covered are standard components placed next to the ARM
core.
 They improve performance, manage resources, and provide extra functionality
and are designed to provide flexibility in handling particular applications.
 There are three hardware extensions ARM wraps around the core.
Hardware Core Extensions

5. Cache and tightly coupled memory

6. Memory management

7. Coprocessor interface
Cache and tightly coupled memory
The cache is a block of fast memory placed between main memory and the core. It
allows for more efficient fetches from some memory types.
 Most ARM-based embedded system use a single-level cache internal to the
processor.
 ARM has two forms of cache. The first is found attached to the Von Neumann-
style cores. It combines both data and instruction into a single unified cache as
shown in figure 1.21.

Figure 1.21: A simplified Von Neumann architecture with cache

1 Microprocessors and

Figure 1.22: A simplified Harvard architecture with TCMs

A cache provides an overall increase in performance but at the expense of
predictable execution. But for real-time system it is paramount that code execution
is deterministic the time taken for loading and storing instructions or data must be
predictable. This is achieved using a form of memory called tightly coupled memory
(TCM). TCM upper as memory in the address map and can be accessed as fast
memory. Processor with TCM in figure 1 .22 .

By combine both technologies, ARM processor can have both improved

performance and predictable real time response. The figure 1.23 below shows an
example core with a combination of caches with TCMs.

Figure 1.23: A simplified Harvard architecture with caches and TCMs

Memory management
ARM cores have three different types of memory management hardware-no
extensions providing no protection, a memory protection unit (MPU) providing
limited protection and a memory management unit (MMU) providing full protection.
 Non-protected memory is fixed and provides very little flexibility. It is normally
used for small, simple embedded system that require no protection from rogue
application.
 MPU’s employ a simple system that uses a limited number of memory regions
1 Microprocessors and
are controlled with a set of special coprocessor registers and each region is
defined with specific access permissions.
 MMUs are the most comprehensive memory management hardware available on
the ARM. The MMU uses a set of translation tables to provide time-grained
control over memory.
Coprocessor
Coprocessors can be attached to the ARM processor.
A coprocessor extends the processing features of a core by extending the instruction
set or by providing configuration registers.
 The co-processor can be accessed through a group of dedicated ARM instruction
that provide a load-store type interface.
 The coprocessor can be also extend the instruction set by providing a specialized
group of new instructions. For example, there are a set of specialised
instructions that can be added to the standard ARM instruction set to process
vector floating-point (VFP) operations.
 These new instructions are processed in the decode stage of the ARM pipeline. If
the decode stage sees a coprocessor instruction, then it offers it to the relevant
coprocessor.
REVIEW QUESTIONS

1. Explain the architecture of a typical embedded based on ARM core with a neat
diagram.
2. Explain the concepts of pipeline and interrupts used in ARM processor.
3. Differentiate between RISC and CISC processor.
4. Explain ARM core data flow model with a neat diagram.
5. Discuss briefly how coprocessor can be attached to ARM processor.
6. Explain the AMBA interface with a neat diagram and where is it present in the
architecture ?
7. List out the features of ARM processor.
8. List the features of CISC and RISC processor
9. Write a short note on ARM memory hierarchy.
10. Briefly explain the embedded system software with a neat diagram.
11.Draw and explain the ARM processor model or register set of ARM processor
1. Explain the difference between microprocessor and microcontrollers
2. Explain the difference between CISC and RISC architectures.
3. Explain the ARM design philosophy (Physical features that have driven ARM
processor design).
1 Microprocessors and
4. Explain with a neat diagram, the embedded system hardware based on ARM
core.
5. Write a short notes on i) ARM bus technology ii) AMBA bus protocol iii) Memory
iv) Memory Controller
6. Explain embedded system software( Initialization code, operating system and
applications)
7. Explain with a neat diagram, ARM core data flow model.
8. Briefly explain the seven basic operating modes of ARM core with relevant
diagram. With a neat diagram, explain the register organization of ARM.
9. With a suitable diagram, explain Conditional code flags(CPSR) of ARM RM.
10.Explain the pipeline execution of ARM instructions with an example.
11.Explain the core extensions of ARM with diagrams.


 Fourth Semester BE Degree Examination, June/July 2017

Microprocessor and Microcontroller

Time : 3 hours Max. Marks: 80
Note: Answer any Five full questions, choosing one full question from each
module.
Module - 1

1. (a) Explain execution unit (EU) and Bus Interface Unit (BIU) of 8086 p with a
neat diagram [08 Marks]
(b) Explain the different addressing modes used in 8086 p with suitable
example [08 Marks]
OR
2. (a) Explain all bits of flag register of 8086 p with a neat diagram. Show the
setting and resetting of flag bits with a suitable example. [06 Marks]
(b) Write an assembly level program (ALP) to add two bytes of data stored at data
1 and data 2 and save the result in sum with comments. Identify all the
directives found in the program. [06 Marks]
(c) Show the memory dump for the following data section or data segment.
[04 Marks]
Module - 2

3. (a) Explain Rotate instructions with suitable example. [06 Marks]

(b) With a suitable program show how a packed BCD value is converted to ASCII
value [04 Marks]
(c) Assume that there is a class of five people. With following grades: 69, 87, 96,
45, 75. Write an ALP to find the highest grade [06 Marks]

OR
4. (a) Write on ALP that adds the following two multiword numbers and saves the
result: Data 1 = 548FB9963CE7 and Data 2 = 3FCD4FA23B8DH [08 Marks]
(b) Write an ALP to perform the following:

(i) Clear the screen

(ii) Set the cursor at row

2 Microprocessors and
(iii) Prompt “There is a message for you from VTU: to read it enter Y. If the
user enters „Y‟ or „y‟ then the message “Hello! All the best for your
exams” will appear on the screen. If the user enters any other key, then
the prompt “No more messages for you” should appear on the next line.
[08 Marks]
Module - 3

5. (a) Explain handling of overflow problem arised in addition of signed numbers

with a suitable example. [06 Marks]
(b) Explain XLAT instruction with example [04 Marks]

(c) Explain 74138 decoder configuration to enable the memory address F0000H
to F7FFFH to connect four 8 K RAMS [06 Marks]
OR

6. (a) Briefly explain the control word format of 8255 in I/O mode and BSR mode.
Find the control word if PA = out, PB = in, PC0-PC3 in and PC4-PC7 out. Use
port addresses of 300H-303H for the 8255 chip. Then get data from port B
and send it to part A [08 Marks]
(b) Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH and 52H.

(i) Find the checksum byte

(ii) Perform the checksum operation to ensure data integrity.

(iii) If the second byte 62H had been changed to 22H. Show how checksum
detects the error. [08 Marks]
Module - 4

7. (a) Differentiate between RISC and CISC processors [06 Marks]

(b) Explain ARM core data flow model with a neat diagram [06 Marks]

(c) Discuss briefly how microprocessor can be attached to ARM processor

[04 Marks]
OR

8. (a) Explain the architecture of a embedded device based on ARM core with a
neat diagram [08 Marks]
(b) Explain the concept of pipeline and interrupts used in ARM processor
[08 Marks]
 Examiniation Question 2
Module - 5

9. (a) Explain the following instructions of ARM processor with suitable example
(i) MLA (ii) QADD (iii) SMELL (iv) LSI. [08 Marks]

(b) Write an ALP to copy of data (Block D to another block (Block 2) using ARM
instructions. [04 Marks]
OR

10.(a) Write an ALP using ARM instructions that calls subroutine fact to find the
factorial of a given number. [08 Marks]
(b) Write short notes on memory access and branch instructions of ARM
controller [08 Marks]


2 Microprocessors and

Fourth Semester BE Degree Examination, Dec.2017/Jan.2018

Microprocessor and Microcontroller

Time : 3 hours Max. Marks: 80
Note: Answer any Five full questions, choosing one full question from each
module.
Module - 1

11.(a) Explain the architecture of 8086 microprocessor with a neat diagram along
with functions of various blocks. [06 Marks]
(b) With an example distinguish between physical address, logical address and
offset address. If CS = 2000 h, DS = 3000 h, SS = 4000 h, ES = 5000 h,
BX = 0020 h, BP = 0030 h. Find physical address for (i) MOV AL, [BP]
(ii) MOV CX, [BX] [04 Marks]

(c) Explain the following addressing modes of 8086:

(i) Register indirect

(ii) Based indexed indirect

(iii)Direct memory

OR

12.(a) What are assembler directives? Explain the following assembler directives
(i) PROC, (ii) Assume, (iii) PTR. [04 Marks]
(b) Write assembly language program to add 5 bytes of data stored in data
segment. [04 Marks]
(c) With syntax, explain the following control transfer instructions:
(i) Conditional transfer

(ii) Unconditional transfer instruction [08 Marks]

Module - 2

13.(a) Explain the syntax of following instructions with an example:

(i) DAA (ii) MUL (iii) AND (iv) SHR (v) CMP (vi) AAM

[06 Marks]
 Examiniation Question 2
(b) Write a program to convert lower case to upper case by reading string from
KB and print the converted string at 10 th row, 20th column after clearing the
screen. [06 Marks]
(c) Write an ALP to count the number of one‟s and zero‟s in a given 8 bit data
using rotate instructions. [04 Marks]
OR

14.(a) Explain the syntax of following instructions with example: (i) AAA, (ii) SHL,
(iii) DIV, (iv) RCR. [04 Marks]

(b) What is an interrupt? Explain various types with an interrupt vector table.
[06 Marks]

(c) Write an ALP to sort a given set of 16 bit numbers in ascending order using
any sorting method. [06 Marks]
Module - 3

15.(a) With an example how to identify over flow and under flow using flags in a flag
register for performing arithmetic operation on 16 bit number. [06 Marks]
(b) Write the syntax of following instruction and explain with an example:
(i) CBW, (ii) IDIV, (iii) CMPSB, (iv) Xlat [04 Marks]

(c) Design a memory system for 8086 with one 64 KB RAM and one 64 KB ROM
at address 30000h and F0000h show the complete design along with
memory mapping and draw the final diagram with address decoder.
[06 Marks]

OR

16.(a) With block diagram, explain 8255 and write control word register format for
PA output, PB input in mode 0. [06 Marks]
(b)
Write an ALP to read PB and check number of one‟s in a given 8 bit data at PB
and display FFh on PA if it is even parity else 00h on PA if it is odd parity
[05 Marks]
(c)
Write a program using string instructions to accept a string from keyboard
and check for palindrome and accordingly display appropriate message
[05 Marks]
2 Microprocessors and
Module - 4

17.(a) Compare microprocessor with microcontroller [04 Marks]

(b) Explain the programmer‟s model of ARM processor with complete register
sets available. [04 Marks]
(c) With diagram explain the various blocks in a 3 stage pipeline of ARM
processor organisation. [04 Marks]
(d) Explain registers used under various modes. [04 Marks]

OR

18.(a) Explain the structure of ARM cross development tool kit [06 Marks]

(b) Describe the various modes of operation of ARM processor [05 Marks]
(c) Explain the various fields in Current Program Status Register (CPSR),
[05 Marks]
Module - 5

19.(a) Explain the syntax with example the following instructions of ARM processor
(i) MVN, (ii) RSB, (iii) ORR, (iv) MLA, (v) LDR [05 Marks]

(b) Write a program to display message “Hellow world” using ARM7 processor.
[04 Marks]

(c) Explain various formats of add instructions based on operands of ARM7

processor [04 Marks]

(d) If r5 = 5, r7 = 8 and using the following instruction, write values of r5, r7 after
execution MOV r7, r5, LSL # 2. [03 Marks]

OR

20.(a) Explain software interrupt instruction of ARM processor [04 Marks]

(b) Explain various types of multiply instructions with syntax and example
[04 Marks]

(c) What are the salient features of ARM instruction set? [05 Marks]

(d) If r1 = 0b1111, r2 = 0b0101, find r0 after BIC r0, r1, r2 [03 Marks]
 Examiniation Question 2

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1. The X86 PC Assembly Language, Design Interfacing by Muhammad Ali Mazidi
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