Computer Science 37 Lecture 22
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Alexander TaylorComputer Science 37 Lecture 22
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Alexander TaylorLecture 22
Control Hazards
Time (in clock cycles)
IF
ID
EX
MEM
Visualize: A beq instruction going through the pipeline. Branch: At what pipeline stage can the branch decision be made?
Question: What is going on while the beq is floating towards the MEM stage?
WB
Time (in clock cycles)
beq
IF ID EX MEM WB
Question: Do we have to wait until the beq hits the MEM stage to launch the execution of another instruction in the pipeline?
Ok, so we say that we dont have to wait we assume that the branch is not taken.
Time (in clock cycles) Program execution CC 1 CC 2 order (in instructions) 40 beq $1, $3, 7 IM Reg
CC 3
CC 4
CC 5
CC 6
CC 7
CC 8
CC 9
DM
Reg
44 and $12, $2, $5
IM
Reg
DM
Reg
48 or $13, $6, $2
IM
Reg
DM
Reg
52 add $14, $2, $2
IM
Reg
DM
Reg
72 lw $4, 50($7)
IM
Reg
DM
Reg
The beq reaches MEM and we figure out we want to branch. Interlude: Why do we branch to address 72? Question: What happens to the three instructions that started after the beq?
Assumption: Branch is not taken. true false
Win: We already started the execution of the instructions following the branch. No time was wasted; all stages in the pipeline were kept busy.
Lose: We have to cancel the execution of the three instructions that followed the branch. Three stages wont have done any useful work (three clock cycles wasted). To flush the pipeline, we must set the control bits of the instructions in IF, ID, and EX to 0s.
Question: Do we need extra controls in the pipeline to implement flush? We could reduce the cost of the taken branch by moving the decision to an earlier stage in the pipeline. The optimization calls for two changes: 1) Do branch address calculation right at the ID stage. PC value and immediate can be found in IF/ID, move the branch adder from MEM to ID. 2) Branch decision: Lets not use the ALU. Equality can be tested by XOR-ing the two operands and OR-ing all the bits in the result. We can do this easily in the ID stage. Its much faster than using the ALU, anyway.
IF.Flush
Hazard detection unit M u x M u x
ID/EX
WB Control M EX
EX/MEM
WB M
0 IF/ID
MEM/WB
WB
Shift left 2 M u x
Registers PC Instruction memory
ALU
M u x
Data memory
M u x
Sign extend
M u x Forwarding unit
To flush out an instruction from IF, we can just zero out all the bits in the IF/ID register creating a nop.
Performance: The more the branch is not taken, the more improvement one will observe in this architecture.
The more times the branch is taken, the worst the CPI will be.
Predicting Branches On-the-fly
What happened when this specific branch instruction was last executed? Was the branch taken or not taken?
0x03AF 0x0020 0x1200
Branch History Buffer (beq $t1, $t2, 20) 0 (beq $a0, $t0, 100) 1 (beq $s4, $t3, 123) 0
Extra Memory: Small and Fast
Branch taken last time it executed? Lower bits of instruction address
Question: What if the prediction is wrong?
Optimizing Delayed Branches with Scheduling
a. From before add $s1, $s2, $s3 if $s2 = 0 then Delay slot b. From target sub $t4, $t5, $t6 add $s1, $s2, $s3 if $s1 = 0 then Delay slot sub $t4, $t5, $t6 c. From fall through add $s1, $s2, $s3 if $s1 = 0 then Delay slot
Becomes
Becomes
Becomes add $s1, $s2, $s3
if $s2 = 0 then add $s1, $s2, $s3 add $s1, $s2, $s3 if $s1 = 0 then sub $t4, $t5, $t6
if $s1 = 0 then sub $t4, $t5, $t6
Best choice
2nd best
When is this good?
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Correctness: The optimization can never change the expected behavior of the program.
Performance: If the pipeline is short, an optimization that gains a cycle is big relative improvement. If the pipeline is long, one cycle in many is not such a great improvement.
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Exceptions and Pipelining
We compute the instruction below and discover overflow: add $1, $2, $1 Question: What happens when an exception is detected? Question: What happens to the instructions that I launched before in the pipeline? If exceptions are detected at the end of EX, I need additional controls to flush ID and EX. Complication: we cant allow WriteBack to happen for the offending instruction.
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IF.Flush
Hazard detection unit 40000040 M u x
ID.Flush
EX.Flush
ID/EX
WB Control 0 M u x M 0
M u x M u x
EX/MEM
WB M
MEM/WB
WB
0 EX Cause Except PC
IF/ID
Shift left 2 M u x
Registers PC Instruction memory
ALU
M u x
Data memory
M u x
Sign extend
M u x Forwarding unit
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Superscalar and Dynamic Pipelining
Better performance: Are long pipelines the best we can do? Superscalar: Replicate the stations in the pipeline, so there are n*IF, n*ID, n*EX, n*MEM, n*WB. Launch n instructions into the pipeline every clock cycle. Question: What are the drawbacks?
Dynamic Pipeline Scheduling: Look at instructions down the sequence (past the stall) to start executing sooner.
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