CAEN

Tools for Discovery

n Electronic Instrumentation
DACMa u

UM7788

FELib PHA Parameters User Manual

Description of the FELib Parameters for the PHA Firmware of
Digitizers 2.0
Rev. 5 - November 24th, 2022
Purpose of this User Manual

This document contains the description of the FELib parameters related to the DPP-PHA
firmware of the Digitizer 2.0 series.

Change Document Record

Date Revision Changes
November 10th, 2021 00 Initial release
December 15th, 2021 01 Modified Raw Endpoints section.
January 18th, 2022 02 Modified TempSensAirIn, TempSensAirOut, TempSensCore,
TempSensFirstADC, TempSensLastADC, TempSensHottestADC,
TempSensADC0, TempSensADC1, TempSensADC2, TempSensADC3,
TempSensADC4, TempSensADC5, TempSensADC6, TempSensADC7,
TempSensDCDC parameters description.
July 1st, 2022 03 Modified Introduction and Technical Support. Corrected EnClockOutP0 and
EnClockOutFP description. Modified TimeFilterRiseTimeT,
TimeFilterRiseTimeS, EnergyFilterRiseTimeT, EnergyFilterRiseTimeS,
EnergyFilterFlatTopT, EnergyFilterFlatTopS, EnergyFilterPoleZeroT,
EnergyFilterPoleZeroS, ChRealtimeMonitor, ChDeadtimeMonitor,
GlobalTriggerSource description. Added parameters ADCToVolts,
EnStatEvents, ITLAPolarity, ITLBPolarity, ITLConnect, ChTriggerCnt,
ChSavedEventCnt, ChWaveCnt. Removed some not yet implemented
parameters. Modified Raw Endpoints description. Updated back cover page.
September 15th, 2022 04 Modified max value of EnergyFilterPileUpGuardT, EnergyFilterPileUpGuardS
parameters. Modified description of the parameters WaveAnalogProbe0
and WaveAnalogProbe1 and WaveDigitalProbe0, WaveDigitalProbe1,
WaveDigitalProbe2, WaveDigitalProbe3. Corrected some parameters name
typos.
November 24th, 2022 05 Corrected LVDSMode parameter and Decoded Endpoints description.

Symbols, Abbreviated Terms, and Notations

ADC Analog to Digital Converter
DAQ Data Acquisition
DAW Dynamic Acquisition Window
DPP Digital Pulse Processing
GPO General Purpose Output
LVDS Low-voltage Differential Signaling
PCB Printed Board Circuit
PHA Pulse Height Analysis
PSD Pulse Shape Discrimination
PUC Product Unlock Code
TTT Trigger Time Tag
ZLE Zero Length Encoding

Reference Documents
[RD1] DS7783 – 2740/2745 Digitizer Data Sheet
[RD2] GD7897 – 2740/2745 Digitizers User Guide
https://www.caen.it/support-services/documentation-area/
Manufacturer Contact
CAEN S.p.A.
Via Vetraia, 11 55049 Viareggio (LU) - ITALY
Tel. +39.0584.388.398 Fax +39.0584.388.959
www.caen.it | info@caen.it
© CAEN SpA – 2022
Limitation of Responsibility
If the warnings contained in this manual are not followed, Caen will not be responsible for damage caused by improper
use of the device. The manufacturer declines all responsibility for damage resulting from failure to comply with the
instructions for use of the product. The equipment must be used as described in the user manual, with particular regard
to the intended use, using only accessories as specified by the manufacturer. No modification or repair can be
performed.

Disclaimer
No part of this manual may be reproduced in any form or by any means, electronic, mechanical, recording, or otherwise,
without the prior written permission of CAEN spa.
The information contained herein has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies. CAEN spa reserves the right to modify its products specifications without giving any notice;
for up to date information please visit www.caen.it.
MADE IN ITALY: We remark that all our boards have been designed and assembled in Italy. In a challenging environment
where a competitive edge is often obtained at the cost of lower wages and declining working conditions, we proudly
acknowledge that all those who participated in the production and distribution process of our devices were reasonably
paid and worked in a safe environment (this is true for the boards marked "MADE IN ITALY", while we cannot guarantee
for third-party manufactures).
 CAEN Electronic Instrumentation

Index
Purpose of this User Manual ...................................................................................................................... 2
Change Document Record .......................................................................................................................... 2
Symbols, Abbreviated Terms, and Notations .......................................................................................... 2
Reference Documents.................................................................................................................................. 2
Manufacturer Contact .................................................................................................................................. 3
Limitation of Responsibility ........................................................................................................................ 4
Index ........................................................................................................................................ 5
Figures ..................................................................................................................................... 7
1 Introduction ..................................................................................................................... 8
2 Parameters .................................................................................................................... 10
2.1 Digitizer general parameters ........................................................................................................10
2.1.1 CupVer ..................................................................................................................................................................10
2.1.2 FPGA_FwVer .......................................................................................................................................................10
2.1.3 FwType .................................................................................................................................................................10
2.1.4 ModelCode ...........................................................................................................................................................10
2.1.5 PBCode ................................................................................................................................................................10
2.1.6 ModelName ..........................................................................................................................................................11
2.1.7 FormFactor ...........................................................................................................................................................11
2.1.8 FamilyCode ..........................................................................................................................................................11
2.1.9 SerialNum .............................................................................................................................................................11
2.1.10 PCBrev_MB ....................................................................................................................................................11
2.1.11 PCBrev_PB .....................................................................................................................................................11
2.1.12 License ............................................................................................................................................................12
2.1.13 LicenseStatus .................................................................................................................................................12
2.1.14 LicenseRemainingTime.................................................................................................................................12
2.1.15 NumCh ............................................................................................................................................................12
2.1.16 ADC_Nbit ........................................................................................................................................................12
2.1.17 ADC_SamplRate ............................................................................................................................................12
2.1.18 InputRange .....................................................................................................................................................13
2.1.19 InputType ........................................................................................................................................................13
2.1.20 Zin ....................................................................................................................................................................13
2.1.21 IPAddress, Netmask, Gateway ....................................................................................................................13
2.1.22 ClockSource ...................................................................................................................................................13
2.1.23 EnClockOutP0 ................................................................................................................................................13
2.1.24 EnClockOutFP ................................................................................................................................................14
2.2 Acquistion, Trigger and VETO parameters ................................................................................15
2.2.1 StartSource ..........................................................................................................................................................15
2.2.2 GlobalTriggerSource ...........................................................................................................................................15
2.2.3 WaveTriggerSource ............................................................................................................................................16
2.2.4 EventTriggerSource ............................................................................................................................................16
2.2.5 ChannelsTriggerMask ........................................................................................................................................16
2.2.6 WaveSaving .........................................................................................................................................................17
2.2.7 TrgOutMode .........................................................................................................................................................17
2.2.8 GPIOMode ...........................................................................................................................................................17
2.2.9 BusyInSource.......................................................................................................................................................18
2.2.10 SyncOutMode .................................................................................................................................................19
2.2.11 BoardVetoSource ...........................................................................................................................................19
2.2.12 BoardVetoWidth .............................................................................................................................................19
2.2.13 BoardVetoPolarity ..........................................................................................................................................19
2.2.14 ChannelVetoSource.......................................................................................................................................20
2.2.15 ADCVetoWidth ...............................................................................................................................................20
2.2.16 RunDelay.........................................................................................................................................................20
2.2.17 EnAutoDisarmAcq..........................................................................................................................................20
2.2.18 LedStatus ........................................................................................................................................................20
2.2.19 AcquisitionStatus............................................................................................................................................21
2.2.20 MaxRawDataSize ..........................................................................................................................................21
2.2.21 EnDataReduction ...........................................................................................................................................22
2.2.22 EnStatEvents ..................................................................................................................................................22
2.2.23 VolatileClockOutDelay...................................................................................................................................22

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2.2.24 PermanentClockOutDelay ............................................................................................................................22
2.3 Waveform Inspector parameters .................................................................................................23
2.3.1 WaveDataSource ................................................................................................................................................23
2.3.2 ChRecordLengthS, ChRecordLengthT ............................................................................................................23
2.3.3 WaveResolution ..................................................................................................................................................23
2.3.4 WaveAnalogProbe0 and WaveAnalogProbe1 ................................................................................................24
2.3.5 WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2, WaveDigitalProbe3 .................................24
2.3.6 ChPreTriggerS, ChPreTriggerT ........................................................................................................................24
2.4 Service parameter ..........................................................................................................................25
2.4.1 TestPulsePeriod ..................................................................................................................................................25
2.4.2 TestPulseWidth ...................................................................................................................................................25
2.4.3 TestPulseLowLevel .............................................................................................................................................25
2.4.4 TestPulseHighLevel ............................................................................................................................................25
2.4.5 IOlevel ...................................................................................................................................................................25
2.4.6 TempSensAirIn, TempSensAirOut, TempSensCore, TempSensFirstADC, TempSensLastADC,
TempSensHottestADC, TempSensADC0, TempSensADC1, TempSensADC2, TempSensADC3,
TempSensADC4, TempSensADC5, TempSensADC6, TempSensADC7, TempSensDCDC................................26
2.4.7 VInSensDCDC, VOutSensDCDC .....................................................................................................................26
2.4.8 IOutSensDCDC ...................................................................................................................................................26
2.4.9 FreqSensCore .....................................................................................................................................................26
2.4.10 DutyCycleSensDCDC ...................................................................................................................................26
2.4.11 SpeedSensFan1, SpeedSensFan2 .............................................................................................................26
2.4.12 ErrorFlagMask, ErrorFlagDataMask............................................................................................................27
2.4.13 ErrorFlags .......................................................................................................................................................27
2.4.14 BoardReady ....................................................................................................................................................27
2.5 Individual trigger parameters .......................................................................................................28
2.5.1 ITLAMainLogic, ITLBMainLogic ........................................................................................................................28
2.5.2 ITLAMajorityLev, ITLBMajorityLev ....................................................................................................................29
2.5.3 ITLAPairLogic, ITLBPairLogic ...........................................................................................................................29
2.5.4 ITLAPolarity, ITLBPolarity ..................................................................................................................................29
2.5.5 ITLConnect ...........................................................................................................................................................29
2.5.6 ITLAMask, ITLBMask .........................................................................................................................................30
2.5.7 ITLAGateWidth, ITLBGateWidth .......................................................................................................................30
2.6 LVDS parameters ............................................................................................................................31
2.6.1 LVDSMode ...........................................................................................................................................................31
2.6.2 LVDSDirection .....................................................................................................................................................31
2.6.3 LVDSIOReg .........................................................................................................................................................31
2.6.4 LVDSTrgMask .....................................................................................................................................................31
2.7 Front Panel LEMO DAC parameters ............................................................................................33
2.7.1 DACoutMode .......................................................................................................................................................33
2.7.2 DACoutStaticLevel ..............................................................................................................................................33
2.7.3 DACoutChSelect .................................................................................................................................................33
2.8 Input signal conditioning parameters .........................................................................................34
2.8.1 VGAGain (2745 digitizers only) .........................................................................................................................34
2.8.2 EnOffsetCalibration .............................................................................................................................................34
2.8.3 ChEnable ..............................................................................................................................................................34
2.8.4 SelfTrgRate ..........................................................................................................................................................34
2.8.5 ChStatus ...............................................................................................................................................................35
2.8.6 DCOffset ...............................................................................................................................................................35
2.8.7 GainFactor............................................................................................................................................................35
2.8.8 ADCToVolts .........................................................................................................................................................35
2.8.9 TriggerThr .............................................................................................................................................................36
2.8.10 Pulse Polarity ..................................................................................................................................................36
2.9 Event Selection and Coincidence parameters ..........................................................................37
2.9.1 EnergySkimLowDiscriminator............................................................................................................................37
2.9.2 EnergySkimHighDiscriminator ...........................................................................................................................37
2.9.3 EventSelector.......................................................................................................................................................37
2.9.4 WaveSelector.......................................................................................................................................................37
2.9.5 CoincidenceMask ................................................................................................................................................38
2.9.6 AntiCoincidenceMask .........................................................................................................................................38
2.9.7 CoincidenceLengthT, CoincidenceLengthS ....................................................................................................38
2.10 DPP-PHA parameters .....................................................................................................................39
2.10.1 TimeFilterRiseTimeT, TimeFilterRiseTimeS ..............................................................................................39
2.10.2 TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS .........................................................................39

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2.10.3 EnergyFilterRiseTimeT, EnergyFilterRiseTimeS .......................................................................................40
2.10.4 EnergyFilterFlatTopT, EnergyFilterFlatTopS .............................................................................................40
2.10.5 EnergyFilterPeakingPosition ........................................................................................................................40
2.10.6 EnergyFilterPeakingAvg ...............................................................................................................................41
2.10.7 EnergyFilterPoleZeroT, EnergyFilterPoleZeroS ........................................................................................41
2.10.8 EnergyFilterFineGain.....................................................................................................................................41
2.10.9 EnergyFilterLFLimitation ...............................................................................................................................41
2.10.10 EnergyFilterBaselineAvg ...............................................................................................................................42
2.10.11 EnergyFilterBaselineGuardT, EnergyFilterBaselineGuardS ....................................................................42
2.10.12 EnergyFilterPileUpGuardT, EnergyFilterPileUpGuardS ...........................................................................42
2.10.13 Energy_Nbit ....................................................................................................................................................42
2.10.14 ChRealtimeMonitor ........................................................................................................................................42
2.10.15 ChDeadtimeMonitor .......................................................................................................................................43
2.10.16 ChTriggerCnt ..................................................................................................................................................43
2.10.17 ChSavedEventCnt .........................................................................................................................................43
2.10.18 ChWaveCnt.....................................................................................................................................................43
3 Commands .................................................................................................................... 44
3.1 Reset .................................................................................................................................................44
3.2 ClearData ..........................................................................................................................................44
3.3 ArmAcquisition ...............................................................................................................................44
3.4 DisarmAcquisition ..........................................................................................................................44
3.5 SwStartAcquisition .........................................................................................................................44
3.6 SwStopAcquisition .........................................................................................................................44
3.7 SendSWTrigger ...............................................................................................................................44
3.8 ReloadCalibration ...........................................................................................................................44
4 Endpoints ...................................................................................................................... 45
4.1 Parameters .......................................................................................................................................45
4.1.1 ActiveEndpoint .....................................................................................................................................................45
4.2 Raw Endpoints ................................................................................................................................45
4.2.1 Raw .......................................................................................................................................................................45
4.3 Decoded Endpoints ........................................................................................................................48
4.3.1 DPPPHA ...............................................................................................................................................................48
4.3.2 Statistics ...............................................................................................................................................................50
5 Flags............................................................................................................................... 51
5.1 High Priority .....................................................................................................................................51
5.2 Low Priority .....................................................................................................................................51
6 Technical Support ........................................................................................................ 52

Figures
Figure 1: Individual Trigger logic scheme........................................................................................................................................28
Figure 2: Triangular filter working principle scheme ......................................................................................................................39
Figure 3: Energy filter working principle scheme. ..........................................................................................................................40
Figure 4: Energy filter Pole-Zero undercompensation (left) and over compensation (right). ...................................................41
Figure 5: 27xx digitizer general event structure. ............................................................................................................................45
Figure 6: Event aggregate in Individual Trigger Mode. .................................................................................................................46
Figure 7: Start Run event structure. .................................................................................................................................................46
Figure 8: DPP-PHA firmware Raw Data structure. ........................................................................................................................46
Figure 9: Stop Run event structure. .................................................................................................................................................48

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1 Introduction
CAEN Waveform digitizers x27xx introduce a new approach in the access to the firmware parameters with respect to the
previous generation V17xx, DT57xx and N67xx. Indeed, while in the previous generation x17xx the approach was based
on the direct exposition of the single firmware register, the new generation of digitizer provides an abstraction of the
register in the form of library parameters much easier to understand and use.
This new approach is meant to simplify the things for those users that are required to build their own DAQ system and
software and so need to access to the digitizer firmware parameters.
CAENFELib and CAENDig2Lib are the two libraries provided to the user.
Both are downloadable from the CAEN website and includes, in their own installation folder, the related SDK, demo
codes and documentation codes to be used to start user’s custom software development.
CAENFELib can be used to control and acquire data from the new generation CAEN digitizers. This library is just an
interface and does not include support to any digitizer family. In order to use a digitizer, the user must first install the
respective underlying library.
Existing implementation is the CAENDig2Lib (for VX2740 and other second-generation digitizers).

The following manual includes a description of the CAENFELib related to the DPP-PHA firmware and it is structured as
follows.
In the Parameters chapter the description of each single parameter is included in this form:

Parameter name
Level: Mode: Type: UoM: Min: (if present) Max: (if present)
Description of the parameter
Value

Returned value or Allowed values with the corresponding description if required.

Level: indicates the level at which the parameter is applied. It can be Channel (CH), Digitizer (DIG), LVDS or VGA.
Mode: indicates if the parameter is read-only (R) or read/write (R/W).
Type: indicates the parameter type (STRING, NUMBER, ENUM). Type doesn’t correspond to any C-type, all CAENDig2Lib
parameters are float or string.
UoM: indicates the Unity of Measurement of the parameter (if any).
Min: indicates the minimum allowed value (if present)
Max: indicated the maximum allowed value (if present)

The user should note that the CAENFELib, always works with string parameters but then they have to be interpreted in
the proper way according to the Type field.

Parameters must be used in the CAENFELib_Set/GetValue() function with the correct path form:
• For CH parameters: /ch/ChannelNumber/par/ParameteName. Parameters may be set simultaneously in
multiples channels by selecting the interval separated by “..“. E.g. /ch/0..8/par/ParameterName.
• For DIG parameters: /par/ParameterName.
• For LVDS parameters: /lvds/Index/par/ParameteName. Parameters may be set simultaneously in multiples
indexes by selecting the interval separated by “..“. E.g. /lvds/0..3/par/ParameterName. Index is [0,1,2,3].
• For VGA parameters: /vga/Index/par/ParameteName. Parameters may be set simultaneously in multiples
indexes by selecting the interval separated by “..“. E.g. /vga/0..3/par/ParameterName. Index is [0,1,2,3].

In the Commands chapter the description of each single command is included in this form:

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Command name
Level:
Description of the command
Level: indicates the level at which the command is applied. It can be Channel (CH) or Digitizer (DIG).

Commands must be used in the CAENFELib_SendCommand() function with the correct path form:
• For CH commands: /ch/ChannelNumber/cmd/CommandName. Commands may be sent simultaneously to
multiples channel by selecting the interval separated by “..“. E.g. /ch/0..8/cmd/CommandName.
• For DIG commands: /cmd/CommandName.

In the Endpoints chapter the description of each single command is included in this form:

EndPoint name
Description of the EndPoint
Supported Fields
Default Data Format

Supported Fields: indicates which fields are supported, their native type, dimension and description.
Default Data Format: shows the corresponding format.

In the Flags chapter the description of each flag provided by the DPP_PHA firmware as additional event-wise information
is included in this form:

Flag name
Table with flag corresponding bit, name and description.

Future manual releases will include also additional schemes and guidelines about how to correlate the CAENFELib
parameter to implement specific functionalities.

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2 Parameters
2.1 Digitizer general parameters
2.1.1 CupVer
Level: DIG Mode: R Type: STRING
CUP version currently in use in format “YYYYMMDDNN” there YYYY is the year, MM the month, DD the day and NN a
progressive daily index of the release.

Value
E.g “2021101800”

2.1.2 FPGA_FwVer
Level: DIG Mode: R Type: STRING
Build version of the FPGA firmware currently in use.

Value
E.g TBD

2.1.3 FwType
Level: DIG Mode: R Type: ENUM
Firmware type.

Value
Option Description
DPP_PHA DPP PHA firmware
DPP_ZLE DPP ZLE firmware
DPP_PSD DPP PSD firmware
DPP_DAW DPP DAW firmware
DPP_OPEN Open DPP firmware
Scope Scope firmware

2.1.4 ModelCode
Level: DIG Mode: R Type: STRING
CAEN model code.

Value
E.g. WV2740XAAAAA.

2.1.5 PBCode
Level: DIG Mode: R Type: STRING
CAEN piggyback product code.

Value
E.g. WA40BXAAAAAA.

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2.1.6 ModelName
Level: DIG Mode: R Type: STRING
CAEN model name.

Value
E.g. V2740.

2.1.7 FormFactor
Level: DIG Mode: R Type: ENUM
CAEN digitizer form factor.

Value
Option Description
0 VME
1 VME64X
2 DT

2.1.8 FamilyCode
Level: DIG Mode: R Type: NUMBER
CAEN family code. For example, 2740 indicates all versions of the XX2740 (VME, VME64X, desktop, SE/DIFF, etc.).

Value
E.g. 2740

2.1.9 SerialNum
Level: DIG Mode: R Type: STRING
CAEN serial number.

Value
E.g. 12741.

2.1.10 PCBrev_MB
Level: DIG Mode: R Type: NUMBER
PCB Revision of the Mother Board.

Value
E.g. 1

2.1.11 PCBrev_PB
Level: DIG Mode: R Type: NUMBER
PCB Revision of the Piggyback.

Value
E.g. 1

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2.1.12 License
Level: DIG Mode: R Type: STRING
PUC (Product Unlock Code) for DPP firmware.

Value
E.g. 626C40509DD07C7880CEA247.

2.1.13 LicenseStatus
Level: DIG Mode: R Type: STRING
License status. Use web interface to manage the license. See [RD2].

Value
“Licensed” or “Not Licensed”.

2.1.14 LicenseRemainingTime
Level: DIG Mode: R Type: NUMBER UoM: SECONDS
Remaining time to automatic run stop in case of not licensed or invalid license. A reboot is required to start a new
acquisition.

Value
Countdown from 30 minutes.

2.1.15 NumCh
Level: DIG Mode: R Type: NUMBER
Number of input channels.

Value
E.g 64

2.1.16 ADC_Nbit
Level: DIG Mode: R Type: NUMBER
Number of bits of the ADCs.

Value
E.g. 16

2.1.17 ADC_SamplRate
Level: DIG Mode: R Type: NUMBER UoM: MS/s
Sampling rate of the ADCs.

Value
E.g. 125 MS/s

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2.1.18 InputRange
Level: DIG Mode: R Type: NUMBER UoM: Vpp
Input dynamic range.

Value
E.g. 2 (Vpp).

2.1.19 InputType
Level: DIG Mode: R Type: ENUM
Single ended or differential input type.

Value
Option Description
0 Single ended
1 Differential

2.1.20 Zin
Level: DIG Mode: R Type: NUMBER UoM: Ohm
Input impedance in Ohm.

Value
E.g. 50 Ω.

2.1.21 IPAddress, Netmask, Gateway

Level: DIG Mode: R Type: STRING
IPv4 network settings for the ethernet link. Useful to get the ethernet IPv4 when connected by USB.

Value
E.g. IP Address 10.105.252.100, Netmask 255.255.0.0, Gateway 10.105.254.254

2.1.22 ClockSource
Level: DIG Mode: R/W Type: ENUM
This is the source of the system clock. Multiple options are not allowed.

Value
Option Description
Internal Local oscillator, 62.5 MHz
FPClkIn Front Panel Clock input
P0ClkIn Clock from P0 VME backplane (not implemented)
Link Clock recovery from Ethernet or Optical Link (not implemented)
DIPswitchSel Clock source decided by dip switches on the board (not implemented)

2.1.23 EnClockOutP0
Level: DIG Mode: R/W Type: ENUM
Enable clock output on P0 connector for the backplane propagation of the clock. Enable clock output on Front Panel for
the daisy chain propagation of the clock between multiple boards.

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Value
Option Description
True Clock output on the P0 is enabled
False Clock output on the P0 is disabled

2.1.24 EnClockOutFP
Level: DIG Mode: R/W Type: ENUM
Enable clock output on Front Panel for the daisy chain propagation of the clock between multiple boards.

Value
Option Description
True Clock output on the front panel is enabled
False Clock output on the front panel is disabled

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2.2 Acquistion, Trigger and VETO parameters

2.2.1 StartSource
Level: DIG Mode: R/W Type: ENUM
Defines the source for the start of run. Multiple options are allowed, separated by “|”.

Value
Option Description
EncodedClkIn Start from CLK-IN/SYNC connector on the front panel. This is a 4-pin connector
(LVDS signals) used to propagate the reference clock (typ. 62.5 MHz) and a Sync
signal. The rising edge of the Sync starts the acquisition, that lasts until the Sync
returns low (falling edge).
SINlevel Start from SIN (1=run, 0=stop)
SINedge Start from SIN (rising edge = run; stop from SW)
SWcmd Start from SW (see SwStartAcquisition)
LVDS Start from LVDS (see LVDSMode)
P0 Start from P0 (backplane)

2.2.2 GlobalTriggerSource
Level: DIG Mode: R/W Type: ENUM
Defines the source for the Global Trigger, which is the signal that saves the events in the memory buffers. Multiple
options are allowed, separated by “|”.

Value
Option Description
TrgIn Front Panel TRGIN
P0 Trigger from P0 (backplane)
SwTrg Software trigger (see SendSWTrigger)
LVDS LVDS trgin (see LVDSMode)
ITLA Internal Trigger Logic A: combination of channel self-triggers (see ITLAMainLogic, ITLBMainLogic)
ITLB Internal Trigger Logic B: combination of channel self-triggers
ITLA_AND_ITLB Second level Trigger logic making the AND of ITL A and B
ITLA_OR_ITLB Second level Trigger logic making the OR of ITL A and B
EncodedClkIn Encoded CLK-IN trigger (not implemented)
GPIO Front Panel GPIO
TestPulse Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)

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2.2.3 WaveTriggerSource
Level: CH Mode: R/W Type: ENUM
Allows to set the trigger source for the waveform. Setting this parameter means to get an event including the waveform
and the associated time stamp and energy information.

Value
Option Description
ITLB Internal Trigger Logic B can generate a trigger for a waveform
ITLA Internal Trigger Logic A can generate a trigger for a waveform
GlobalTriggerSource Acquisition Trigger Source (the same of the Scope mode) can generate a
trigger for a waveform
TRGIN External TRGIN can generate a trigger for a waveform
ExternalInhibit Inhibit can generate a trigger for a waveform
ADCUnderSaturation ADC Undersaturation can generate a trigger for a waveform
ADCOversaturation ADC Oversaturation can generate a trigger for a waveform
SWTrigger Software Trigger can generate a trigger for a waveform
ChSelfTrigger Channel self-trigger can generate a trigger for a waveform
Ch64Trigger One (or more) channel self-trigger can generate a trigger for a waveform
Disabled No trigger source enabled for the waveform

2.2.4 EventTriggerSource
Level: CH Mode: R/W Type: ENUM
Allows to set the trigger source for a Time-Energy (T-E) event. Setting this parameter means to get an event including
time stamp and energy information.

Value
Option Description
ITLB Internal Trigger Logic B can generate a trigger for a T-E event
ITLA Internal Trigger Logic A can generate a trigger for a T-E event
GlobalTriggerSource Acquisition Trigger Source (the same of the Scope mode) can generate a trigger for for a T-E
event
TRGIN External TRGIN can generate a trigger for a T-E event
SWTrigger Software Trigger can generate a trigger for a T-E event
ChSelfTrigger Channel self-trigger can generate a trigger for a T-E event
Ch64Trigger One (or more) channel self-trigger can generate a trigger for a T-E event
Disabled No trigger source enabled for the T-E event

2.2.5 ChannelsTriggerMask
Level: CH Mode: R/W Type: STRING
Allows to set the mask over 64 bits to generate a channel trigger. It can be used to trigger a channel using a trigger
coming from another channel.
It also allows to set the mask over 64 bits to enable the channel to participate in the coincidence logic defined in
CoincidenceMask and AntiCoincidenceMask.(option Channel64Trg).

Value
64-bit enable mask, each bit representing a channel.

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2.2.6 WaveSaving
Level: CH Mode: R/W Type: ENUM
Allows to save waveforms always or on request only.

Value
Option Description
Always Waveforms are always saved
On Request Waveforms are saved on request

2.2.7 TrgOutMode
Level: DIG Mode: R/W Type: ENUM
Selects the signal that is routed to the TRGOUT output. Multiple options are not allowed.

Value
Option Description
Disabled
TRGIN Propagation of Front Panel TRGIN (TRGOUT is a replica, with some delay, of the
TRGIN signal)
P0 Propagation of P0 trigger (not implemented yet)
SwTrg Software trigger (see SendSWTrigger)
LVDS LVDS trgin (see LVDSMode)
ITLA Internal Trigger Logic A: combination of channel self-triggers (see ITLAMainLogic,
ITLBMainLogic)
ITLB Internal Trigger Logic B: combination of channel self-triggers
ITLA_AND_ITL Second level Trigger logic making the AND of ITL A and B
B
ITLA_OR_ITLB Second level Trigger logic making the OR of ITL A and B
EncodedClkIn Propagation of the Encoded CLK-IN trigger (not implemented yet)
Run Propagation of the RUN signal (acquisition start/stop), before applying the delay
given by the RunDelay parameter.
RefClk Monitor of the 62.5 MHz clock (used for phase alignment)
TestPulse Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)
Busy Busy of the board
Fixed0 0
Fixed1 1
SyncIn SyncIn signal
SIN SIN signal
GPIO GPIO signal
AcceptTrg Accepted Triggers signal
TrgClk Trigger Clock signal

2.2.8 GPIOMode
Level: DIG Mode: R/W Type: ENUM
Select the signal that is routed to the GPIO, when this is used as output. Multiple options are not allowed. The GPIO on
the front panel is a bidirectional signal that can used in three different ways:
1) as independent board output (each board drives its own GPIO)

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2) as a shared input for the boards: the signal is driven high (= 1) or low (= 0) by an external source and connected in
“short circuit” among multiple boards using “T” connectors at the inputs. The GPIO is not internally terminated, thus it
is necessary to put a 50Ω terminator at the end of the line (last “T” of the chain)
3) as a shared bidirectional line, making a “wired OR”. One or more boards can simultaneously drive the signal high (=
1). If no board drives the GPIO, it remains low (= 0). All boards can read back the signal. It is necessary to put a 50Ω
terminator at both ends of the line (first and last “T” of the chain). This mode ca be used to generate, for instance, the
global Busy and Veto logic for multiple boards.

Value
Option Description
Disabled GPIOMode is disabled.
TrgIn Propagation of Front Panel TRGIN (GPIO is a replica, with some delay, of the
TRGIN signal)
P0 Propagation of P0 trigger
SIN Propagation of SIN
LVDS LVDS trgin (see LVDSMode)
ITLA Internal Trigger Logic A: combination of channel self-triggers (see ITLAMainLogic,
ITLBMainLogic)
ITLB Internal Trigger Logic B: combination of channel self-triggers
ITLA_AND_ITL Second level Trigger logic making the AND of ITL A and B
B
ITLA_OR_ITLB Second level Trigger logic making the OR of ITL A and B
EncodedClkIn Propagation of the Encoded CLK-IN trigger (not implemented)
SwTrg Software trigger (see SendSWTrigger)
Run Propagation of RUN
RefClk Monitor of the 62.5 MHz clock (used for phase alignment)
TestPulse Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)
Busy Busy of the board
Fixed0 0
Fixed1 1

2.2.9 BusyInSource
Level: DIG Mode: R/W Type: ENUM
In a multi-board system, it might be necessary to prevent one board to accept a new trigger while another board is full
and thus unable to accept the same trigger. For this reason, each board can generate a Busy signal to notify that it is
unable to get a new trigger. If the busy/veto mechanism has some latency, it is advisable generate the busy slightly
before the digitizer become full. For this purpose, it is possible to assert the busy output when the acquisition memory
reaches a programmable level of occupancy.
The OR of the busy signals is typically used to stop the global trigger. It is possible to get the individual busy signals from
each board and make an external OR logic or connect the boards with cables to propagate the Busy along the chain. Each
board makes an OR between its internal busy and the busy input signal coming from the previous board, thus having a
global Busy at the end of the line. This parameter defines the source of the Busy Input.

Value
Option Description
SIN Busy input from SIN on front panel
GPIO Busy input coming from GPIO on front panel, used as a simple input. It is also
possible to use GPIO as a wired OR (bidirectional), as described in GPIOMode. In
this mode, the Busy line goes high as soon as one board drives it high. All the
boards can read the Busy line and use it as a veto for the trigger (see
BoardVetoSource)
LVDS LVDS trgin (see LVDSMode)

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Option Description
Disabled The Busy is given by the Internal Busy only (Memory full or almost full)

2.2.10 SyncOutMode
Level: DIG Mode: R/W Type: ENUM
In a multi-board system, it can be useful to propagate a synchronous signal together with the clock (to synchronize the
start of the run, for example) on CLK OUT front panel connector [RD1]. This parameter defines which signal must be sent
out. Multiple options are not allowed.

Value
Option Description
Disabled SyncOutMode is disabled
SyncIn SyncIn signal (if provided with clkIn on CLK IN connector [RD1])
TestPulse Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)
IntClk Internal 62.5 MHz clock
Run Propagation of RUN

2.2.11 BoardVetoSource
Level: DIG Mode: R/W Type: ENUM
Defines the source for the Veto, which is the signal that inhibits the acquisition trigger. Multiple options are allowed,
separated by “|”. The VETO signal can be either active high or low, depending on the BoardVetoPolarity parameter.
When active low, it acts as a GATE for the trigger. It is possible to stretch the duration of the VETO by means of the
parameter.

Value
Option Description
SIN SIN on the front panel
LVDS LVDS trgin (see LVDSMode)
GPIO GPIO on the front panel (used as input)
P0 P0 (signal from the backplane)
EncodedClkIn Encoded CLK-IN veto (not implemented)
Disabled VETO is always OFF

2.2.12 BoardVetoWidth
Level: DIG Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 34359738360
Whatever is the source of the VETO signal, it is possible to stretch the duration of the veto up to a given time by means
of a re-triggerable monostable. Expressed in ns. When 0, the monostable is disabled and the veto lasts as long as the
selected source is active.

Value
E.g. 2000 ns

2.2.13 BoardVetoPolarity
Level: DIG Mode: R/W Type: ENUM
Defines the polarity of the Veto.

Value
Option Description
ActiveHigh Veto is active high. The signals acts as an “Inhibit” for the trigger

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Option Description
ActiveLow Veto is active low. The signals acts as a “Gate” the trigger

2.2.14 ChannelVetoSource
Level: CH Mode: R/W Type: ENUM
Allows to set the veto for each channel; it can be external (which means one of the veto options in the previous table),
or it can be on a channel base.

Value
Option Description
BoardVeto Enables board veto
ADCOverSaturation Enables veto due to ADC oversaturation
ADCUnderSaturation Enables veto due to ADC undersaturation
Disabled Any channel veto source is disabled

2.2.15 ADCVetoWidth
Level: CH Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 524280
It is the width of the ADC veto (undersaturation and oversaturation width) expressed in ns.

Value
E.g. 2000 ns

2.2.16 RunDelay
Level: DIG Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 524280
When the start of run is controlled by a RUN signal that is propagated in daisy chain between the boards (for instance
through the ClkIn-ClkOut or SIN-GPIO sync chain), it is necessary to compensate for the propagation delay and let the
boards to start exactly at the same time. The Run Delay parameter allow the start of the acquisition to be delayed by a
given number of clock cycles with respect to the rising edge of the RUN signal. Assuming that the propagation delay is 2
cycles, the RunDelay setting will be 0 for the last board in the chain, 2 for the previous one, and so on up 2*(NB-1) for
the first one.

Value
E.g. 20 ns

2.2.17 EnAutoDisarmAcq
Level: DIG Mode: R/W Type: ENUM
When enabled, the Auto Disarm option disarms the acquisition at the stop of run. When the start of run is controlled by
an external signal, this option prevents the digitizer to restart without the intervention of the software.

Value
Option Description
True The acquisition is automatically disarmed after the stop. It is therefore necessary
to rearm the digitizer (with the relevant command sent by the software) before
starting a new run.
False The acquisition is not disarmed after the stop. Multiple transition of the start
signal will produce multiple runs.

2.2.18 LedStatus
Level: DIG Mode: R Type: STRING
Get a 32-bit word representing the LEDs status of the digitizer.

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Value
Bit Number Name
0 LED_JESD_Y_PASS
1 LED_JESD_H_PASS
2 LED_DDR4_0_PASS
3 LED_DDR4_1_PASS
4 LED_DDR4_2_PASS
5 LEDFP_FAIL
6 LEDFP_NIM
7 LEDFP_TTL
8 LEDFP_DTLOSS
9 LEDFP_DTRDY
10 LEDFP_TRG
11 LEDFP_RUN
12 LEDFP_PLL_LOCK
13 LEDFP_CLKOUT
14 LEDFP_CLKIN
15 LEDFP_USB
16 LEDFP_SFP_SD
17 LEDFP_SFP_ACT
18 LEDFP_ACT
19-31 Not Used

2.2.19 AcquisitionStatus
Level: DIG Mode: R Type: STRING
Get a 32-bit word representing the acquisition status of the digitizer.

Value
Bit Number Name
0 Armed
1 Run
2 Run_mw
3 Jesd_Clk_Valid
4 Busy
5 PreTriggerReady
6 LicenceFail
7-31 Not Used

2.2.20 MaxRawDataSize
Level: DIG Mode: R Type: NUMBER UoM: byte
Maximum size that can be returned from a single call to GetData from the raw endpoint (see Chap. 4). This parameter
should be read at the end of the configuration.

Value
E.g. 2621440 bytes

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2.2.21 EnDataReduction
Level: DIG Mode: R/W Type: STRING
If enabled, events consisting of 2 words are compressed in a single word event.

Value
Option Description
False Data reduction is disabled.
True Data reduction is enabled.

2.2.22 EnStatEvents
Level: DIG Mode: R/W Type: STRING
If enabled, stats events are generated.

Value
Option Description
False Stats event generation is disabled.
True Stats event generation is enabled.

2.2.23 VolatileClockOutDelay
Level: DIG Mode: R/W Type: NUMBER UoM: ps Min: -18888.888 Max: 18888.888
Sets the delay of the clock output with respect to the input reference clock. When the clock is distributed between
multiple boards in daisy chain (typ. through CLKIN-CLKOUT connectors), this option allows for compensation of the
propagation delay and fine alignment of the clock phases. This setting is directly writing into the PLL registers and is not
permanent. Once the good setting has been found, use the parameter PermanentClockOutDelay to store the delay in
the flash memory and automatically reload it at every power-up.

Value
E.g. 148.148 ps.

2.2.24 PermanentClockOutDelay
Level: DIG Mode: R/W Type: NUMBER UoM: ps Min: -18888.888 Max: 18888.888
Sets the EnStatEvents
Level: DIG Mode: R/W Type: STRING
If enabled, stats events are generated.

Value
Option Description
False Stats event generation is disabled.
True Stats event generation is enabled.

VolatileClockOutDelay, stores the value into the filesystem and makes it permanent.
When read, it returns the value of the delay stored in the filesystem, that may differ from the one currently applied, if
volatile. Steps of 74.074 ps

Value
E.g. 148.148 ps.

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2.3 Waveform Inspector parameters

2.3.1 WaveDataSource
Level: CH Mode: R/W Type: ENUM
In normal mode, the acquired waveform represents a sequence of ADC samples, resulting from the A/D conversion of
the analog input. For test purposes, it is possible to replace the ADC data with internal data generators.ù

Value
Option Description
ADC_DATA Data from the ADC (normal operating mode)
ADC_TEST_TOGGLE Set the ADC to produce a Toggle signal
ADC_TEST_RAMP Set the ADC to produce a Ramp signal
ADC_TEST_SIN Set the ADC to produce a Sinusoidal signal
IPE (not implemented)
Ramp Data from a ramp generator (16 bit: 6 most significant bit for the channel
codification + 10 bit for the Ramp signal)
SquareWave Internal Test Pulse (see TestPulsePeriod and TestPulseWidth)
ADC_TEST_PRBS

2.3.2 ChRecordLengthS, ChRecordLengthT

Level: CH Mode: R/W Type: NUMBER UoM: sample/ns Min: 4/32 Max: 8100/64800
The waveform size. Integer representing the number of samples (“S” option) or the time in ns (“T” option). The actual
size of the waveform will be automatically rounded to the closest allowed value. It is possible to get the exact size by
reading back the parameter. The record length in time depends on wave resolution.

Value
E.g. 32000

2.3.3 WaveResolution
Level: CH Mode: R/W Type: ENUM
Allows to set the waveform resolution.

Value
Option Description
Res8 8ns
Res16 16ns
Res32 32ns
Res64 64ns

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2.3.4 WaveAnalogProbe0 and WaveAnalogProbe1

Level: CH Mode: R/W Type: ENUM
Allows to set the analog signal for the analog probe 0 and 1.

Value
Option Description
ADCInput, ADC input probe
TimeFilter Time Filter probe
EnergyFilter Energy Filter probe
EnergyFilterBaseline Energy Filter Baseline
EnergyFilterMinusBaseline [Energy Filter – Baseline] probe

2.3.5 WaveDigitalProbe0, WaveDigitalProbe1, WaveDigitalProbe2,

WaveDigitalProbe3
Level: CH Mode: R/W Type: ENUM
Allows to select the logical signal for digital probe 0, 1, 2 and 3.

Value
Option Description
Trigger Trigger probe
TimeFilterArmed Time Filter Armed probe
ReTriggerGaurd ReTrigger Guard probe
EnergyFilterBaselineFreeze Energy Filter Baseline Freeze probe
EnergyFilterPeaking Energy Filter Peaking probe
EnergyFilterPeakReady Energy Filter Peak Ready probe
EnergyFilterPileUpGuard Energy Filter Pile Up Guard probe
EventPileUp Event Pile Up probe
ADCSaturation ADC Saturation probe
ADCSaturationProtection ADC Saturation Protection probe
PostSaturationEvent Post Saturation Event probe
EnergyFilterSaturation Energy Filter Saturation probe
AcquisitionInhibit Acquisition Inhibit probe

2.3.6 ChPreTriggerS, ChPreTriggerT

Level: CH Mode: R/W Type: NUMBER UoM: sample/ns Min: 4/32 Max: 4000/32000
Number of samples coming before the position of the trigger in the waveform (i.e. size of the pre-trigger window).

Value
E.g. 800/3200.

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2.4 Service parameter

2.4.1 TestPulsePeriod
Level: DIG Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 34359738360
The Test Pulse is a programmable square wave that can be used as an internal periodic trigger (mainly for test purposes)
or to generate a logic test pulse (TTL or NIM) on the TRGOUT and GPIO outputs. The actual value will be rounded to 8 ns.

Value
E.g 1000 ns.

2.4.2 TestPulseWidth
Level: DIG Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 34359738360
Width (i.e. the time the signal stays high = 1) of the test pulse in nanoseconds (ns). The actual value will be rounded to 8
ns. See TestPulsePeriod.

Value
E.g 1000 ns.

2.4.3 TestPulseLowLevel
Level: DIG Mode: R/W Type: NUMBER UoM: ADC counts Min: 0 Max: 65535
Low level of the test pulse. See TestPulsePeriod.

Value
E.g. 0.

2.4.4 TestPulseHighLevel
Level: DIG Mode: R/W Type: NUMBER UoM: ADC counts Min: 0 Max: 65535
High level of the test pulse. See TestPulsePeriod.

Value
E.g. 10000.

2.4.5 IOlevel
Level: DIG Mode: R/W Type: ENUM
Sets the electrical logic level of the LEMO I/Os (TRGIN, SIN, TRGOUT, GPIO). NOTE: TRGIN and SIN are 50 Ω terminated,
GPIO and TRGOUT require 50 Ω termination at the receiver.

Value
Option Description
NIM NIM logic (0=0V, 1=-0.8V, that is -16mA)
TTL Low Voltage TLL logic (0=0V, 1=3.3V)

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2.4.6 TempSensAirIn, TempSensAirOut, TempSensCore, TempSensFirstADC,

TempSensLastADC, TempSensHottestADC, TempSensADC0,
TempSensADC1, TempSensADC2, TempSensADC3, TempSensADC4,
TempSensADC5, TempSensADC6, TempSensADC7, TempSensDCDC
Level: DIG Mode: R Type: NUMBER Units: Celsius degrees Min: 0 Max: null
Various sensors monitoring the temperature of the incoming (TempSensAirIn) and outcoming (TemSensAirOut) air flow
of the board, at the FPGA core (TempSensCore), at the first, the last and the ottest ADC component (TempSensFirstADC,
TempSensLastADC, TempSensHottestADC), at the ADC sensors (TempSensADC0, TempSensADC1, TempSensADC2,
TempSensADC3, TempSensADC4, TempSensADC5, TempSensADC6, TempSensADC7), and at the DC-DC converter
(TempSensDCDC). The resolution is 0.1 °C.

Value
E.g. 40.7 (°C).

2.4.7 VInSensDCDC, VOutSensDCDC

Level: DIG Mode: R Type: NUMBER Units: Volts Min: 0 Max: null
Sensors monitoring the input and output voltage of the DC-DC converter. The resolution is 0.001 V

Value
E.g. 4.997 (V).

2.4.8 IOutSensDCDC
Level: DIG Mode: R Type: NUMBER Units: Ampere Min: 0 Max: null
Sensor monitoring the DC-DC converter current. The resolution is 0.001 A.

Value
E.g. 7.570 (A).

2.4.9 FreqSensCore
Level: DIG Mode: R Type: NUMBER Units: Hertz Min: 0 Max: null
Frequency of the DCDC converter. The resolution is 0.1 Hz.

Value
E.g. 800 (Hz).

2.4.10 DutyCycleSensDCDC
Level: DIG Mode: R Type: NUMBER Units: Percentage Min: 0 Max: null
Duty cycle of the DCDC converter. The resolution is 0.1 %.

Value
E.g. 14.8 (%).

2.4.11 SpeedSensFan1, SpeedSensFan2

Level: DIG Mode: R Type: NUMBER Units: Rpm Min: 0 Max: null
Sensors monitoring the fan speed (desktop modules only). The resolution is 1 rpm.

Value
E.g. 2700 (rpm).

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2.4.12 ErrorFlagMask, ErrorFlagDataMask

Level: DIG Mode: R/W Type: STRING
There are several error sources in the digitizer, mainly coming from the internal health monitoring system (temperature,
current, etc..), but also from FPGA data consistency checking and others. All these errors can be combined into a error
flag mask through a masked OR, programmed by this parameter. The ErrorFlagMask drives the relevant LED on the front
panel, while ErrorFlagDataMask drives the error flag bit in the event.

Value
32-bit integer, where each bit meaning is explained in the table below. Other bits currently unused.

Bit Description
0 power_fail
1 board_init_fault
2 si5341_unlock
3 si5395_unlock
4 LMK04832_unlock
5 jesd_unlock
6 ddr_pl_bank0_calib_fail
7 ddr_pl_bank1_calib_fail
8 ddr_ps_calib_fail
9 fpga_config_fail
10 bic_error
11 adc_overtemp
12 air_overtemp
13 fpga_overtemp
14 dcdc_overtemp
15 clkin_miss
16 adc_shutdown

2.4.13 ErrorFlags
Level: DIG Mode: R Type: STRING
Reads the status of the error flags.

Value
See ErrorFlagMask, ErrorFlagDataMask fields.

2.4.14 BoardReady
Level: DIG Mode: R Type: ENUM
Check if there is any error set in ErrorFlags.

Value
Option Description
True True means ErrorFlags is zero
False Otherwise

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2.5 Individual trigger parameters

2.5.1 ITLAMainLogic, ITLBMainLogic
Level: DIG Mode: R/W Type: ENUM
Each channel of the digitizer feature a digital bipolar triangular filter discriminator with programmable rise time and
threshold (see TimeFilterRiseTimeT, TimeFilterRiseTimeS and TriggerThr) able to self-trigger on the input pulses and
generate a self-trigger signal. In PHA Mode, the channels acquire independently, so the channel self-trigger is used locally
to acquire a waveform. The trigger threshold is then referred to the bipolar triangular filter, and the threshold crossing
arms the event selection. The trigger fires at the zero crossing of the time filter signal. The user can see the derivative
trace on the signal inspector.
It is also possible to combine all the self-triggers of the board (64 lines in the case of the V2740), according to a specific
trigger logic. There are two independent logic blocks, ITLA and ITLB. Their output can be used separately to feed, for
instance, AcqTrigger and TrgOut, or combined in a second level trigger logic to implement more complex trigger schemes
(see GlobalTriggerSource and TrgOutMode). Therefore, the ITLs can either generate the local acquisition trigger,
common to all the channels, for the acquisition of the waveform, or propagate the signal outside, through the TRGOUT,
thus making it possible to combine triggers of multiple boards in an external trigger logic, that eventually feeds back the
TRGIN of the digitizers.
Each ITL is made of an input enable mask (64 bits, one per channel), an optional pairing logic that combines the self-
triggers of two consecutive channels (e.g. paired coincidence) and the main trigger logic that combines the 64 self-
triggers with an OR, AND or Majority logic. The output can be linear (no stretching) or reshaped by a programmable gate
generator, either re-triggerable or not and finally programmed for polarity (direct or inverted).
ITL Mask: 64 bit

PairMode: AND, OR, NONE

ITL Mode: AND, OR, MAJ

SELF-TRG[0]
PAIR
LOGIC
SELF-TRG[1]

Width in ns (0 = Linear)
SELF-TRG[2]
Retriggerable: True, False
PAIR
LOGIC Polarity: DIRECT, INVERTED
SELF-TRG[3]
ENABLE MASK

MAIN
ITLOUT
TRG GATE POLARITY
LOGIC

SELF-TRG[62]
PAIR
SELF-TRG[63] LOGIC

Figure 1: Individual Trigger logic scheme.

Value
Option Description
OR ITLOUT = masked OR of channel self-triggers
AND ITLOUT = masked AND of channel self-triggers
Majority ITLOUT = masked Majority of channel self-triggers

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2.5.2 ITLAMajorityLev, ITLBMajorityLev

Level: DIG Mode: R/W Type: NUMBER UoM: units Min: 1 Max: 63
Defines the majority level of the Main Logic of the ITL A and B. The majority output is calculated at every clock cycle and
it becomes TRUE when Nch >= MajLev, where Nch is the number of self-triggers active in that clock cycles and MajLev is
the programmed majority level. NOTE: when the Pair Logic is used to combine the self-triggers two by two (AND/OR),
each pair produces two identical signals that will be counted twice in the majority level

Value
E.g 10.

2.5.3 ITLAPairLogic, ITLBPairLogic

Level: DIG Mode: R/W Type: ENUM
Pairs of channels can be combined with an OR or AND before feeding the Main trigger Logic. When the AND/OR logic is
applied, the two outputs of the Pair Logic blocks are identical. Please note that they are counted twice in the following
Majority logic. If the Pair Logic is disabled (option “NONE”), the block is transparent, and the two outputs are just a
replica of the inputs.

Value
Option Description
OR Both Pair Logic Outputs = OR of two consecutive self-triggers
AND Both Pair Logic Outputs = AND of two consecutive self-triggers
NONE Outputs = Inputs

2.5.4 ITLAPolarity, ITLBPolarity

Level: DIG Mode: R/W Type: ENUM
Polarity of ITLA/ITLB.

Value
Option Description
Direct Polarity of the ITLA/ITLB is Direct
Inverted Polarity of the ITLA/ITLB is Inverted

2.5.5 ITLConnect
Level: CH Mode: R/W Type: STRING Index:[0:63]
Alternative to ITLAMask, ITLBMask. Determines if the channel partecipate in ITLA or ITLB.

Value
Option Description
Disabled The channel is disabled.
ITLA The channel participates in ITLA logic block.
ITLB The channel participates in ITLB logic block.

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2.5.6 ITLAMask, ITLBMask

Level: DIG Mode: R/W Type: STRING
Enable Mask at the input of the ITLA/ITLB. The user should pay attention to the fact that the use of this parameter
overwrites the ITLConnect settings. The two cannot be used at the same time.

Value
64-bit enable mask, each bit representing a channel.

2.5.7 ITLAGateWidth, ITLBGateWidth

Level: DIG Mode: R/W Type: NUMBER UoM: ns Min: 0 Max: 524280
Width of the gate generator at the output of the ITLs. Steps of 8 ns.

Value
E.g 1000 ns

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2.6 LVDS parameters

2.6.1 LVDSMode
Level: LVDS Mode: R/W Type: ENUM
The digitizer has 16 LVDS I/Os that can be programmed to be inputs or outputs in groups of 4 (quartets), depending on
the parameter LVDSDirection). Once the direction has been selected, it is possible to select the functionality of the LVDS
lines, individually for each quartet.

Value
Option Description
SelfTriggers Each LVDS line can be assigned to a combination of the 64 self-triggers,
implemented as a masked OR, where the mask is set by the parameter
LVDSTrgMask (16 independent masks, one per LVDS line)
Sync Whatever is the direction of the quartet, the 4 lines are rigidly assigned to
specific acquisition signals:
0=Busy; 1=Veto; 2=Trigger; 3=Run
It is possible to implement a daisy chain distribution of these signals using one
quartet as input and another one as output
IORegister The LVDS lines of the quartet are statically controlled by the parameter
LVDSIOReg. Use the SetValue function to set the relevant LVDS lines when
programmed as output. Use GetValue to read the status of the LVDS lines when
programmed as inputs.

2.6.2 LVDSDirection
Level: LVDS Mode: R/W Type: ENUM
Assigns the direction of a quartet of LVDS I/Os.

Value
Option Description
Input The LVDS lines of the relevant quartet are used as input. The relevant LED on the
front panel is OFF
Output The LVDS lines of the relevant quartet are used as output. The relevant LED on
the front panel lights-up.

2.6.3 LVDSIOReg
Level: DIG Mode: R/W Type: STRING
Set the status of the LVDS I/O for the quartets that are programmed to be output and Mode = IORegister.

Value
16-bit value representing the status of the LVDS I/Os (either for writing or reading).

2.6.4 LVDSTrgMask
Level: DIG Mode: R/W Type: STRING
Each LVDS line can be assigned to a combination of the 64 self-triggers, implemented as a masked OR, where the mask
is set by this parameter. There are 16 independent masks, one per LVDS line. NOTE: the trigger mask assignment does
not imply the LVDS direction and mode settings. It is therefore necessary to set the Direction = Output and Mode =
SelfTriggers to use the Self-Trigger propagation to the LVDS I/Os.

Value
64-bit enable mask, each bit representing a channel.

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Each independent mask can be set using a string in the format "<mask ID in the range [0, 15]>=<64-bit integer>" as value.
Integers are internally parsed using C++ std::stoul, so you can use 0x prefix for hexadecimal or 0 for octal.
For example:
CAEN_FELib_SetValue(root_handle, "/par/lvdstrgmask", "7=0xf0f0f0f0f0f0f0f0");
Each independent mask can be get by writing the mask ID in the value string that is passed to the CAEN_FELib_GetValue,
and the function will overwrite it with the value.
For example:
char value[256] = "7";
CAEN_FELib_GetValue(root_handle, "/par/lvdstrgmask", value);

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2.7 Front Panel LEMO DAC parameters

2.7.1 DACoutMode
Level: DIG Mode: R/W Type: ENUM
Select the signal type to be sent in output on the front panel DAC connector.

Value
Option Description
Static DAC output stays at a fixed level, given by the parameter DACoutStaticLevel
IPE (not implemented)
ChInput The DAC reproduces the input signal received by one input channel, selected by
the parameter DACoutChSelect
MemOccupancy Level of the memory occupancy (not yet implemented)
ChSum The DAC reproduces the “analog” sum of the of all the digitizer inputs.
OverThrSum The DAC output is proportional to the number of channels that are currently
above the threshold
Ramp The DAC output is driven by a 14-bit counter
Sin5MHz The DAC output is a sine wave at 5 MHz with fixed amplitude
Square Square wave with period and width set by TestPulsePeriod and TestPulseWidth
and amplitude between TestPulseLowLevel and TestPulseHighLevel.

2.7.2 DACoutStaticLevel
Level: DIG Mode: R/W Type: NUMBER UoM: units Min: 0 Max 16383
When the DACoutMode = Static, the DAC generates a static output.

Value
E.g 1000

2.7.3 DACoutChSelect
Level: DIG Mode: R/W Type: NUMBER UoM: units Min: 0 Max 63
When the DACoutMode = ChInput, the DAC reproduces the inputs signal received by a selected channel.

Value
Selected channel index.

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2.8 Input signal conditioning parameters

2.8.1 VGAGain (2745 digitizers only)
Level: VGA Mode: R/W Type: NUMBER Index: [0, 1, 2, 3] UoM: dB Min: 0 Max: 40
Sets the gain of the Variable Gain Amplifiers (VGA) in steps of 0.5 dB. The gain is set commonly to a group of 16 channels
depending on the Index: Index[0] means CH0-CH15.

Value
E.g. 1 (dB).

2.8.2 EnOffsetCalibration
Level: DIG Mode: R/W Type: ENUM
The input DCoffset that determines the position of the signal baseline (zero volt) is controlled by individual channel DACs.
Due to the tolerance of the components, there is some spread in the offset setting that is compensated by the offset
calibration. This is normally enabled and automatically applied in the firmware of the board. The calibration can be
disabled, mainly when a new calibration has to be calculated.

Value
Option Description
True DC offset calibration is applied (default)
False DC offset calibration is not applied

2.8.3 ChEnable
Level: CH Mode: R/W Type: ENUM
Allows to enable/disable a channel. If the Run is already set, ch_enable starts the acquisition.

Value
Option Description
True The channel is enabled for the acquisition
False The channel is disabled for the acquisition

2.8.4 SelfTrgRate
Level: CH Mode: R Type: NUMBER
Each channel has a 32-bit counter permanently connected to its self-trigger. This parameter allows to read the channel
self-trigger rate in Hertz (Hz).

Value
Eg. 1000 Hz.

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2.8.5 ChStatus
Level: CH Mode: R Type: ENUM
Gets a 32-bit word representing the status of the acquisition.

Value
Bit Description
0 Channel signal delay initialization status (1 = initial delay done)
1 Channel time filter initialization status (1 = time filter initialization done)
2 Channel energy filter initialization status (1 = energy filter initialization done)
3 Channel full initialization status (1 = initialization done)
4 Reserved
5 Channel enable acquisition status (1 = acq enabled)
6 Channel inner run status (1 = run active)
7 Time-energy event free space status (1 = time-energy can be written)
8 Waveform event free space status (1 = waveform can be written)
9 : 31 Not used

2.8.6 DCOffset
Level: CH Mode: R/W Type: NUMBER UoM: percentage Min: 0 Max: 100
A constant DC offset (controlled by a 16-bit DAC) is added to the analog input, individually for each channel, in order to
adjust the position of the signal baseline (that is the “zero volt” of the analog input) within the dynamic range of the ADC.
Because of the tolerance of the components, it is necessary to calibrate the offset DAC. The calibration is done by factory
testing and normally it is not necessary to recalibrate the digitizer. It is however possible to perform a new calibration.
The calibration parameters are stored in the flash memory of the board and loaded at power on. They are automatically
applied by the internal logic every time the parameter DCoffset is written or read. DCoffset expressed as a float number,
in percent of the full scale. When the DC offset is 0, the baseline of the input signal is at 0 ADC counts. When the DC
offset is 100, the baseline of the input signal is at 2NBIT-1 ADC counts.

Value
E.g 50 %.

2.8.7 GainFactor
Level: CH Mode: R
Read the gain ADC calibration value stored in the internal flash. This value can be used by the user in its own DAQ
software to calibrate the ADC and provide the signal amplitude value in mV units.

Value
E.g 1.010591

2.8.8 ADCToVolts
Level: CH Mode: R Type: NUMBER UoM: Volts
Factor to convert ADC counts to volts. It is a more sophisticated version of the inverse of GainFactor and takes into
account also the value of VGAGain (2745 digitizers only). While GainFactor is a fixed value, ADCToVolts provides the
current value to be applied to convert ADC into Volts.

Value
E.g 0.000031

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2.8.9 TriggerThr
Level: CH Mode: R/W Type: NUMBER UoM: units Min: 0 Max 8191
Each channel of the digitizer features a digital triangular fast filter discriminator with programmable rise time (see
TimeFilterRiseTimeT, TimeFilterRiseTimeS) and threshold able to self-trigger on the input pulses and generate a self-
trigger signal feeding the internal trigger logics or digitizer outputs. This parameter sets the trigger threshold. The trigger
threshold is then referred to the bipolar triangular signal itself, and the threshold crossing arms the event selection. The
trigger fires at the zero crossing of the bipolar signal. The user can see the bipolar trace on the signal inspector. Threshold
value in counts is referred to the Time Filter. It is a 13-bit signed number.

Value
E.g 52.

2.8.10 Pulse Polarity

Level: CH Mode: R/W Type: ENUM
Allows to set the polarity of the input pulse.

Value
Option Description
Positive Positive polarity
Negative Negative polarity

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2.9 Event Selection and Coincidence parameters

2.9.1 EnergySkimLowDiscriminator
Level: CH Mode: R/W Type: NUMBER UoM: units Min: 0 Max 65534
Allows to flag events with energy higher than the low skim threshold. 16-bit value.

Value
E.g. 1000.

2.9.2 EnergySkimHighDiscriminator
Level: CH Mode: R/W Type: NUMBER UoM: units Min: 0 Max 65534
Allows to flag events with energy lower than the high skim threshold. 16-bit value.

Value
E.g 2000.

2.9.3 EventSelector
Level: CH Mode: R/W Type: ENUM
Allows to set which events have to be saved.

Value
Option Description
All All events are saved
Pileup Only pileup events are saved
EnergySkim Save only the events in the Energy skim range

2.9.4 WaveSelector
Level: CH Mode: R/W Type: ENUM
Allows to set which waveform have to be saved.

Value
Option Description
All All waves are saved
Pileup Only pileup waves are saved
EnergySkim Save only waves in the EnergySkim range

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2.9.5 CoincidenceMask
Level: CH Mode: R/W Type: ENUM
Allows to set the coincidence mask that generates a trigger on the specified channel.

Value
Option Description
Disabled All the coincidence sources are disabled
Ch64Trigger One of the 64 channels can generate a coincidence signal
TRGIN TRGIN can generate a coincidence signal
GlobalTriggerSource Acquisition Trigger can generate a coincidence signal
ITLA ITLA can generate a coincidence signal
ITLB ITLB can generate a coincidence signal

2.9.6 AntiCoincidenceMask
Level: CH Mode: R/W Type: ENUM
Allows to set the anticoincidence mask that generates a trigger on the specified channel.

Value
Option Description
Disabled All the anticoincidence sources are disabled
Ch64Trigger One of the 64 channels can generate an anticoincidence signal
TRGIN TRGIN can generate an anticoincidence signal
GlobalTriggerSource Acquisition Trigger can generate an anticoincidence signal
ITLA ITLA can generate an anticoincidence signal
ITLB ITLB can generate an anticoincidence signal

2.9.7 CoincidenceLengthT, CoincidenceLengthS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 8/1 Max: 524280/65535
Coincidence window length in nanoseconds (ns) or samples (S). 16-bit value.

Value
E.g 800 ns/100 samples.

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2.10 DPP-PHA parameters

2.10.1 TimeFilterRiseTimeT, TimeFilterRiseTimeS
Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 32/4 Max: 2000/250
The x27xx digitizer running the DPP_PHA firmware discriminates events based on a triangular signal, whose rise time
can be defined by the user in the range 0.08 to 2 μs. The TriggerThrshold is then referred to the derivative of the triangle
itself, and the threshold crossing arms the event selection.

Figure 2: Triangular filter working principle scheme

The trigger fires at the zero crossing of the derivative signal itself. This parameter allows to set the rise time of the time
filter (in ns or samples). 8-bit value.

Value
E.g. 400 ns/50 samples.

2.10.2 TimeFilterRetriggerGuardT, TimeFilterRetriggerGuardS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 0/0 Max: 8000/1000
In case of fast signal such as those coming from PMTs possible overshoots in the fast discriminator signal may occur
causing a retrigger and so possible fake pile-up. This parameter allows to set a retrigger inhibit guard (in ns or samples).
10-bit value in steps of 8 ns/1 sample.

Value
E.g 2000 ns/250 samples.

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2.10.3 EnergyFilterRiseTimeT, EnergyFilterRiseTimeS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 32/4 Max: 13000/1625
The digitizer x27xx running the DPP-PHA firmware evaluates the energy value using a Trapezoidal filter. As in the
traditional analog chain, the Shaping Amplifier is able to convert the exponential shape from the Charge Sensitive
Preamplifier into a Gaussian shape whose height is proportional to the pulse energy, in the same way the Trapezoidal
filter is able to transform it into a trapezoidal signal whose amplitude is proportional to the input pulse height (energy).
In this analogy, the Energy Filter Rise Time corresponds to the Shaping Time times a factor of 2/2.5.

Figure 3: Energy filter working principle scheme.

This parameter allows to set the trapezoid rise time (in ns or samples). 11-bit value.

Value
E.g 8000 ns/1000 samples.

2.10.4 EnergyFilterFlatTopT, EnergyFilterFlatTopS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 32/4 Max: 3000/375
The energy value of the input pulse is evaluated as the height of the trapezoid in its Flat Top region. The user must take
care that the flat top is really flat and that the Peaking (i.e. the samples used for the energy calculation) is in the flat
region. Moreover the correct setting of flat top and peaking helps in the correct evaluation of the energy especially when
large volume detectors are involved and the ballistic deficit may cause a significant error in the energy calculation. In this
case it may be convenient to increase the flat top duration and delay the peaking time to wait for the full charge
collection. This parameter allows to set the trapezoid flat top (in ns or samples). 9-bit value.

Value
E.g 2000 ns/250 samples.

2.10.5 EnergyFilterPeakingPosition
Level: CH Mode: R/W Type: NUMBER UoM: percentage Min: 0 Max: 100
The trapezoid Peaking Position in percentage (%) of the flat top.

Value
E.g. 80%.

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2.10.6 EnergyFilterPeakingAvg
Level: CH Mode: R/W Type: ENUM
The number of samples used to evaluate the peak.

Value
Option Description
OneShot 1 sample
LowAVG 4 samples
MediumAVG 16 samples
HighAVG 64 samples

2.10.7 EnergyFilterPoleZeroT, EnergyFilterPoleZeroS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 32/4 Max: 524000/65500
Like the Gaussian pulse of the Shaping Amplifier, also the trapezoid requires an accurate pole-zero adjustment to
guarantee the correct return to the baseline at the end of the falling edge. To correctly set the pole-zero the user must
take care of setting the proper Trapezoid Decay Time value (which corresponds also to the Input Decay Time) to avoid
either undershoot or overshoot effects. Pole Zero Adjustment can reduce signal artifacts due to pulses pile up occurring
when the counting rate is high compared to the pulse decay.

Figure 4: Energy filter Pole-Zero undercompensation (left) and over compensation (right).

This parameter allows to set the Pole-Zero compensation (in ns or samples). 16-bit value.

Value
E.g. 50000 ns.

2.10.8 EnergyFilterFineGain
Level: CH Mode: R/W Type: NUMBER UoM: units Min: 1 Max: 10
Allows to set the energy fine gain (in 0.001 step). The energy fine gain is a digital multiplication factor and does not
change the Full Scale Range. 16-bit value.

Value
16-bit value.

2.10.9 EnergyFilterLFLimitation
Level: CH Mode: R/W Type: ENUM
Allows to enable a low-frequency filter for the energy filter.

Value
Option Description
0 Disabled
1 Enabled

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2.10.10 EnergyFilterBaselineAvg
Level: CH Mode: R/W Type: ENUM
The energy filter includes also a baseline restorer that operates on the trapezoidal filter output and calculates the
baseline by averaging a programmable number of points before the start of the trapezoid. The baseline is then frozen
for the trapezoid duration and used for the height calculation. Once the trapezoid is returned to the baseline, the
averaging restarts to run. The pulse height (i.e. the trapezoid amplitude) is given as the distance between the flat top
and the baseline taken in the programmed position; to further reduce the fluctuation of this distance due to the noise,
it is possible to average a certain number of points in the flat top before subtracting the baseline. This parameter allows
to set the trapezoid filter baseline average.

Value
Option Description
Fixed Baseline fixed at 0
VeryLow Baseline samples for average = 16
Low Baseline samples for average = 64
MediumLow Baseline samples for average = 256
Medium Baseline samples for average = 1024
MediumHigh Baseline samples for average = 4096
High Baseline samples for average = 16384

2.10.11 EnergyFilterBaselineGuardT, EnergyFilterBaselineGuardS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 0/0 Max: 8000/1000
In addition to the Baseline Average, the user can also set the Baseline Hold-Off or Baseline Guard value to freeze the
baseline calculation beyond the trapezoid end, thus reducing the noise on the baseline calculation. This parameter allows
to set the trapezoid filter baseline protection after peak (in ns or samples). 10-bit value.

Value
E.g. 2000 ns.

2.10.12 EnergyFilterPileUpGuardT, EnergyFilterPileUpGuardS

Level: CH Mode: R/W Type: NUMBER UoM: ns/sample Min: 0/0 Max: 64000/8000
If two events are separated by less than the trapezoid duration, then the relevant trapezoids overlap. The trapezoid
duration is defined as RT + FT + PileUpGuard, where RT is the trapezoid Rise Time, FT is the trapezoid Flat Top,The
PileUpGuard starts at the end of the Peaking time (see EnergyFilterPeakingPosition). This parameter allows to set the
trapezoid filter pileup guard (in ns or in steps of 8 samples = 64 ns). 10-bit value.

Value
E.g. 5000 ns.

2.10.13 Energy_Nbit
Level: CH Mode: R Type: NUMBER
Number of bits used to provide the Energy value.

Value
E.g. 16

2.10.14 ChRealtimeMonitor
Level: CH Mode: R Type: NUMBER UoM: 524288 ns
RealTime measured by the FPGA, incremented with step of 524288 ns. Reading this parameter updates the values of
ChDeadtimeMonitor, ChTriggerCnt, ChSavedEventCnt and ChWaveCnt.

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Value
32-bit value expressed in clock cycles.

2.10.15 ChDeadtimeMonitor
Level: CH Mode: R Type: NUMBER UoM: 524288 ns
DeadTime measured by the FPGA, incremented with step of 524288 ns. Updated when reading ChRealtimeMonitor.

Value
32-bit value expressed in clock cycles.

2.10.16 ChTriggerCnt
Level: CH Mode: R Type: NUMBER UoM: 1 cnt
Counter of channel triggers (24 bit), measured by FPGA. Updated when reading ChRealtimeMonitor.

Value
Eg. 1000.

2.10.17 ChSavedEventCnt
Level: CH Mode: R Type: NUMBER UoM: 1 cnt
Counter of channel saved events, measured by FPGA (24 bit). Updated when reading ChRealtimeMonitor.

Value
Eg. 1000.

2.10.18 ChWaveCnt
Level: CH Mode: R Type: NUMBER UoM: 1 cnt
Counter of channel events with waveform, measured by FPGA (24 bit). Updated when reading ChRealtimeMonito.

Value
Eg. 1000.

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3 Commands
3.1 Reset
Level: DIG
Resets the board. This command sets all registers to the default value and clear data from memories. It does not act on
the communication interfaces, the PLLs and the clocks.

3.2 ClearData
Level: DIG
Clear data from memories. Register’s content is not affected. This command is typically used before starting an
acquisition to guarantee that no data belonging to a previous run is still present in the internal memory of the digitizer.

3.3 ArmAcquisition
Level: DIG
Arms the digitizer to start an acquisition. When the start of run is software controlled, the arming is not implicit in the
start command and it is necessary to use the ArmAcquisition command.

3.4 DisarmAcquisition
Level: DIG
Disarms the acquisition and prevents the digitizer to start a new run (for instance controlled by an external signal feeding
SIN) without the grant of the software. It is possible to set an automatic disarm after the stop of the acquisition by means
of the EnAutoDisarmAcq parameter. However, in order to make the higher level software aware of this occurrence and
allow him to properly manage the Disarm condition, the use of the DisarmAcquistion command is mandatory even when
the EnAutoDisarmAcq parameter is used.

3.5 SwStartAcquisition
Level: DIG
Starts the acquisition, provided that the option SwStart is enabled in the parameter StartSource. This start command
does require a previous arming command.

3.6 SwStopAcquisition
Level: DIG
Forces the acquisition to stop, whatever is the start source.

3.7 SendSWTrigger
Level: DIG
Send a software trigger to the digitizer, provided that the option SwTrg is enabled in the GlobalTriggerSource parameter.

3.8 ReloadCalibration
Level: DIG
Delete calibration file and reload it from flash or, if invalid, use default calibration.

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4 Endpoints
4.1 Parameters
4.1.1 ActiveEndpoint
Level: ENDPOINT FOLDER Mode: R/W Type: ENUM
Defines which endpoint will be used.

Option Description
raw Decode is disabled and ReadData should be made on handle /endpoint/raw
dpppha Decode is enabled and ReadData should be made on handle /endpoint/dpppha

4.2 Raw Endpoints

4.2.1 Raw
Path: /endpoint/raw
Raw data. See MaxRawDataSize parameter to get the maximum size that can be returned by a single call to ReadData.

Supported fields
Name Native type Dim. Description
DATA U8 (fixed) 1 Raw data (type conversion not supported)
SIZE SIZE_T 0 Size of data written to DATA
N_EVENTS U32 0 Add N_EVENTS to raw endpoint to get the number of
events in the blob. In case of firmware using
aggregate events (DPP firmwares) it returns the
number of aggregates.

Default data format

[
{ "name": "DATA", "type”: "U8", "dim": 1 },
{ "name": "SIZE", "type”: "SIZE_T"}
]

Data are passed on the network as big-endian 64-bit words. The endianness must be properly adjusted before to start
decoding it.

In all the 27xx digitizer family the most general structure of the events is

Figure 5: 27xx digitizer general event structure.

where
• n. words = N
• format can be:
o 0x1 in case of Common Trigger Mode
o 0x2 in case of Individual Trigger Mode
o 0x3 in case of Special Events

The DPP-PHA belongs to the Individual trigger mode case. In such a mode the event aggregate has the following format

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Figure 6: Event aggregate in Individual Trigger Mode.

where
• n. aggregate words = N
• bit 56 ("board fail") is common to all the aggregated events. The size of each aggregated event must be
inferred by the information in the aggregated event itself.

Three event types are present in the data aggregate:

• The Start Run event
• Data events, one per each trigger accepted by the board
• The Stop Run event
The Start Run is a special event composed of four 64-bit words and generated by the board when the acquisition starts.
The Start Run event is below described:

Figure 7: Start Run event structure.

where
• dec. factor log2 (decimation factor in log2 scale) = 0x0;
• n. traces = 0x1;
• acquisition width = 0x0;

The aggregate event(0), aggregate event (1), …, aggregate event (N-1) can be of three types:

a. single event without waveform sample (W=0)

b. single event with waveform sample (W=1)

c. single word event

Figure 8: DPP-PHA firmware Raw Data structure.

The latter can be used when the data throughput is a concern. Such event type replaces the first one when the
EnDataReduction is enabled.
In the above pictures:
• bit 63 is set on the last header word, despite the presence of the waveform payload. In case of no extra word,
it is set on the second word.
• there are always at least 2 words (i.e. bit 63 on first word is unset).
• the optional waveform payload is present only if the bit 62 on the second word is set.
• in the timestamp field: 1 LSB = 8 ns
• in the fine timestamp field: 1 LSB = 7.8125 ps

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• The number of user words must be deduced by bit 63.

When waveform are present, channel record length = N samples (ChRecordLengthS, ChRecordLengthT) so waveform n.
words = N/2.
Sample format is:
• analog probe #0 = bit [0:13]
• digital probe #0 = bit 14
• digital probe #1 = bit 15
• analog probe #1 = bit [16:29]
• digital probe #2 = bit 30
• digital probe #3 = bit 31

Extra word type can be

• Waveform = 0x0
• Time = 0x1

The DPP-PHA extra word Time and Counters is in the form

If enabled, these events are sent for statistical purposes only, and does not represent real events. If there is the time
extra word, bit 55 is set on the first word and the second word is meaningless. In the dead time field 1 LSB = 8 ns.

The DPP-PHA extra word Waveform is in the form

If there is the waveform extra word, bit 62 is set on the second word.

The Analog probe info format is:

• analog probe type = bit[0:2]
• is signed = bit 3
• multiplication factor = bit[4:5]

The Analog probe type can be:

• ADC input = 0x0
• Time filter = 0x1
• Energy filter = 0x2
• Energy filter baseline = 0x3
• Energy filter minus baseline = 0x4

The Analog probe multiplication factor can be:

• Factor 1 = 0x0
• Factor 4 = 0x1
• Factor 8 = 0x2
• Factor 16 = 0x3

The Digital probe info format is:

• digital probe type = bit[0:3]

The Digital probe type can be:

• Trigger = 0x0
• Time filter armed = 0x1
• Re-trigger guard = 0x2
• Energy filter baseline freeze = 0x3
• Energy filter peaking = 0x4
• Energy filter peak ready = 0x5
• Energy filter pile up guard = 0x6
• Event pile up = 0x7

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• ADC saturation = 0x8
• ADC saturation protection = 0x9
• Post saturation event = 0xA
• Energy filter saturation = 0xB
• Signal inhibit = 0xC

The Time resolution (Time res.) is referred to the waveform downsampling, and it can be:
• No downsampling = 0x0
• Downsampling x2 = 0x1
• Downsampling x4 = 0x2
• Downsampling x8 = 0x3
The Stop Run is a special event composed of three 64-bit words and generated at the end of the Run. The Stop Run event
will be read out after all the data events.

The Stop event is below described:

Figure 9: Stop Run event structure.

where
• Timestamp is the end of run time so the Real Time (1LSB = 8ns)
• Dead time is the dead time of the acquisition (1LSB = 8ns)

4.3 Decoded Endpoints

4.3.1 DPPPHA
Path: /endpoint/dpppha
Decoded endpoint.

Supported fields
Name Native type Dim. Description
CHANNEL U8 0 Channel (7 bits)
TIMESTAMP U64 0 Timestamp (48 bits)
TIMESTAMP_NS U64 0 Timestamp in nanoseconds (51 bits)
FINE_TIMSTAMP U16 0 Fine timestamp (10 bits)
ENERGY U16 0 Energy (16 bits)
FLAGS_LOW_PRIORITY U16 0 Event low priority flags (12 bits). See Low Priority.
FLAGS_HIGH_PRIORITY U8 0 Event high priority flags (8 bits). See High Priority.
TRIGGER_THR U16 0 Trigger threshold (16 bits)
TIME_RESOLUTION U8 0 Time resolution (2 bits):
• No downsampling (0)
• Downsampling x2 (1)
• Downsampling x4 (2)
• Downsampling x8 (3)
ANALOG_PROBE_1 I32 1 Analog probe #1 (18 bits, signed)
ANALOG_PROBE_1_TYPE U8 0 Analog probe #1 type (3 bits):
• ADC input (0)
• Time filter (1)
• Energy filter (2)

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Name Native type Dim. Description
• Energy filter baseline (3)
• Energy filter minus baseline (4)
ANALOG_PROBE_2 I32 1 Analog probe #2 (18 bits, signed)
ANALOG_PROBE_2_TYPE U8 0 Analog probe #2 type. See ANALOG_PROBE_1_TYPE
description.
DIGITAL_PROBE_1 U8 1 Digital probe #1 (1 bit)
DIGITAL_PROBE_1_TYPE U8 0 Digital probe #1 type (4 bits):
• Trigger (0)
• Time filter armed (1)
• Re trigger guard (2)
• Energy filter baseline freeze (3)
• Energy filter peaking (4)
• Energy filter peak ready (5)
• Energy filter pile up guard (6)
• Event pile up (7)
• ADC saturation (8)
• ADC saturation protection (9)
• Post saturation event (10)
• Energy filter saturation (11)
• Signal inhibit (12)
DIGITAL_PROBE_2 U8 1 Digital probe #2 (1 bit)
DIGITAL_PROBE_2_TYPE U8 0 Digital probe #2 type. See DIGITAL_PROBE_1_TYPE
description.

DIGITAL_PROBE_3 U8 1 Digital probe #3 (1 bit)

DIGITAL_PROBE_3_TYPE U8 0 Digital probe #3 type. See DIGITAL_PROBE_1_TYPE
description.
DIGITAL_PROBE_4 U8 1 Digital probe #4 (1 bit)
DIGITAL_PROBE_4_TYPE U8 0 Digital probe #4 type. See DIGITAL_PROBE_1_TYPE
description.

WAVEFORM_SIZE SIZE_T 0 Number of waveform samples, assumed to be equal

for all probes.
BOARD_FAIL BOOL 0 Set if the logical AND between of the ErrorFlag and
ErrorFlagDataMask is not 0. Present in all the events
belonging to the same aggregate. (1 bit)
EVENT_SIZE SIZE_T 0 Total event raw size, useful for statistics.
FLUSH BOOL 0 Flush of the aggregate word. Shared by all the events
in the aggregate. Useful for debug purposes. (1 bit)
AGGREGATE_COUNTER U32 0 Aggregate counter section in the Event Aggregate
structure. Shared by all the events in the aggregate.
Useful for debug purposes. (24 bit)

Default data format

[
{ "name": "CHANNEL", "type": "U8" },
{ "name": "TIMESTAMP", "type": "U64" },
{ "name": "FINE_TIMESTAMP", "type": "U16" },
{ "name": "ENERGY", "type": "U16" },
{ "name": "ANALOG_PROBE_1", "type": "I32", "dim": 1 },
{ "name": "ANALOG_PROBE_2", "type": "I32", "dim": 1 },
{ "name": "DIGITAL_PROBE_1", "type": "U8", "dim": 1 },
{ "name": "DIGITAL_PROBE_2", "type": "U8", "dim": 1 },
{ "name": "DIGITAL_PROBE_3", "type": " U8", "dim": 1 },
{ "name": "DIGITAL_PROBE_4", "type": " U8", "dim": 1 },

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CAEN Electronic Instrumentation
{ "name": "WAVEFORM_SIZE", "type": "SIZE_T" }
]

4.3.2 Statistics
Path: /endpoint/dpppha/stats
Decoded endpoint.
The statistics endpoint data are aligned to the data stream obtained from the dpppha endpoint.
The user should note that the dpppha endpoint has a buffer of 4096 events, and therefore the statistics endpoint data
could be up to 4096 events ahead of what the user reads from the dpppha endpoint.
All the time fields are U64 Native type however the information in provided on 48 bit like the single even timestamp for
the fields REAL_TIME, DEAD_TIME and LIVE_TIME while it is provided on 51 bit for the fields REAL_TIME_NS,
DEAD_TIME_NS and LIVE_TIME_NS. All the counts fields are U32 Native type however the information in provided on 24
bit.

Supported fields
Name Native type Dim. Description
REAL_TIME U64 1 Channel real time (in clock steps)
REAL_TIME_NS U64 1 Channel real time (in ns)
DEAD_TIME U64 1 Channel dead time (in clock steps)
DEAD_TIME_NS U64 1 Channel dead time (in ns)
LIVE_TIME U64 1 Channel live time (in clock steps)
LIVE_TIME_NS U64 1 Channel live time (in ns)
TRIGGER_CNT U32 1 Counter of channel triggers
SAVED_EVENT_CNT U32 1 Counter of channel saved events

Default data format

[
{ "name": "REAL_TIME", "type": "U64", "dim": 1 },
{ "name": "DEAD_TIME", "type": "U64", "dim": 1 }
]

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 CAEN Electronic Instrumentation

5 Flags
5.1 High Priority
Bit Name Description
0 Pile-Up Identifies pile-up events, ie two events in which the second one occurred
before the Peaking Time of the first one. Both are then tagged as pile-up
because it’s not possible to evaluate their energy. See
EnergyFilterPeakingPosition
1 Pile-up rejector guard Identifies an event occurred during the pile-up rejector guard window. See
event EnergyFilterPileUpGuardT, EnergyFilterPileUpGuardS. There are cases in
which both such bits can be '1': if an event occurs in the pile-up rejector
guard of the previous one and does not reach the peaking time because
another event has occurred, then such event will have both bits at 1. This
allows, with the same data and without doing two separate acquisitions, to
have two spectra: one corrected for the PUR guard and one not corrected
2 Event saturation Identifies an event in which a saturation of the input dynamics occurred
3 Post saturation event Identifies an event occurred during the ADCVetoWidth time.
4 Trapezoid saturation Identifies an event in which a saturation of the trapezoid occurred.
event
5 SCA selected event Identifies an event falling within the SCA windows (if enabled).

5.2 Low Priority

Bit Name Description
0 Event waveform Identifies a saved waveform because occurred when the external inhibit is
occurred during external active (useful in case of Transistor Reset Preamplifier detector use to see
inhibit what happens during the reset).
1 Event waveform under- Identifies a saved waveform because under-saturating.
saturation
2 Event waveform over- Identifies a saved waveform because over-saturating.
saturation
3 External trigger Identifies an event triggered by the external trigger from the TRG-IN
connector
4 Global trigger Identifies an event triggered by a global trigger condition.
5 Software trigger Identifies an event triggered by a software trigger.
6 Self trigger Identifies an event triggered by the single channel self trigger.
7 LVDS trigger Identifies an event triggered by the external trigger from the LVDS
connector.
8 64 channel trigger Identifies an event triggered by another (or a combination of other)
channels trigger.
9 ITLA trigger Identifies an event triggered by the ITLA logic.
10 ITLB trigger Identifies an event triggered by the ITLB logic.

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CAEN Electronic Instrumentation

6 Technical Support
CAEN makes available the technical support of its specialists for requests concerning the software, hardware,
and eventually board repair. To access the support platform, please follow the steps below:

1. Login at www.caen.it or register a new account.

2. On the MyCAEN+ area, from the “Dashboard” section (www.caen.it/mycaen/dashboard), register your
boards
3. From the “Support” section (www.caen.it/mycaen/support) open a ticket request for the issue you have
found.
4. In case of product repair, a CAEN operator will enable the RMA (Return Merchandise Authorization) form
directly from the support ticket.

Note: only MyCAEN+ accounts can request technical support. If you have a basic account, please insert
 your institutional email: if the domain is in our whitelist, the account is automatically updated to MyCAEN+,
otherwise an operator will take care of the validation within 48 hours.

UM7788 – FELib PHA Parameters User Manual rev. 5 52

CAEN
Tools for Discovery
n Electronic Instrumentation

CAEN SpA is acknowledged as the only company in the world providing a complete range of High/Low Voltage Power
Supply systems and Front-End/Data Acquisition modules which meet IEEE Standards for Nuclear and Particle Physics.
Extensive Research and Development capabilities have allowed CAEN SpA to play an important, long term role in this
field. Our activities have always been at the forefront of technology, thanks to years of intensive collaborations with the
most important Research Centres of the world. Our products appeal to a wide range of customers including engineers,
scientists and technical professionals who all trust them to help achieve their goals faster and more effectively.

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Tel. +39.0584.388.398 Tel. +49 (0)212 254 4077 Tel. +1.718.981.0401
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info@caen.it Fax +49 (0)212 25 44079 info@caentechnologies.com
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UM7788 - FELib PHA Parameters User Manual rev. 3 - July 1st, 2022
00107/17:VX2740.MUTX/0
Copyright © CAEN SpA. All rights reserved. Information in this publication supersedes all earlier versions. Specifications subject to change without notice.

53 UM7788 – FELib PHA Parameters User Manual rev. 5