FACULTY OF ENGINEERING, TECHNOLOGY AND BUILT ENVIRONMENT

BEE2041 - DIGITAL ELECTRONICS II LAB

MAY – AUGUST 2023

LAB REPORT 4

DESIGN MOORE SEQUENCE DETECTOR TO DETECT A SEQUENCE ----101----

USING “STATE MACHINE FILE” IN QUARTUS 2

Name Student ID
Luai Jia Seng 1001850425
Shiwveshana Parmasivam 1002268536
Pang Jun Hong 1002164551
Ishrat Jabin 1002266036
Gan Zhi Yong 1002058218
TITLE : Design Moore Sequence Detector To Detect A Sequence 101 Using “State Machine
File” In Quartus 2

INTRODUCTION

The Moore Sequence Detector is a fundamental digital logic circuit that is used to identify
specific sequences within a digital input stream. It does this by comparing the digital input
stream to a known sequence. During this lab project, which is titled "Designing a Moore
Sequence Detector to Detect Sequence 101 using 'State Machine File' in Quartus II," we go
into the world of digital design and hardware description languages in order to build a
sequence detector that is on the cutting edge of technological advancement.

The major purpose of this project is to create a Moore-type state machine by making use of
Quartus II, which is a well-known piece of software that is used for digital design, simulation,
and synthesis. The target sequence that will be identified is "101," and the detector will be
developed to properly recognize this sequence wherever it appears in an input stream. The
idea behind a Moore machine is that it is able to generate outputs entirely based on its present
state, regardless of the input that is being provided at that specific time. When it comes to
designation, different flipflops (such as D, JK, and SR) and state machines (such as Mealy
and Moore) stand for varying efficacy in terms of things like power consumption, time delay,
cost, and other factors; all of these aspects are determined by the requirement.

Throughout the course of this experiment, we have investigated the fundamental aspects of
state machines, such as their states, inputs, outputs, and transitions. We were able to develop
the requisite sequence detector by creating a state machine file so that we can define the
states and transitions that are necessary.
METHODOLOGY

State Machine Diagram

To begin, we need to have a solid understanding of the requirements of the sequence detection
task, which is to locate the sequence "101" anywhere within the input stream. We are going to
create a Moore Sequence Detector, which is a device that creates outputs only dependent on
the state it is in at the moment. To begin, we sketch out a picture of the state machine to illustrate
the different states, transitions, inputs, and outputs. The various states are depicted as circles
with meaningful names, and the connections between them are shown as arrows. These arrows
signify transitions that are triggered when certain input requirements are met. The outputs are
decided according to the current state, which indicates whether or not the desired sequence has
been found.

Verilog HDL

Moving on to the Verilog_HDL implementation, the first thing that has to be done is to declare
the module. This module will have inputs that represent the bits of the input stream, and it will
have an output that indicates sequence detection. We establish a state register to keep track of
the current state of the Moore machine and define an enumerated data type to represent the
different states of the Moore machine. We decide the subsequent state and the outputs that
correspond to that state using combinational logic. This logic takes into account both the inputs
and the current state. In accordance with the idea underlying the Moore machine, these outputs
are produced entirely as a consequence of the existing state.

As soon as the design is complete, for the purpose of ensuring accurate outputs, simulation
covers a variety of input sequences, including both valid and invalid instances of the required
"101" sequence. After the simulation and verification processes have been completed
successfully, we use Quartus II to synthesize the Verilog code in order to build the hardware
configuration files. On the target platform, the performance of the design is evaluated in terms
of speed and resource consumption, and optimization is made, where appropriate. By adhering
to this all-encompassing methodology, we will be able to effectively design and construct a
Moore Sequence Detector in Quartus II. This detector will be able to recognize the sequence
"101" and will do so by employing a state machine diagram in addition to Verilog_HDL.
 Where is the logic circuit diagram?
SIMULATION

label what is x and ~x

Figure 1 : Moore Machine State Diagram for 101 Detection

Figure 2 : Output for the Moore State Machine

Figure 3 : Output for the Moore State Machine with label

Figure 4 : Sequence of input and output signal

increase the font size.

Figure 5 : Verilog HDL code

 Figure 6 : Verilog HDL code

DICSUSSION

The Moore state diagram, which consists of four phases A, B, C, and D, represents the sequence
detection logic effectively. In state A, when the input changes to 1, the machine transitions to
state B. State B is then transformed into state C when the input becomes 0 and state D when
the input is 1. Additionally, state D reverts to state C when input 0 is received. Throughout
these transitions, the output remains constant and is directly proportional to the Moore
machine's current state. This trait conforms to the fundamental principle of Moore machines,
which dictates that outputs are exclusively determined by the current state.

To evaluate the functionality of this '101' sequence detector state machine, we applied the
simulation software Quartus II, which produced accurate and fluid results. The successful
simulation validated the state diagram's efficacy as a Moore state machine for achieving the
intended sequence detection.

The timing diagram analysis disclosed an intriguing aspect of Moore machines. When the
sequence '101' was detected during a particular clock cycle (t2, t3, or t4), the output changed
to 1 only after the subsequent rising edge of the clock (t3, t4, or t6) and not at the precise
completion of the sequence. This latency between sequence completion and output
modification is a defining characteristic of Moore machines. Moore machines introduce this
response delay because outputs are linked to the state rather than the inputs themselves.

Close examination of the timing events revealed that the input alterations and corresponding
output responses were synchronized with the clock's rising edges. At t0, the input transformed
from 0 to 1, and at t1, it reversed direction and became 0. At t2, the input again transitioned
from 0 to 1, forming the sequence '101'. However, the output remained 0 until t3's ascending
edge, when the sequence completed. Therefore, at time t3, the output changed to 1, signifying
effective sequence detection. Consequently, the input changed from 1 to 0 at t3's ascending
edge, and the output also changed from 1 to 0. At time t4, the input changed from 0 to 1, re-
creating the sequence '101'. The output remained 0 until the ascending edge of t6 signaled the
completion of the sequence, at which point it reverted to 1.
Did not discuss on the VHDL code.

CONCLUSION

In this lab, we focused on making a Moore Sequence Detector, which is a sequential state
machine that looks for a specific target sequence in a string of bits. Our goal was to find the
sequence "101." As a Moore machine, the output of our device is only based on its current state
and not on the input (x). During the experiment, we were able to successfully build the Moore
Sequence Detector in Quartus II by following the Figure X state diagram. The state diagram
shows the changes and factors that are needed to find the sequence "101." This required making
four states, called A, B, C, and D, and setting up the transitions between them based on the
input numbers.

When we used Quartus II's simulation tool to test the designed Moore Sequence Detector, we
got the results we wanted and expected. The computer waveform showed that the output went
high (1) exactly when the input sequence "101" was read by the state machine. This result
proves that the Moore machine works as it should to find the target code.
The fact that this lab experiment went well has taught us a lot about how Moore state machines
can be used as sequence monitors. Moore machines make digital circuit design easier and more
predictable because they only use the current state to figure out what to do next.

Overall, the correct application of the Moore Sequence Detector and its ability to find the "101"
sequence help us learn more about digital logic and state machines. This lab experience taught
us a lot that will be very useful as we continue to learn about and build more complicated digital
systems in the future.

REFERENCES

[1] What is a Moore machine?. (2023). Retrieved 25 July 2023, from

https://www.educative.io/answers/what-is-a-moore-machine

[2] Verilog Tutorial for Beginners. (2023). Retrieved 26 July 2023, from
https://www.chipverify.com/verilog/verilog-tutorial

[3] Harris, S., & Harris, D. (2022). Sequential Logic Design. Digital Design And Computer
Architecture, 106-169. doi: 10.1016/b978-0-12-820064-3.00003-9
 FACULTY OF ENGINEERING
ELECTRICAL AND ELECTRONIC ENGINEERING DEPARTMENT
Lab Report Assessment Rubric
Luai Jia Seng ( 1001850425) , Shiwveshana Parmasivam (1002268536), Pang Jun Hong (1002164551),
Ishrat Jabin (1002266036), Gan Zhi Yong (1002058218)
Name and ID: Lab:

Category 1 (Poor) 2 (Fair) 3 (Good) 4 (Very Good) 5 (Excellent) Marks Total

Introduction is unclear or Introduction is somewhat Introduction is clear and Introduction is clear and Introduction is exceptional,
lacks depth. clear and provides some provides adequate provides thorough providing extensive
background information. background information. background information. background information and
Introduction (Literature 4
a clear statement of the ______ x 0.6 2.4
Review)
research question or
hypothesis.

Methodology is incomplete or Methodology is somewhat Methodology is complete and Methodology is complete, Methodology is exceptional,
unclear, with significant complete and clear, but lacks clear, with adequate detail clear, precise, and with exceptional clarity,
errors in the simulation, detail or precision, with some and precision, and demonstrates a clear detail, precision, and
circuit, table or calculation. errors in the simulation, demonstrates a good understanding of the innovation in the simulation,
circuit, table or calculation. understanding of the procedures and techniques circuit, table or calculation,
Method (Simulation, Circuit, procedures and techniques used, with minimal errors in with no errors. 4 x 0.6
______ 2.4
Table and Calculation) used, with few errors in the the simulation, circuit, table
simulation, circuit, table or or calculation.
calculation.

Results are incomplete or lack Results are somewhat Results are complete and Results are complete, clear, Results are exceptional, with
clarity. complete and clear, but lack clear, with adequate detail precise, and well-organized. exceptional clarity, detail, 2.4
Results (Lab Work with
some detail or precision. and precision. precision, and outstanding 4 x 0.6
______
image and description)
organization.

Little or no discussion or Somewhat complete Complete discussion and Complete discussion and Exceptional discussion,
conclusion, or lacks insights. discussion and conclusion, conclusion, provides conclusion, provides providing exceptional insights
provides some insights into adequate insights into the thorough insights into the into the results and
4
Discussion and conclusion the results. results. results, and is well-supported demonstrating a deep ______ x 0.6 2.4
by evidence. understanding of their
significance.
 Report is poorly written, Report is somewhat clear, but Report is clear, well- Report is exceptionally clear, Report is exceptional in every
contains numerous errors, may have some errors, lacks organized, and meets the well-organized, and exceeds aspect, demonstrating
lacks clarity and organization, clarity and organization, and minimum requirements of the minimum requirements exceptional clarity,
and fails to meet the meets the minimum the assignment. of the assignment. organization, and creativity,
minimum requirements of requirements of the Demonstrates a good Demonstrates a thorough displaying outstanding 5 x 0.6
Overall Quality ______
the assignment. assignment but lacks polish. understanding of the topic understanding of the topic originality and a deep 3
and displays some creativity and displays significant understanding of the topic,
and originality. creativity and originality. providing exceptional
contributions to the field.

Total Marks (15%) 12.6