CD4555BMS

CD4556BMS
CMOS Dual Binary to 1 of 4
December 1992 Decoder/Demultiplexers

Features Pinouts CD4556BMS

TOP VIEW
• High Voltage Type (20V Rating)
E 1 16 VDD
• CD4555BMS: Outputs High on Select
A 2 15 E
• CD4556BMS: Outputs Low on Select
B 3 14 A
• Expandable with Multiple Packages
1/2 OF DUAL Q0 4 13 B
• 100% Tested for Quiescent Current at 20V Q1 5 12 Q0 1/2 OF DUAL
• Standardized, Symmetrical Output Characteristics Q2 6 11 Q1

• Maximum Input Current of 1µA at 18V Over Full Pack- Q3 7 10 Q2

age Temperature Range; 100nA at 18V and +25oC VSS 8 9 Q3

• Noise Margin (Over Full Package/Temperature Range)

CD4555BMS
- 1V at VDD = 5V TOP VIEW
- 2V at VDD = 10V
- 2.5V at VDD = 15V E 1 16 VDD

• 5V, 10V and 15V Parametric Ratings A 2 15 E

B 3 14 A
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of 1/2 OF DUAL Q0 4 13 B
‘B’ Series CMOS Devices” Q1 5 12 Q0 1/2 OF DUAL

Q2 6 11 Q1
Applications
Q3 7 10 Q2
• Decoding VSS 8 9 Q3
• Code Conversion
• Demultiplexing (Using Enable Input as a Data Input
Functional Diagrams
• Memory Chip-Enable Selection
VDD 16
• Function Selection 2 4
Q0
A 5
3 Q1
B 6
1
Description E
7
Q2
Q3
CD4555BMS and CD4556BMS are dual one-of-four decod- 12
14 Q0
ers/demultiplexers. Each decoder has two select inputs (A A 11
13 Q1
B 10
and B), an Enable input (E), and four mutually exclusive out- 15 Q2
E 9
puts. On the CD4555BMS the outputs are high on select; on Q3
the CD4556BMS the outputs are low on select. VSS 8

When the Enable input is high, the outputs of the CD4555BMS

CD4555BMS remain low and the outputs of the
CD4556BMS remain high regardless of the state of the VDD 16
4
select inputs A and B. The CD4555BMS and CD4556BMS A
2 Q0
3 5
are similar to types MC14555 and MC14556, respectively. B Q1
1 6
E Q2
7
The CD4555BMS and CD4556BMS are supplied in these Q3
16-lead outline packages: 12
14 Q0
A 11
Braze Seal DIP *H46 †H4T 13 Q1
B 10
15 Q2
Frit Seal DIP H1E E 9
Q3
Ceramic Flatpack H6W
VSS 8
*CD4555B Only †CD4556B Only
CD4556BMS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3346
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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 Specifications CD4555BMS, CD4556BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125oC
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

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 Specifications CD4555BMS, CD4556BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 440 ns
A or B Input to any Output TPLH1
10, 11 +125oC, -55oC - 594 ns
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
E to any Output TPLH2
10, 11 +125oC, -55oC - 540 ns
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 7 - V
-55oC

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 Specifications CD4555BMS, CD4556BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 190 ns
A or B Input to any Output TPLH1 o
VDD = 15V 1, 2, 3 +25 C - 140 ns
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25oC - 170 ns
E to any Output TPLH2 oC
VDD = 15V 1, 2, 3 +25 - 130 ns
Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
TTLH
VDD = 15V 1, 2, 3 +25oC - 80 ns
oC
Input Capacitance CIN Any Input 1, 2 +25 - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25o C - 25 µA
o
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25 C -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas

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 Specifications CD4555BMS, CD4556BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
PART NUMBER CD4555BMS & CD4556BMS
Static Burn-In 1 4 - 7, 9 - 12 1 - 3, 8, 13 - 15 16
Note 1
Static Burn-In 2 4 - 7, 9 - 12 8 1 - 3, 13 - 16
Note 1
Dynamic Burn- - 1, 8, 15 16 4 - 7, 9 - 12 2, 14 3, 13
In Note 1
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagrams
4(12) 4(12)
2(14) Q0 2(14) Q0
A A
5(11) 5(11)
* *
Q1 Q1
3(13) 3(13)
B 6(10) B 6(10)
Q2 Q2
* *
7(9) 7(9)
1(15) 1(15)
Q3 Q3
E E
VDD VDD
* *
*ALL INPUTS PROTECTED BY CMOS *ALL INPUTS PROTECTED BY CMOS
PROTECTION NETWORK PROTECTION NETWORK

VSS VSS
FIGURE 1. CD455RBMS LOGIC DIAGRAM (1 OF 2 IDENTICAL FIGURE 2. CD4556BMS LOGIC DIAGRAM (1 OF 2 IDENTICAL
CIRCUITS) CIRCUITS)

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 CD4555BMS, CD4556BMS

TRUTH TABLE

INPUTS ENABLE SELECT OUTPUTS CD4555BMS OUTPUTS CD4556BMS

E B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 1 0 1
0 1 0 0 1 0 0 1 0 1 1
0 1 1 1 0 0 0 0 1 1 1
1 X X 0 0 0 0 1 1 1 1
X = Don’t Care Logic 1 ≡ High
Logic 0 ≡ Low

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

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 CD4555BMS, CD4556BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)
AMBIENT TEMPERATURE (TA) = +25oC

250 250

200 SUPPLY VOLTAGE (VDD) = 5V 200

SUPPLY VOLTAGE (VDD) = 5V

150 150
10V

100 100 10V

15V 15V
50 50

0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (A OR B INPUT TO ANY OUTPUT) CAPACITANCE (E INPUTS TO ANY OUTPUT)
PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

300 TRANSITION TIME (tTHL, tTLH) (ns)

250
200

200
ANY INPUT SUPPLY VOLTAGE (VDD) = 5V
150
150

100
100 E INPUT 10V
15V
50 50

0 5 10 15 20 0
0 20 40 60 80 100
SUPPLY VOLTAGE (VDD) = 5V
LOAD CAPACITANCE (CL) (pF)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME vs SUPPLY FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CPACI-
VOLTAGE TANCE
106
AMBIENT TEMPERATURE (TA) = +25oC
DYNAMIC POWER DISSIPATION (PD) (µW)

5
10

104 SUPPLY VOLTAGE (VDD) = 15V

LOAD CAPACITANCE (CL) = 50pF

103

VDD = 10V
CL = 50pF
102
VDD = 10V
CL = 15pF
10
VDD = 5V
CL = 50pF
1
2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
10-1 1 10 102 103 104
INPUT FREQUENCY (f) (kHz)

FIGURE 11. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY

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 CD4555BMS, CD4556BMS

20ns 20ns 20ns 20ns

90% VDD 90% VDD

50% INPUT B 50% INPUT B
10% VSS 10% VSS
tPHL tPLH
tPLH tPHL

90% VDD 90% VDD

50% OUTPUT Q3 50% OUTPUT Q3
10% VSS 10% VSS
tTHL
tTLH
tTLH tTHL

fI = 1MHz, 50% DUTY CYCLE fI = 1MHz, 50% DUTY CYCLE

FIGURE 12. CD4555BMS B INPUT TO Q3 OUTPUT DYNAMIC FIGURE 13. CD4556BMS B INPUT TO Q3 OUTPUT DYNAMIC
SIGNAL WAVEFORMS SIGNAL WAVEFORMS

20ns 20ns
20ns 20ns
VDD VDD
90%
90%
50% INPUT E INPUT E
50%
10% VSS 10% VSS
tPHL
tPLH tPLH tPHL

VDD 90% VDD

90%
50% OUTPUT Q3 50% OUTPUT Q3
10% 10%
VSS VSS
tTHL tTLH tTLH
tTHL

fI = 1MHz, 50% DUTY CYCLE fI = 1MHz, 50% DUTY CYCLE

FIGURE 14. CD4555BMS E INPUT TO Q3 OUTPUT DYNAMIC FIGURE 15. CD4556BMS E INPUT TO Q3 OUTPUT DYNAMIC
SIGNAL WAVEFORMS SIGNAL WAVEFORMS

Applications
TRUTH TABLE
1/6 CD4555BMS
SELECT INPUTS OUTPUTS
A Q0
A Q0 B A Q0 Q1 Q2 Q3
SELECT

Q1
INPUTS

B Q1 0 0 DATA 0 0 0
B OUTPUTS
Q2
Q2 0 1 0 DATA 0 0
E Q3 1 0 0 0 DATA 0
DATA Q3
1 1 0 0 0 DATA
1/6 CD4069BMS

FIGURE 16. 1 OF 4 LINE DATA DEMULTIPLEXER USING

CD4555BMS

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 CD4555BMS, CD4556BMS

Applications (Continued)
CD4555BMS
TRUTH TABLE
A Q0 INPUTS Q OUTPUTS
A Q0
Q1 C B A 0 1 2 3 4 5 6 7
B Q1
B 0 0 0 1 0 0 0 0 0 0 0
Q2
Q2
0 0 1 0 1 0 0 0 0 0 0
DECODER INPUTS

E Q3
Q3
0 1 0 0 0 1 0 0 0 0 0
OUTPUTS 0 1 1 0 0 0 1 0 0 0 0
A Q0
Q4 1 0 0 0 0 0 0 1 0 0 0
Q1 1 0 1 0 0 0 0 0 1 0 0
B Q5
Q2 1 1 0 0 0 0 0 0 0 1 0
Q6
E Q3 1 1 1 0 0 0 0 0 0 0 1
C Q7

1/6 CD4069BMS
OR EQUIV

FIGURE 17. 1 OF 8 DECODER USING CD4555BMS

CD4555BMS

A Q0
A Q0
Q1
B Q1
B Q2
Q2
E Q3
Q3

A Q0
Q4
DECODER INPUTS

Q1
B Q5
Q2
Q6
E Q3
Q7

A Q0
C
OUTPUTS
Q1
B
D Q2
A Q0
Q8
E Q3
E Q1
B Q9
Q2
1/2 CD4556BMS Q10
E Q3
Q11

A Q0
Q12
Q1
B Q13
Q2
Q14
E Q3
Q15

FIGURE 18. 1 OF 16 DECODER USING CD4555BMS AND CD4556BMS

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 CD4555BMS, CD4556BMS

TRUTH TABLE

INPUTS Q OUTPUTS
E D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
1 X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X = Don’t Care

Chip Dimensions and Pad Layouts

CD4555BMSH CD4556BMSH

Dimensions in parenthesis are in millimeters and are

derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

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 CD4555BMS, CD4556BMS

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