ECE 3153:

MICROPROCESSORS
Dr. Anu Shaju Areeckal,
Asst. Professor, Dept of E&C, MIT Manipal

This ppt is for reference only. Use the referred textbooks as the main study material.
ARM Data Transfer
Instructions

Credits: Dr. Bore Gowda, ECE, MIT

ARM Data Transfer Instructions
 Load-store instructions transfer data between memory and
processor registers.
 There are three types of load-store instructions:
o single-register data transfer(LDR/STR)
o multiple-register transfer(LDM/STM)
o Single data swap(SWP)
 These instructions are used for moving a single data item in and
out of a register.
 The datatypes supported are signed and unsigned:
o words (32-bit)
o halfwords (16-bit)
o bytes
Load-Store Instructions
Single-register transfer
Syntax: <LDR|STR>{cond}{B} Rd, addressing1
LDR{cond}H|SB|SH Rd, addressing2
STR{cond}H Rd, addressing2
LDR Load half word into a register Rd < - - mem32[address]
LDRB Load zero-extended byte into a register Rd < - - mem8[address]
Load zero-extended halfword into a
LDRH Rd < - - mem16[address]
register
LDRSH Load signed halfword into a register Rd < - - SignExtended(mem16[address])
LDRSB Load signed byte into a register Rd < - - SignExtended(mem8[address])
STRB Save a byte from a register into memory Rd - - > mem8[address]
STR Save a word from a register into memory Rd - - > mem32[address]
Save a halfword from a register into
STRH Rd - - > mem16[address]
memory
Addressing modes
Addressing modes
Addressing Modes in ARM Processors
 All instructions are designed to operate on an operand
 There are different ways to specify the address of the
operands for any given operations such as load, add or
branch.
 The different ways of determining the address of the operands
are called addressing modes.
 Types of addressing modes
• Register addressing mode
• Immediate addressing mode
• Indirect memory addressing modes
• Program counter relative addressing mode
Addressing modes
 Register Addressing modes
• In this addressing mode, the operand is specified in one of the
processor registers
• Example: MOV R1, R2
ADD R1, R2, R3

 Immediate addressing mode

• In this addressing mode, the operand value is specified in the
instruction itself
• Example: MOV R3, #0x12
ADD R4, R2, #0x12345678
AND R6, R1, #0xAA23CD24
Addressing modes
 Program counter relative addressing mode
• Register R15 is the program counter.
• If R15 is used as a pointer register to access operand, the resulting
addressing mode is called PC relative addressing.
• The operand is specified with respect to the current code location
• In this mode assembler determines the immediate offset as the
difference between the address of the operand and the content of the
updated PC
• When the effective address is calculated at run time, the content of PC
will have been updated to the address two words (8 bytes) forward
from the instruction containing the relative addressing mode
• The reason is that the ARM processor will have already fetched the
next instruction due to pipelined instruction execution
• Example: LDR R2, Val ; operand at [ PC, offset]
MOV r3, [R15, 0x25]
;ADD R1, R2, R3
Addressing modes
 Indirect memory addressing modes
• For indirect addressing modes, the operand is specified in the memory
• The ARM instruction set provides different modes for addressing
memory.
• The effective address of the memory operand is the sum of the
contents of a base register (Rn) and a signed offset
• The offset is either:
• a 12-bit immediate value in the instruction or
• the contents of a second register Rm or
• a shifted version of the contents of a second register Rm
• These modes incorporate following indexing methods:
• preindex
• preindex with writeback
• postindex.
Addressing modes
 Indirect memory addressing modes
 Preindex with writeback: Calculates an address from a base
register plus address offset and then updates that address base
register with the new address.
 Preindex: Same as the preindex with writeback but does not update
the address base register.
 Postindex: only updates the address base register after the address
is used.
 The preindex mode is useful for accessing an element in a data
structure.
 The postindex and preindex with writeback modes are useful for
traversing an array.
Addressing modes
 Indirect memory addressing modes
 A signed offset or register is denoted by “+/−”, identifying that it is either
a positive or negative offset from the base address register Rn.
 base address register (Rn): Pointer to a byte in memory, a
 offset: specifies a number of bytes.
 Immediate: Address is calculated using the base address register and a
12-bit offset encoded in the instruction.
 Register (Rm): Address is calculated using the base address register and a
specific register’s contents.
 Scaled: means the address is calculated using the base address register
and a barrel shift operation. These operations cannot use the barrel
shifter.
ARM Data Transfer Instructions
Single-register data transfer(LDR/STR)
Example:
// loads a word from the address stored in register r1 and places it into
register r0
LDR r0, [r1] ; = LDR r0, [r1, #0]

// store the contents of register r0 to the memory address contained in

register r1.
STR r0, [r1] ; = STR r0, [r1, #0]

The offset from register r1 is zero

Register r1 is called the base address register.
ARM Data Transfer Instructions
Single-register data transfer(LDR/STR)
 Addressing modes for LDR/STR/LDRB/STRB instructions
Addressing modes
 Indirect memory addressing modes
ARM Data Transfer Instructions
0x40000000 0x44332211 R0= 0x-------------
Pre condition for all 0x40000004 0x88776655 R1= 0x40000000
the instructions 0x40000008 0xCCBBAA99 R2= 0X00000004
0x4000000C 0x12FFEEDD
Post condition
Indexing Instructions
R0 R1 R2
LDR R0, [R1, #4] 0x88776655 0x40000000 0X00000004
Preindex LDR R0, [R1, R2] 0x88776655 0x40000000 0X00000004
LDR R0, [R1, R2, LSL #1] 0xCCBBAA99 0x40000000 0X00000004
Preindex LDR R0, [R1, #4]! 0x88776655 0x40000004 0X00000004
with LDR R0, [R1, R2]! 0x88776655 0x40000004 0X00000004
writeback LDR R0, [R1, R2, LSL #1]! 0xCCBBAA99 0x40000008 0X00000004
LDR R0, [R1], #4 0x44332211 0x40000004 0X00000004
Postindex LDR R0, [R1], R2 0x44332211 0x40000004 0X00000004
LDR R0, [R1], R2, LSL #1 0x44332211 0x40000008 0X00000004
ARM Data Transfer Instructions
Single-register data transfer(LDR/STR)
 Addressing modes for LDRH/STRH/LDRSB/LDRSH instructions
ARM Data Transfer Instructions

0x40000000 0x2211 R0= 0x-------------

Pre condition for all 0x40000002 0xBBAA R1= 0x40000000
the instructions 0x40000004 0x9988
0x40000006 0xDDFF

Post condition
Instructions
R0 R1
LDRH R0, [R1, #4] 0x00009988 0x40000000
LDRSH R0, [R1, #4] 0xFFFF9988 0x40000000
LDRSB R0, [R1, #4]! 0xFFFFFF88 0x40000004
LDRB R0, [R1, #4]! 0x00000088 0x40000004
ARM Data Transfer Instructions
Pre condition Post condition
Instructions
R0= 0x44332211 R0 R1
R1= 0x40000000 STR R0, [R1] 0x44332211 0x40000000
Post condition STRB R0, [R1, #4]! 0x44332211 0x40000004
0x40000000 ---- STRH R0, [R1, #4]! 0x44332211 0x40000008
0x40000001 ---- Post condition
0x40000002 ---- 0x40000000 0x11
0x40000003 ---- 0x40000001 0x22
0x40000004 ---- 0x40000002 0x33
0x40000005 ---- 0x40000003 0x44
0x40000006 ---- 0x40000004 0x11
0x40000007 ---- 0x40000005 ----
0x40000008 ---- 0x40000006 ----
0x40000009 ---- 0x40000007 ----
0x40000008 0x11
0x40000009 0x22
Data transfer instruction
format
ARM Data Transfer Instruction Format
ARM Data Transfer Instruction Format
 Bits [31-28] Condition
ARM Data Transfer Instruction Format
 Bits [27 26]: 0 1 fixed for data transfer instructions
ARM Data Transfer Instruction Format
 Bits [25]: offset is immediate(0) or register(1)

Bits[7-11]: shift amount 0-31 bits

6 5 Shift type
0 0 Logical left
0 1 Logical right
1 0 Arithmetic right
1 1 Rotate right
ARM Data Transfer Instruction Format
Bit [24] (P): Auto indexing
P=1 Pre indexing or
P=0 Post indexing
Bit[21] (W): updates/not updates the base register
W=1 Write back or
W=0 No write back

P W Functions Example R1=

1 0 Pre indexing mode, does not updates LDR R0, [R1, #4] R1
the base register
1 1 Pre indexing mode, auto updates the LDR R0, [R1, #4]! R1+4
base register
0 X Post indexing mode, auto updates the LDR R0, [R1], #4 R1+4
base register
ARM Data Transfer Instruction Format
Bit[20]: L – Load/Store
L=0 store L=1 load
[22]: B – bit (Unsigned Byte)
B=0 word b=1 byte
L B Functions
0 0 Store a word from a register to memory
0 1 Store a byte form a register to memory
1 0 Load a word from a memory to a register
1 1 Load a byte from a memory to a register

Bit[23]: U – bit (Up/Down)

 This bit makes instructions to compute an effective address starting
from a base register (Rn)
When U=1, effective address is computed by adding immediate or
register offset to base register (Rn)
When U=0, effective address is computed by subtracting an unsigned
immediate or register offset from base register (Rn)
Swap Instruction

26
Swap and Swap Byte Instructions

• Atomic operation of a memory read followed by a memory write which

moves byte or word quantities between registers and memory.
• Syntax:
• SWP{<cond>}{B} Rd, Rm, [Rn]

1
Rn
temp

2 3
Memory
• Thus to Rd Rd = Rm.
Rmimplement an actual swap of contents make
• The compiler cannot produce this instruction.
09-08-2023 Dr Kanthi. M, Professor, ECE Dept. 28
09-08-2023 Dr Kanthi. M, Professor, ECE Dept. 29
REFERENCE TEXTBOOKS
• William Hohl, “ARM assembly language
fundamentals and techniques”, CRC press, 2009
• Andrew N Sloss, “ARM System developer’s guide,
designing and optimizing system software”,
Elsevier, 2004
• J. R. Gibson, “ARM Assembly Language-an
Introduction”, Dept. of Electrical Engineering and
Electronics, The University of Liverpool, 2007