19-4674; Rev 3; 12/09

Low-Power, Multifunction, Polyphase AFE

General Description Features

MAXQ3180
The MAXQ3180 is a dedicated electricity measurement ♦ Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire,
front-end that collects and calculates polyphase volt- and Other 3-Phase Services
age, current, power, energy, and many other metering
and power-quality parameters of a polyphase load. The ♦ Active Power and Energy of Each Phase and
computed results can be retrieved by an external mas- Combined 3-Phase (kWh), Positive and Negative
ter through the on-chip serial peripheral interface ♦ Reactive Power and Energy of Each Phase and
(SPI™) bus. This bus is also used by the external mas- Combined, Positive and Negative
ter to configure the operation of the MAXQ3180 and
monitor the status of operations. ♦ Apparent Power and Energy of Each Phase and
Combined 3-Phase
The MAXQ3180 performs voltage and current measure-
ments using an integrated ADC that can measure up to ♦ Neutral Line Current Measurement
seven external differential signal pairs. An eighth differ- ♦ Line Frequency (Hz)
ential signal pair is used to measure the die tempera-
ture. An internal amplifier automatically adjusts the ♦ Power Factors
current channel gain to compensate for low-current ♦ Voltage Phasor Angles
channel-signal levels.
♦ Phase Sequence Indication
♦ Phase Voltage Absence Detection
Applications ♦ Voltage and Current Harmonic Measurement
3-Phase Multifunction Electricity Meters
♦ Fundamental and Total Power and Energy

Ordering Information ♦ Two Pulse Outputs: Configurable for Active,

Reactive, and Apparent Powers
PART TEMP RANGE PIN-PACKAGE
♦ Programmable Pulse Widths
MAXQ3180-RAN+ -40°C to +85°C 28 TSSOP
♦ Programmable No-Load Current Threshold
+Denotes a lead(Pb)-free/RoHS-compliant package.
♦ Programmable Meter Constants
♦ Programmable Thresholds for Undervoltage and
Pin Configuration and Typical Application Circuit appear at Overvoltage Detection
end of data sheet. ♦ Programmable Threshold for Overcurrent Detection
♦ Amp-Hours in Absence of Voltage Signals
♦ On-Chip Digital Temperature Sensor
♦ Precision Internal Voltage Reference 2.048V
(30ppm/°C typical), Also Supports An External
Voltage Reference
♦ Supports Software Meter Calibration
♦ Up to 3-Point Multipoint Calibration to
Compensate for Transducer Nonlinearity
♦ Power-Fail Detection
♦ Bidirectional Reset Input/Output
♦ SPI-Compatible Serial Interface with Interrupt
Request (IRQ) Output
♦ Single 3.3V Supply, Low Power (35mW typical)
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 Low-Power, Multifunction, Polyphase AFE
MAXQ3180

TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Metering Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Precision Pulse Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power-Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
External High-Frequency Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
External High-Frequency Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Internal RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Master Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SPI Communications Rate and Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SPI Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Host Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RAM-Based Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
General Operating Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Global Status Register (STATUS) (0x000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Operating Mode Register 0 (OPMODE0) (0x001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Operating Mode Register 1 (OPMODE1) (0x002) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Operating Mode Register 2 (OPMODE2) (0x003) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2 _______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
TABLE OF CONTENTS (continued)
Global Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Interrupt Request Flag Register (IRQ_FLAG) (0x004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Interrupt Mask Register (IRQ_MASK) (0x006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Meter Pulse Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Pulse Configuration—CFP Output (PLSCFG1) (0x01E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Pulse Configuration—CFQ Output (PLSCFG2) (0x01F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
CFP Pulse Width (PLS1_WD) (0x020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
CFP Pulse Threshold (THR1) (0x022) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
CFQ Pulse Width (PLS2_WD) (0x026) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
CFQ Pulse Threshold (THR2) (0x028) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Calibration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Current Gain, Phase X = A/B/C/N (X.I_GAIN) (A: 0x130, B: 0x21C, C: 0x308, N: 0x12E) . . . . . . . . . . . . . . . . . . .38
Voltage Gain, Phase X = A/B/C (X.V_GAIN) (A: 0x132, B: 0x21E, C: 0x30A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Energy Gain, Phase X = A/B/C (X.E_GAIN) (A: 0x134, B: 0x220, C: 0x30C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Phase-Angle Compensation, High Range, Phase X = A/B/C (X.PA0) (A: 0x13E, B: 0x22A, C: 0x316) . . . . . . . . .39
Phase-Angle Compensation, Medium Range, Phase X = A/B/C (X.PA1) (A: 0x140, B: 0x22C, C: 0x318) . . . . . .40
Phase-Angle Compensation, Low Range, Phase X = A/B/C (X.PA2) (A: 0x142, B: 0x22E, C: 0x31A) . . . . . . . . .40
Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Overcurrent Level (OCLVL) (0x044) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Overvoltage Level (OVLVL) (0x046) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Undervoltage Level (UVLVL) (0x048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
No-Load Level (NOLOAD) (0x04A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Phase Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C) . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Interrupt Mask, Phase X = A/B/C (X.MASK) (A: 0x145, B: 0x231, C: 0x31D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Energy Overflow Flags, Phase X = A/B/C (X.EOVER) (A: 0x146, B: 0x232, C: 0x31E) . . . . . . . . . . . . . . . . . . . . .43
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Line Frequency (LINEFR) (0x062) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power Factor, Phase X = A/B/C (X.PF) (A: 0x1C6, B: 0x2B2, C: 0x39E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
RMS Voltage, Phase X = A/B/C (X.VRMS) (A: 0x1C8, B: 0x2B4, C: 0x3A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
RMS Current, Phase X = A/B/C (X.IRMS) (A: 0x1CC, B: 0x2B8, C: 0x3A4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Energy, Real Positive, Phase X = A/B/C (X.EAPOS) (A: 0x1E8, B: 0x2D4, C: 0x3C0) . . . . . . . . . . . . . . . . . . . . . .45
Energy, Real Negative, Phase X = A/B/C (X.EANEG) (A: 0x1EC, B: 0x2D8, C: 0x3C4) . . . . . . . . . . . . . . . . . . . . .46
Energy, Reactive Positive, Phase X = A/B/C (X.ERPOS) (A: 0x1F0, B: 0x2DC, C: 0x3C8) . . . . . . . . . . . . . . . . . .46
Energy, Reactive Negative, Phase X = A/B/C (X.ERNEG) (A: 0x1F4, B: 0x2E0, C: 0x3CC) . . . . . . . . . . . . . . . . .47
Energy, Apparent, Phase X = A/B/C (X.ES) (A: 0x1F8, B: 0x2E4, C: 0x3D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

_______________________________________________________________________________________ 3
 Low-Power, Multifunction, Polyphase AFE
MAXQ3180

TABLE OF CONTENTS (continued)

Virtual Register Conversion Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Voltage Units Conversion Coefficient (VOLT_CC) (0x014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Current Units Conversion Coefficient (AMP_CC) (0x016) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Power Units Conversion Coefficient (PWR_CC) (0x018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Energy Units Conversion Coefficient (ENR_CC) (0x01A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Virtual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Real Power, Phase X = A/B/C/T (PWRP.X) (A: 0x801, B: 0x802, C: 0x804, T: 0x807) . . . . . . . . . . . . . . . . . . .51
Reactive Power, Phase X = A/B/C/T (PWRQ.X) (A: 0x811, B: 0x812, C: 0x814, T: 0x817) . . . . . . . . . . . . . . .52
Apparent Power, Phase X = A/B/C/T (PWRS.X) (A: 0x821, B: 0x822, C: 0x824, T: 0x827) . . . . . . . . . . . . . . .52
Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
RMS Volts, Phase X = A/B/C (V.X) (A: 0x831, B: 0x832, C: 0x834) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
RMS Amps, Phase X = A/B/C/N (I.X) (A: 0x841, B: 0x842, C: 0x844, N: 0x840) . . . . . . . . . . . . . . . . . . . . . . .53
Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Power Factor (PF.T) (0x867) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Real Energy, Phase A/B/C/T (ENRP.X) (A: 0x8C1, B: 0x8C2, C: 0x8C4, T: 0x8C7) . . . . . . . . . . . . . . . . . . . . .54
Reactive Energy, Phase A/B/C/T (ENRQ.X) (A: 0x8D1, B: 0x8D2, C: 0x8D4, T: 0x8D7) . . . . . . . . . . . . . . . . .54
Apparent Energy, Phase A/B/C/T (ENRS.X) (A: 0x871, B: 0x872, C: 0x874, T: 0x877) . . . . . . . . . . . . . . . . . .54
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Analog Front-End Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Digital Signal Processing (DSP) Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Digital Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Per Sample Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Per DSP Cycle Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Energy Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
No-Zero-Crossing Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Phase Sequence Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
RMS Voltage, RMS Current, and Energy Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Power Calculation (Active, Reactive, Apparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Energy Accumulation Start Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
No-Load Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
On Demand Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
RMS Volts, RMS Amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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Line Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Phasor Angles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Meter Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Generating Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Meter Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Overvoltage and Overcurrent Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Meter Units to Real Units Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Units Conversion Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Calibrating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Calibrating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Calibrating Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Interfacing the MAXQ3180 to External Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Connections to the Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Sensor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Voltage Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Voltage-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Voltage Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Current Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Current Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Current Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Advanced Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Modifying the ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Fine-Tuning the DSP Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Fine-Tuning the Line Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Fundamental Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Harmonic Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Low-Power Measurement Mode (LOWPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Advanced Calibrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Calibrating Current Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Calibrating Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Calibrating Power/Energy Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Multipoint Phase Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

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Advanced Register Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Analog Scan Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Time Slot Assignment—Current Channel X = A/B/C (SCAN_IX) (A: 0x008, B: 0x00C, C: 0x00A) . . . . . . . . . .73
Time Slot Assignment—Voltage Channel X = A/B/C (SCAN_VX) (A: 0x009, B: 0x00D, C: 0x00B) . . . . . . . . .74
Time Slot Assignment—Neutral Current Channel (SCAN_IN) (0x00E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Time Slot Assignment—Temperature Channel (SCAN_TE) (0x00F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Neutral Current and Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Auxiliary Channel Configuration (AUX_CFG) (0x010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
DSP System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
System Clock Frequency (SYS_KHZ) (0x012) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Cycle Count (CYCNT) (0x01C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Number of Scan Frames per DSP Cycle (NS) (0x040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Line Cycle Noise Rejection Filter (REJ_NS) (0x02C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Line Cycle Averaging Filter (AVG_NS) (0x02E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Meter Measurement Averaging Filter (AVG_C) (0x030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Meter Measurement Highpass Filter (HPF_C) (0x032) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Fundamental Filter Feed-Forward Coefficient (B0FUND) (0x034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Fundamental Filter Feedback Coefficient (A1FUND) (0x036) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Harmonic Filter Feed-Forward Coefficient (B0HARM) (0x03A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Harmonic Filter Feedback Coefficient (A1HARM) (0x03C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Zero-Cross Lowpass Filter (ZC_LPF) (0x05A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Hardware Mirror Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
ADC Configuration (R_ACFG) (0x04C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
ADC Conversion Rate (R_ADCRATE) (0x04E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
ADC Settling Time (R_ADCACQ) (0x050) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
SPI Configuration (R_SPICF) (0x052) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Zero-Crossing Timeout (NZX_TIMO) (0x054) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Communications Timeout (COM_TIMO) (0x056) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Energy Accumulation Timeout (ACC_TIMO) (0x058) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Phase-Angle Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Phase Offset Current Threshold 1 (I1THR) (0x05C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Phase Offset Current Threshold 2 (I2THR) (0x05E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Miscellaneous Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Neutral Current Gain (N.I_GAIN) (0x12E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Gain, Fundamental Energy, Phase X = A/B/C (X.EF_GAIN) (A: 0x136, B: 0x222, C: 0x30E) . . . . . . . . . . . . .87

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Linearity Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Linearity Offset, High Range, Phase X = A/B/C (X.OFFS_HI) (A: 0x138, B: 0x224, C: 0x310) . . . . . . . . . . . . .87
Linearity Gain Coefficient, Low Range, Phase X = A/B/C (X.GAIN_LO) (A: 0x13A, B: 0x226, C: 0x312) . . . .87
Linearity Offset, Low Range, Phase X = A/B/C (X.OFFS_LO) (A: 0x13C, B: 0x228, C: 0x314) . . . . . . . . . . . .88
Measurements—RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
On-Demand RMS Result (N.IRMS) (0x11C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Fundamental Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Fundamental Energy Overflow Flags, Phase X = A/B/C (X.EFOVER) (A: 0x147, B: 0x233, C: 0x31F) . . . . . .89
Energy, Fundamental, Real Positive, Phase X = A/B/C (X.EAFPOS) (A: 0x1FC, B: 0x2E8, C: 0x3D4) . . . . . .89
Energy, Fundamental, Real Negative, Phase X = A/B/C (X.EAFNEG) (A: 0x200, B: 0x2EC, C: 0x3D8) . . . . .90
Energy, Fundamental, Reactive Positive, Phase X = A/B/C (X.ERFPOS) (A: 0x204, B: 0x2F0, C: 0x3DC) . . .90
Energy, Fundamental, Reactive Negative, Phase X = A/B/C (X.ERFNEG) (A: 0x208, B: 0x2F4, C: 0x3E0) . .91
Energy Fundamental, Apparent, Phase X = A/B/C (X.ESF) (A: 0x20C, B: 0x2F8, C: 0x3E4) . . . . . . . . . . . . . .91
Energy Accumulated in the Last DSP Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Real Energy, Phase X = A/B/C (X.ACT) (A: 0x1D0, B: 0x2BC, C: 0x3A8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Reactive Energy, Phase X = A/B/C (X.REA) (A: 0x1D4, B: 0x2C0, C: 0x3AC) . . . . . . . . . . . . . . . . . . . . . . . . .92
Apparent Energy, Phase X = A/B/C (X.APP) (A: 0x1D8, B: 0x2C4, C: 0x3B0) . . . . . . . . . . . . . . . . . . . . . . . . .93
Fundamental Energy Accumulated in the Last DSP Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Fundamental Real Energy, Phase X = A/B/C (X.ACTF) (A: 0x1DC, B: 0x2C8, C: 0x3B4) . . . . . . . . . . . . . . . .93
Fundamental Reactive Energy, Phase X = A/B/C (X.REAF) (A: 0x1E0, B: 0x2CC, C: 0x3B8) . . . . . . . . . . . . .94
Fundamental Apparent Energy, Phase X = A/B/C (X.APPF) (A: 0x1E4, B: 0x2D0, C: 0x3BC) . . . . . . . . . . . .94
Checksum (CHKSUM) (0x060) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Measurements—Virtual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Fundamental Real Power, Phase A/B/C/T (PWRPF.X) (A: 0x881, B: 0x882, C: 0x884, T: 0x887) . . . . . . . . . . . . .96
Fundamental Reactive Power, Phase A/B/C/T (PWRQF.X) (A: 0x891, B: 0x892, C: 0x894, T: 0x897) . . . . . . . . . .96
Fundamental Apparent Power, Phase A/B/C/T (PWRSF.X) (A: 0x8A1, B: 0x8A2, C: 0x8A4, T: 0x8A7) . . . . . . . . .97
Fundamental Real Energy, Phase A/B/C/T (ENRPF.X) (A: 0x8E1, B: 0x8E2, C: 0x8E4, T: 0x8E7) . . . . . . . . . . . . .97
Fundamental Reactive Energy, Phase A/B/C/T (ENRQF.X) (A: 0x8F1, B: 0x8F2, C: 0x8F4, T: 0x8F7) . . . . . . . . .97
Fundamental Apparent Energy, Phase A/B/C/T (ENRSF.X) (A: 0x8B1, B: 0x8B2, C: 0x8B4, T: 0x8B7) . . . . . . . .97
Phasors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Phase B Phasor (VBPH: 0x852) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Phase C Phasor (VCPH: 0x854) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
RMS Voltage, Harmonic (V.HARM) (0x830) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
RMS Current, Harmonic/Neutral (I.N, I.HARM) (0x840) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Ratio of Harmonic/Fundamental (HARM_NF) (0x850) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

_______________________________________________________________________________________ 7
 Low-Power, Multifunction, Polyphase AFE
MAXQ3180

TABLE OF CONTENTS (continued)

Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Specific Design Considerations for MAXQ3180-Based Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

8 _______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
LIST OF FIGURES
Figure 1. External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 2. Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 3. Simplified Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 4a. SPI Interface Timing (CKPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 4b. SPI Interface Timing (CKPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 5. Read SPI Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 6. Write SPI Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 7. Flowchart for Reading from MAXQ3180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 8. Flowchart for Writing to MAXQ3180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 9. Per Sample Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 10. Computation of RMS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 11. Phase Compensation for Energy Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 12. Apparent and Reactive Energy Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 13. Sample Voltage Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 14. Sample Current Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 15. Offset Testing Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 16. Phase Offset vs. Input Current Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

LIST OF TABLES
Table 1. Command Format for SPI Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 2. Command Format for SPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 3. RAM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 4. Virtual Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 5. Meter Unit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 6. Virtual Register Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 7. Virtual Registers That Activate Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

_______________________________________________________________________________________ 9
 Low-Power, Multifunction, Polyphase AFE
ABSOLUTE MAXIMUM RATINGS
MAXQ3180

Voltage Range on DVDD Relative to DGND .........-0.3V to +4.0V Voltage Range on VxP, IxN Relative to AGND ......-0.3V to +4.0V
Voltage Range on AVDD Relative to AGND..........-0.3V to +4.0V Operating Temperature Range ...........................-40°C to +85°C
Voltage Range on AGND Relative to DGND .........-0.3V to +0.3V Junction Temperature ......................................................+150°C
Voltage Range on AVDD Relative to DVDD ..........-0.3V to +0.3V Storage Temperature Range .............................-65°C to +150°C
Voltage Range on Any Pin Relative to Lead Soldering Temperature .............................Refer to the IPC/
DGND except VxP, IxN Pins..............................-0.3V to +4.0V JEDEC J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

METERING SPECIFICATIONS
(VAVDD = VDVDD = VRST to 3.6V, Current Channel Dynamic Range 1000:1 at TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Active Energy Linearity Error DR 1000:1 0.1 %
Reactive Energy Linearity Error DR 1000:1 0.2 %
Apparent Energy Linearity Error DR 1000:1 0.5 %
RMS Voltage Linearity Error DR 20:1 0.5 %
DR 500:1 1.0
RMS Current Linearity Error %
DR 20:1 0.5
Line Frequency Error 0.5 %
Power Factor Error 1.0 %

ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER-SUPPLY SPECIFICATIONS
Digital Supply Voltage VDVDD VRST 3.6 V
Power-Fail Interrupt Trip Point VPFW Active mode, EPWRF = 1 2.84 3.13 V
Power-Fail Reset Trip Point VRST Active mode 2.70 2.99 V
Analog Supply Voltage VAVDD VRST 3.6 V
Analog Supply Current IAVDD fCLK = 8MHz 0.9 1.8 mA
Digital Supply Current IDVDD fCLK = 8MHz 8.5 13 mA
Low-Power Measurement Mode
ILOWPM LOWPM = 1 (Note 1) 4.2 mA
Current
Stop-Mode Current 0.2 12 μA
DIGITAL I/O SPECIFICATIONS
0.7 x
Input High Voltage VIH V
VDVDD
0.3 x
Input Low Voltage VIL V
VDVDD
Input Hysteresis VIHYS VDVDD = 3.3V 500 mV
Input Leakage IL VIN = DGND or VDVDD, pullup off ±0.01 ±1 μA

10 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
ELECTRICAL CHARACTERISTICS (continued)

MAXQ3180
(VAVDD = VDVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Low Current IIL VIN = 0.4V, weak pullup on -50 μA
RESET Pullup Resistance RRESET 50 150 200 k

VDVDD
I OH = -4mA
Output High Voltage (Except - 0.4
VOH V
RESET) VDVDD
I OH = -6mA
- 0.5
I OL = 4mA 0.4
Output Low Voltage VOL V
I OL = 6mA 0.5
SYSTEM CLOCK SOURCES
External Clock Input Frequency 0 8.12 MHz
External Clock Input Duty Cycle 45 55 %
External HF Crystal Frequency f SYS Fundamental mode 8.12 MHz
XTAL1, XTAL2 Internal Load
16 pF
Capacitance
Internal RC Oscillator Frequency 7.4 7.6 8.6 MHz
Internal RC Oscillator Accuracy ±2 %
Internal RC Oscillator Current 50 120 μA
Internal RC Oscillator Startup
(Note 1) 0.45 μs
Delay
ANALOG-TO-DIGITAL CONVERTER
Input Voltage Range 0 VREF V
Common-Mode Bias VCOMM 1.14 V
Offset Error ±2 mV
Offset Error Drift ±8 μV/°C
Gain Error (G = 1) 0.05 %
Spurious-Free Dynamic Range SFDR 90 dB
Total Harmonic Distortion THD 90 dB
Input Bandwidth (-3dB) (Note 1) 7 kHz
INTERNAL VOLTAGE REFERENCE
Temperature Coefficient (Note 1) 30 ppm/°C
Output Voltage VREF 2.048 V
INTERNAL TEMPERATURE SENSOR
Temperature Error (Note 1) -4 +4 °C
SPI SLAVE-MODE INTERFACE TIMING
Maximum SPI Clock Rate f SYS/4 MHz
4x
SCLK Input Pulse-Width High t SCH (Note 3) ns
t SYS
4x
SCLK Input Pulse-Width Low t SCL (Note 3) ns
t SYS

______________________________________________________________________________________ 11
 Low-Power, Multifunction, Polyphase AFE
ELECTRICAL CHARACTERISTICS (continued)
MAXQ3180

(VAVDD = VDVDD = VRST to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SSEL Low to First SCLK Edge
t SE (Note 3) 4t SYS ns
(Slave Enable)
Last SCLK Edge to SSEL High t SYS +
t SD ns
(Slave Disable) 5
MOSI Valid to SCLK Sample
t SIS 5 ns
Edge (MOSI Setup)
SCLK Sample Edge to MOSI t SYS +
t SIH ns
Change (MOSI Hold) 5
SCLK Shift Edge to MISO Valid 3t SYS
t SOV ns
(MISO Hold) +5
Note 1: Specifications guaranteed by design but not production tested.
Note 2: Specifications to -40°C are guaranteed by design and are not production tested.
Note 3: tSYS = 1/fSYS.

SPI Slave Mode Timing

tSD
SSEL SHIFT EDGE SAMPLE EDGE

tSCL tSCH

SCLK

tSE

tSOV

DATA OUTPUT

tSIS tSIH

DATA INPUT

12 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Block Diagram

MAXQ3180
VCOMM

VREF REF CFP, CFQ

COUNTERS I/O CFQ
V0P BUFFERS
I/O CFP
V1P
REGISTERS
V2P
I0P
I1P
I2P
INP
MISO
TEMP ADC SPI
I/O MOSI
SENSE BUFFERS SCLK
I/O
I0N REGISTERS SSEL
I1N
I2N
VN
ADC CONTROL,
ELECTRICITY
I/O I/O
METERING DSP, IRQ
REGISTERS BUFFERS
COMMUNICATIONS
MANAGER

WATCHDOG HF RC
RESET
TIMER OSC/8

16 x 16 POR/
HW MULTIPLY BROWNOUT SYSCLK
48-BIT ACCUMULATE MONITOR

HF
XTAL1
ADC CLOCK XTAL
ADCCLK XTAL2
MAXQ3180 PRESCALER OSC

______________________________________________________________________________________ 13
 Low-Power, Multifunction, Polyphase AFE
Pin Description
MAXQ3180

PIN NAME FUNCTION

POWER PINS
17, 22 DVDD Digital Supply Voltage
25 AVDD Analog Supply Voltage
18 DGND Digital Ground
9 AGND Analog Ground
Voltage Bias. This pin can be used to create an input common-mode DC offset for ADC channel
23 VCOMM
conversions.
Voltage Reference. Reference voltage for the ADC. An external reference voltage can be connected to
24 VREF
this pin when extremely high accuracy is required.
VOLTAGE AND CURRENT PINS
V0P, I0P,
26, 3, 4 Phase A Voltage and Current Analog Inputs
I0N
V1P, I1P,
27, 5, 6 Phase B Voltage and Current Analog Inputs
I1N
V2P, I2P,
28, 7, 8 Phase C Voltage and Current Analog Inputs
I2N
1 VN Analog Input for Common Voltage
2 INP Analog Input for Neutral Current
CLOCK PINS
10 XTAL2 High-Frequency Crystal Input/Output. When using an external high-frequency crystal, the crystal
oscillator circuit should be connected between XTAL1 and XTAL2. When using an externally driven
11 XTAL1 clock (EXTCLK = 1), the clock should be input at XTAL1, with XTAL2 left unconnected.
Interrupt Request Output. This line is driven low by the device to indicate to the master that an
12 IRQ
unmasked interrupt has occurred.
13 SSEL Slave Select Input. This line is the active-low slave select input for the SPI interface.
14 SCLK Slave Clock Input. This line is the clock input for the SPI interface.
Master Out-Slave In Input. This line is used by the master to transmit data to the slave (the
15 MOSI
MAXQ3180) over the SPI interface.
Master In-Slave Out Output. This line is used by the MAXQ3180 (the slave) to transmit data back to
16 MISO
the master over the SPI interface.
19 CFP Pulse Output 1. Configurable to represent energy or RMS voltage or current.
20 CFQ Pulse Output 2. Configurable to represent energy or RMS voltage or current.
Active-Low Reset Input/Output. An external master can reset the MAXQ3180 by driving this pin low.
This pin includes a weak pullup resistor to allow for a combination of wired-OR external reset
sources. An RC circuit is not required for power-up, as this function is provided internally. This pin
21 RESET
also acts as a reset output when the source of the reset is internal to the device (power-fail, watchdog
reset, etc.). In this case, the RESET pin is held low by the device until it exits the reset state, then the
RESET pin is released.

14 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Detailed Description added to the pulse accumulator. The pulse accumula-

MAXQ3180
tor is then tested to determine if the value in the accu-
The MAXQ3180 contains four major subsections: the
mulator is greater than the threshold. If it is greater, the
analog front-end, the digital signal processor, the preci-
threshold value is subtracted from the accumulator
sion pulse generators, and an SPI peripheral for com-
value and the meter pulse starts.
munication to the host processor.
SPI Peripheral
Analog Front-End The SPI controller is a slave-only device that can read
The analog front-end (AFE) is an 8-channel analog-to-
or write any location in the data RAM. Additionally, it
digital converter (ADC). It operates autonomously in the
can request data from on-demand registers.
standard configuration, assigning three channels to
phase A, B, and C voltage; three channels to phase A, The MAXQ3180 implements a truly full-duplex commu-
B, and C current; one channel to neutral current; and nication, rather than the pseudo half-duplex mode used
the last channel to a temperature sensor. by other SPI peripherals. That is, each time a character
is received by the MAXQ3180, a meaningful character
Each channel also contains a programmable-gain
is returned to the host. Often, this is a protocol charac-
amplifier capable of providing a gain of 1, 2, 4, 8, 16, or
ter. In this way, the host can be assured that the com-
32 incoming signals. Only the voltage channels permit
mand has been received and is valid. Optional error
gain scaling by the host processor. The MAXQ3180
checking can also be enabled to further guarantee
DSP firmware automatically sets the gain on current
proper operation.
channels.
Operating Modes
Digital Signal Processor The MAXQ3180 has two basic modes of operation,
The DSP code is permanently embedded in masked
each of which is described in the following sections.
ROM and accepts raw current and voltage samples for
The Initialization Mode is the default mode upon power-
each of three phases and continuously calculates a
up or following reset; entry to and exit from the other
host of values including RMS volts, RMS amps, real
operating modes is only performed as a result of com-
energy, reactive energy, apparent energy, fundamental
mands sent by the master.
and harmonic energy, and power factor.
The MAXQ3180 DSP core processes incoming sam- Run Mode
ples from the analog front-end according to user con- This mode is the normal operating mode for the
figurations. The host sets these operating parameters MAXQ3180. In this mode, the MAXQ3180 continuously
by specifying addresses within the device RAM space. executes the following operations:
When a calculation cycle is complete, the results are • Scans analog front-end channels and collects raw
placed back into RAM as well. Thus, the DSP core uses voltage and current samples.
the RAM block as both its input (for operating parame-
• Processes voltage and current samples through DSP
ters) and output (for calculation results) medium. See
filters as enabled and configured.
the SPI Peripheral section for how the host writes oper-
ating parameters and reads results from the RAM. • Calculates power, energy, and other required quanti-
ties and stores these values in RAM registers.
The DSP also calculates certain values such as line fre-
quency and active and reactive powers only when • Responds to register write and read commands from
demanded by the host. the master.
• Outputs power pulses on CFP and CFQ as configured.
Precision Pulse Generators
The MAXQ3180 includes two precision pulse genera- • Drives IRQ when an interrupt condition has been
tors that generate a pulse whenever certain conditions detected and the interrupt is not masked.
are met. In the MAXQ3180, many meter quantities can
Stop Mode
be selected for conversion to meter pulses including
This mode places the MAXQ3180 into a power-saving
absolute energy, net energy, reactive energy, voltage,
state where it consumes the least possible amount of
and current.
current. In Stop Mode, all functions are suspended,
The pulse generators are accumulators. On each DSP including the ADC and power and voltage measurement
cycle, whatever quantity is being measured—real ener- and processing. The MAXQ3180 does not respond to
gy, reactive energy, current, or something else—is any commands from the master in this operating state.

______________________________________________________________________________________ 15
 Low-Power, Multifunction, Polyphase AFE
Entry into Stop Mode only occurs at the request of the MAXQ3180, the SSEL line is normally driven low at the
MAXQ3180

master. To place the MAXQ3180 into Stop Mode, the beginning of each SPI command. This means that if the
master must read the ENTER STOP (0xC02) register. master sends an SPI command after the MAXQ3180
Once this register has been read, the MAXQ3180 enters Stop Mode, the MAXQ3180 automatically exits
enters Stop Mode immediately, before the transmission Stop Mode.
of the final ACK byte by the MAXQ3180.
Reset Sources
There are three possible ways to bring the MAXQ3180 There are several different sources that can cause the
back out of Stop Mode. MAXQ3180 to undergo a reset cycle. For any type of
• Power Cycle. The MAXQ3180 automatically exits hardware reset, the RESET pin is driven low when a
Stop Mode if a power-on reset occurs. Following exit reset occurs.
from Stop Mode, all registers are cleared back to
their default states, and the MAXQ3180 transitions to External Reset
Initialization Mode. This hardware reset is initiated by an external source
(such as the master controller or a manual pushbutton
• External Reset. The MAXQ3180 exits Stop Mode if
press) driving the RESET pin on the MAXQ3180 low.
an external reset is triggered by driving RESET low.
The RESET line must be held low for at least four cycles
Once the RESET pin is released and allowed to
of the currently selected clock for the external reset to
return to a high state, the MAXQ3180 comes out of
take effect. Once the external reset takes effect, it
reset and goes into Initialization Mode. All registers
remains in effect indefinitely as long as RESET is held
are cleared to their default states when exiting Stop
low. Once the external reset has been released, the
Mode in this manner.
MAXQ3180 clears all registers to their default states
• External Interrupt. Driving the SSEL pin low causes and resumes execution in Initialization Mode.
the MAXQ3180 to exit Stop Mode without undergoing
When an external reset occurs outside of Stop Mode,
a reset cycle. When exiting Stop Mode in this man-
execution (in Initialization Mode) resumes after four
ner, all register and configuration settings are
cycles of the currently selected clock (external high-fre-
retained, and the MAXQ3180 automatically resumes
quency crystal for Run Mode, 1MHz internal RC oscilla-
electric-metering functions and sample processing.
tor for LOWPM Mode). As the MAXQ3180 enters
Note that when the master is communicating with the Initialization Mode, the LOWPM bit is always cleared

CLOCK

RESET

RESET
SAMPLING

INTERNAL
RESET

BEGIN RUNNING IN INITIALIZATION MODE

Figure 1. External Reset

16 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
to 0, meaning that the MAXQ3180 always switches to power-on resets and brownout resets both cause the

MAXQ3180
the high-frequency clock before it begins accepting MAXQ3180 to reset in the same way.
commands in Initialization Mode.
Watchdog Reset
When an external reset occurs from Stop Mode, execu- The MAXQ3180 includes a hardware watchdog timer that
tion (in Initialization Mode) resumes after 128 cycles of is armed and periodically reset automatically during nor-
the internal RC oscillator (or approximately 128μs). mal operation. Under normal circumstances, the
Power-On Reset MAXQ3180 always resets the watchdog timer often
When the MAXQ3180 is first powered up, or when the enough to prevent it from expiring. However, if an internal
power supply, VDVDD, drops below the VRST power-fail error of some kind causes the MAXQ3180 to lock up or
trip point (outside of Stop Mode), the MAXQ3180 is enter an endless execution loop, the watchdog timer
held in power-on reset. Once the power supply rises expires and triggers an automatic hardware reset. There
above the V RST level, the power-on reset state is is no register flag to indicate to the master that a watch-
released and all registers are reset to their defaults and dog reset has occurred, but the RESET line strobes low
execution resumes in Initialization Mode. The high-fre- briefly.
quency external crystal (LOWPM = 0) is always select- The watchdog timer does not run during Stop Mode.
ed as the clock source following any power-on or
brownout reset. Software Reset
The master initiates a software reset by setting the
In Stop Mode brownout detection is disabled, so a SWRES (OPMODE0.3) bit to 1. When a software reset
power-on reset does not occur until VDVDD drops to a occurs, the MAXQ3180 clears all registers to their
lower level (V POR ). From the master’s perspective, default states and returns to Initialization Mode, in the

BROWNOUT DETECTION

BROWNOUT DETECTION (ALWAYS BROWNOUT DETECTION DISABLED

ENABLED OUTSIDE OF STOP MODE) DURING STOP MODE.
FORCES RESET STATE. POR = 1 NO RESET IS GENERATED.

VRST1

BROWNOUT DETECTION DISABLED.

POR LEVEL CAUSES RESET.

VPOR

tPOR

INTERNAL
RESET

STOP MODE

Figure 2. Brownout Reset

______________________________________________________________________________________ 17
 Low-Power, Multifunction, Polyphase AFE
same manner as if an external reset had taken place. External High-Frequency Crystal
MAXQ3180

Unlike a hardware reset, however, a software reset does The default system clock source for the MAXQ3180 is
not cause the MAXQ3180 to drive the RESET line low. an external high-frequency crystal oscillator circuit con-
nected between XTAL1 and XTAL2. When clocked with
Power-Supply Monitoring an external crystal, a parallel-resonant, AT-cut crystal
In addition to the hardware reset provided by the oscillating in the fundamental mode is required.
power-on reset and brownout reset circuits, the
MAXQ3180 includes the capability to detect a low When using a high-frequency crystal, the fundamental
power supply on the DVDD pin and alert the master oscillation mode of the crystal operates as inductive
through the interrupt (IRQ) mechanism before a hard- reactance in parallel resonance with external capaci-
ware reset occurs. This function, which is always tors C1 and C2. The typical values of these external
enabled outside of Stop Mode, causes the RAM status capacitors vary with the type of crystal being used and
register flag PWRF (IRQ_FLAG.0) to be set to 1 when- should be selected based on the load capacitance as
ever V DVDD drops below the V PFW trip point. Once suggested by the crystal manufacturer.
PWRF has been set to 1 by hardware, it can only be Since noise at XTAL1 and XTAL2 can adversely affect
cleared by the master (or by a system reset). Whenever device timing, the crystal and capacitors should always
PWRF = 1, if the EPWRF interrupt masking bit is also be placed as close as possible to the XTAL1 and
set to 1, the MAXQ3180 drives IRQ low to signal to the XTAL2 pins, with connection traces between the crystal
master that an interrupt condition (in this case, a power- and the device kept as short and direct as possible. In
fail warning) exists and requires attention. multiple layer boards, avoid running other high-speed
digital signals underneath the crystal oscillator circuit if
Clock Sources possible, as this could inject unwanted noise into the
All operations including ADC sampling and SPI com- clock circuit.
munications are synchronized to a single system clock.
This clock can be obtained from any one of three selec- Following power-up or any system reset, the high-fre-
table sources, as shown in Figure 3. quency clock is automatically selected as the system
clock source. However, before this clock can be used

HF
CRYSTAL

CLOCK
GLITCH-FREE

GENERATION
MUX

ENABLE SYSTEM CLOCK

1MHz
INTERNAL
OSCILLATOR

INT/EXT
XTAL IN
RING IN WATCHDOG TIMER
CRYSTAL
EXTCLK
STARTUP TIMER
STOPM CLK
POR RING COUNT ENABLE WATCHDOG RESET

Figure 3. Simplified Clock Sources

18 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
for system execution, a crystal warmup timer must Master Communications

MAXQ3180
count 65,536 cycles of the high-frequency clock. While Before the MAXQ3180 can begin performing electric-
this warmup time period is in effect, execution contin- metering operations, the master must initialize a num-
ues using the internal 1MHz oscillator. Once the ber of configuration parameters. Since the MAXQ3180
65,536-cycle count completes (which requires approxi- does not contain internal nonvolatile memory, these
mately 8.2ms at 8MHz), the device automatically parameters (stored in internal registers) must be set by
switches over to the high-frequency clock. This crystal the master each time a power-up or reset cycle occurs,
warmup timer is also activated upon exit from Stop or each time a switch is made between LOWPM Mode
Mode, since the high-frequency crystal oscillator is shut and Run Mode.
down during Stop Mode. The external master communicates with the MAXQ3180
External High-Frequency Clock over a standard SPI bus, using commands to read and
Instead of using a crystal oscillator to generate the write values to internal registers on the MAXQ3180.
high-frequency clock, it is also possible to input a high- These registers include, among many other items:
frequency clock that has been generated by another • Operating mode settings (Stop Mode, LOWPM
source (such as a digital oscillator IC) directly into the Mode, external clock mode, etc.)
XTAL1 pin of the MAXQ3180. • Status and interrupt flags (power-supply failure, over-
To use an external high-frequency clock as the system current/overvoltage detection, etc.)
clock source, the XTAL1 pin should be used as the • Masking control for interrupts to determine which
clock input and the XTAL2 pin should be left uncon- conditions cause IRQ to be driven low
nected. The master should also shut down the internal
crystal oscillator circuit by setting the EXTCLK bit • Configuration settings for analog channel scanning
(OPMODE0.4) to 1. This bit is only cleared by the • Power pulse output configuration
MAXQ3180 if a power-on or brownout reset occurs and • Filter coefficients and configuration
is unaffected by other resets.
• Read-only registers containing accumulated power
When using an external high-frequency clock, the clock and energy data
signal should be generated by a CMOS driver. If the
clock driver is a TTL gate, its output must be connected As the MAXQ3180 obtains voltage and current mea-
to DVDD through a pullup resistor to ensure that the surements in Run Mode or LOWPM Mode, it accumu-
correct logic levels are generated. To minimize system lates, filters, and performs a number of calculations on
noise in the clock circuitry, the external clock source the collected data. Many of these operations (including
must meet the maximum rise and fall times and the the various filtering stages) are configured by settings
minimum high and low times specified for the clock in registers written by the master. The output results
source in the Electrical Characteristics table. can then be read by the master from various read-only
registers in parallel with the ongoing measurement and
Internal RC Oscillator processing operations.
When the external high-frequency crystal is warming
up, or when the MAXQ3180 is placed into LOWPM SPI Communications Rate and Format
mode, the system clock is sourced from an internal RC The SPI is an interdevice bus protocol that provides
oscillator. This internal oscillator is designed to provide fast, synchronous, full-duplex communications between
the system approximately 1MHz, although the exact a designated master device and one or more slave
frequency varies over temperature and supply voltage. devices. In a MAXQ3180-based design, the
MAXQ3180 would be the slave device connected to a
If no external crystal circuit or high-frequency clock will designated master microcontroller.
be used, the MAXQ3180 can be forced to operate infi-
nitely from the internal oscillator by grounding XTAL1. The external master initiates all communications trans-
This ensures that the crystal warmup count never com- fers. The interrupt request line IRQ, while not technical-
pletes, so the MAXQ3180 runs from the internal oscilla- ly part of the SPI bus interface, is also used for
tor in all active modes. master/slave communications because it allows the
MAXQ3180 to notify the master that an interrupt condi-
tion exists. Some SPI peripherals sacrifice speed in
favor of simulating a half-duplex operation. This is not
the case with the MAXQ3180; it is truly a full-duplex SPI
slave.

______________________________________________________________________________________ 19
 Low-Power, Multifunction, Polyphase AFE
During an SPI transfer, data is simultaneously transmit- inactive clock edge is used to latch the data. When
MAXQ3180

ted and received over two serial data lines (MISO and CKPHA is set to a logic 1, data is sampled on the inac-
MOSI) with respect to a single serial shift clock (SCLK). tive clock edge (clock returning to the idle state). When
The polarity and phase of the serial shift clock are the CKPHA is set to a logic 0, data is sampled on the active
primary components in defining the SPI data transfer clock edge (clock transition to the active state).
format. The polarity of the serial clock corresponds to Together, the CKPOL and CKPHA bits allow four possi-
the idle logic state of the clock line and, therefore, also ble SPI data transfer formats.
defines which clock edge is the active edge. To define Transfers over the SPI interface always start with the
a serial shift clock signal that idles in a logic-low state most significant bit and end with the least significant
(active clock edge = rising), the clock polarity select bit. All SPI data transfers to and from the MAXQ3180
(CKPOL; R_SPICF.0) bit should be configured to a 0, are always 8 bits (one byte) in length. The MAXQ3180
while setting CKPOL = 1 causes the shift clock to idle in SPI interface does not support 16-bit character lengths.
a logic-high state (active clock edge = falling). The
phase of the serial clock selects which edge is used to The default format (upon power-up or system reset) for
sample the serial shift data. The clock phase select the MAXQ3180 SPI interface is represented in
(CKPHA; R_SPICF.1) bit controls whether the active or Figure 4a (CKPOL = 0; CKPHA = 0). In this format, the

SCLK CYCLE #
1 2 3 4 5 6 7 8
(FOR REFERENCE)

SCLK (CKPOL = 0)

SCLK (CKPOL = 1)

MOSI
MSB 6 5 4 3 2 1 LSB
(FROM MASTER)
MISO
MSB 6 5 4 3 2 1 LSB *
(FROM SLAVE)

SSEL (TO SLAVE)

*NOT DEFINED BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.

Figure 4a. SPI Interface Timing (CKPHA = 0)

SCLK CYCLE #
1 2 3 4 5 6 7 8
(FOR REFERENCE)

SCLK (CKPOL = 0)

SCLK (CKPOL = 1)

MOSI
MSB 6 5 4 3 2 1 LSB
(FROM MASTER)
MISO
* MSB 6 5 4 3 2 1 LSB
(FROM SLAVE)

SSEL (TO SLAVE)

*NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER.

Figure 4b. SPI Interface Timing (CKPHA = 1)

20 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
SPI clock idle state is low, and data is shifted in and out Some read-only memory locations in the MAXQ3180

MAXQ3180
on the rising edge of SCLK. Once SPI communication trigger actions within the device to calculate electricity-
with the MAXQ3180 has been established, it is possible metering results on the fly. The specific function and
to alter the CKPOL and CKPHA format settings (as well purpose of RAM and virtual ROM locations are given in
as changing the SSEL signal from active low to active the register map. There are several different categories
high) if desired by writing to the R_SPICF mirror register of internal registers on the MAXQ3180.
and then reading from the special command register • RAM Registers. The values of these registers are
UPD_SFR to copy the R_SPICF value into the internal stored in the internal RAM of the MAXQ3180. Some
SPI configuration register. can be read and written by the master, while others
Whenever the active clock edge is used for sampling are read-only. RAM registers are either 2 or 4 bytes
(CKPHA = 0), the transfer cycle must be started with long (16 or 32 bits), although in some registers not all
assertion of the SSEL signal. This requirement means the bits have defined values. Read/write registers are
that the SSEL signal be deasserted and reasserted generally either status/flag registers (which can be
between successive transfers. Conversely, when the written by either the MAXQ3180 or the master), con-
inactive edge is used for sampling (CKPHA = 1), the figuration registers (which are written by the master
SSEL signal may remain low through successive and read by the MAXQ3180 firmware), or data regis-
transfers, allowing the active clock edge to signal the ters (which are read-only and are written by the
start of a new transfer. MAXQ3180 firmware and read by the master).
The clock rate used for the SPI interface is determined • Virtual Registers. These read-only registers are not
by the bus master, since the MAXQ3180 always oper- stored in RAM; instead, they contain values that are
ates as an SPI slave device. However, the maximum calculated on the fly by the MAXQ3180 firmware
clock rate is limited by the system clock frequency of when the master reads them. These registers are
the MAXQ3180. For proper communications operation, used by the master to obtain values such as phase
the SPI clock frequency used by the master must be A, B, and C active, reactive, and apparent power;
less than or equal to the MAXQ3180’s clock frequency power factor; and RMS voltage and current, which
divided by 4. For example, when the MAXQ3180 is run- are calculated from currently collected data on an
ning at 8MHz, the SPI clock frequency must be 2MHz as-needed basis. Most virtual registers are 8 bytes in
or less. And if the MAXQ3180 is running in LOWPM length.
Mode (or if the crystal is still warming up), the SPI clock • Hardware Registers. These registers control core
frequency must remain at 250kHz or less for proper functions of the MAXQ3180 including the ADC and
communications operation. the SPI slave bus controller. Each of these registers
In addition to limiting the overall SPI bus clock rate, the (R_ACFG, R_ADCRATE, R_ADCACQ, R_SPICF, and
master must also include a communications delay fol- OPMODE0 (bit 4, EXTCLK only)) has a register loca-
lowing each byte transmit/receive cycle. This delay, tion in RAM that “shadows” the value of the hardware
which provides the MAXQ3180 with time to process an register. To read from a hardware register, the mas-
ADC sample, should be a minimum of 400 system ter must first read from the special command register
clocks. With default settings and running at 8MHz, this UPD_MIR (A00h) to copy the values from the hard-
delay time is 50μs. Reducing the system clock frequen- ware registers to the mirror registers in RAM, and
cy to 1MHz (LOWPM mode) would increase this delay then the mirror register in RAM can be read. To write
period by a factor of 8 to 400μs. to a hardware register, the master reverses the
process by writing to the mirror RAM register and
SPI Communications Protocol then reading from the special command register
All transactions between the master and the UPD_SFR (900h) to copy the values from the mirror
MAXQ3180 consist of the master writing to or reading registers to the hardware registers.
from one of the MAXQ3180’s registers. To the host, the
MAXQ3180 looks like a memory array that consists of • Special Command Registers. These registers
both RAM and ROM. This is because the ROM firmware (UPD_SFR and UPD_MIR) do not return meaningful
in the MAXQ3180 reads its operational parameters from data when read but instead trigger an operation.
RAM and places its results in RAM. Consequently, con- Reading UPD_SFR causes values to be copied from
figuring a MAXQ3180 is as simple as performing a the mirror registers to hardware, and reading
block write to its RAM locations. UPD_MIR causes values to be copied from the hard-
ware to mirror registers.

______________________________________________________________________________________ 21
 Low-Power, Multifunction, Polyphase AFE
Every defined register on the MAXQ3180 has a 12-bit cycles when it is receiving a multibyte response to a
MAXQ3180

address (from 0 to 4095). This address is used when request, meeting the “send a byte to get a byte” require-
addressing the register for either a read or write opera- ment. But the MAXQ3180 could require time to calculate
tion. Addresses 0 to 1023 (000h to 3FFh) are used to the result, and thus might not have it ready when the
address RAM registers. Registers with addresses from master sends the dummy byte. For this reason, the
1024 to 4095 (400h to FFFh) are used for virtual regis- MAXQ3180 always sends zero or more bytes of a NAK
ters and special command registers. character (0x4E or ASCII ‘N’) followed by an ACK char-
Each command consists of a read/write command acter (0x41, or ASCII ‘A’) before sending the data.
code, a data length (1, 2, 4, or 8 bytes), a 12-bit regis- If the master is writing 1 or more bytes, it sends the
ter address, and the specified number of data bytes fol- data to be written immediately after sending the com-
lowed optionally by a cyclic redundancy check (CRC). mand. The MAXQ3180 returns ACK (0x41) for each
Since SPI is a full-duplex interface, the master and data byte. It then returns NAK (0x4E) until the write
slave must both transmit the same number of bytes dur- cycle is complete, after which it returns a final ACK.
ing the command. When a multiple-byte register is read Immediately after the final ACK, the MAXQ3180 is
or written (2/4/8 byte length), the least significant byte is ready to begin the next transaction; there is no need to
read or written first in the command. wait for any other event. It is not even necessary to tog-
Every transaction begins with the master sending 2 gle SSEL to begin the next transaction. The MAXQ3180
bytes that contain the command (read or write), the knows that the first transaction is over and is ready for
address to access, and the number of bytes to transfer. the next.
Every SPI peripheral must return 1 byte for every byte it If, for whatever reason, it is necessary to reset the com-
receives. If the master is reading 1 or more bytes from munications between the host and the MAXQ3180 (for
the MAXQ3180, it must send dummy bytes during the

Table 1. Command Format for SPI Register Read

BYTE TRANSFERS BIT DESCRIPTION
Command Code:
00 Read
7:6 01 Reserved
10 Write
11 Reserved
Master sends command;
1st byte Data Length:
Slave sends 0xC1 byte
00 1 Byte
5:4 01 2 Bytes
10 4 Bytes
11 8 Bytes
3:0 MSB portion of data address.
Master sends address;
2nd byte 7:0 LSB portion of data address.
Slave sends 0xC2 byte
Master sends dummy byte; Slave responds with NACK if busy,
Master sends dummy;
or with ACK when processing complete.
Sync bytes Slave sends ACK (0x41) or 7:0
NACK (0x4E) byte
Master must receive ACK, then receive data.
3rd byte Master sends dummy;
7:0 Data, LSB
(1st data byte) Slave sends data
... ... ... ...
Nth byte Master sends dummy;
7:0 Data, MSB
(Last data byte) Slave sends data
Master sends dummy;
(N + 1) byte 7:0 Optional CRC
Slave sends CRC

22 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
Table 2. Command Format for SPI Register Write
BYTE TRANSFERS BIT DESCRIPTION
Command code:
00 Read
7:6 01 Reserved
10 Write
11 Reserved
Master sends command;
1st byte Data Length:
Slave sends 0xC1 byte
00 1 Byte
5:4 01 2 Bytes
10 4 Bytes
11 8 Bytes
3:0 MSB portion of data address.
Master sends address;
2nd byte 7:0 LSB portion of data address.
Slave sends 0xC2 byte
3rd byte Master sends data;
7:0 Data, LSB
(1st data byte) Slave sends ACK (0x41)
... ... ... ...
Nth byte Master sends data;
7:0 Data, MSB
(Last data byte) Slave sends ACK (0x41)
Master sends CRC;
(N + 1) byte 7:0 Optional CRC
Slave sends ACK (0x41)
Master sends dummy byte; Slave responds with NACK if busy,
Master sends dummy;
or with ACK when processing complete.
Sync bytes Slave sends ACK (0x41) or 7:0
NACK (0x4E) byte
Master must receive ACK before starting the next transaction.

example, if synchronization is lost), the host only needs sent by the MAXQ3180. The CRC mode is enabled
to wait for the SPI to time out before restarting commu- when the CRCEN bit is set to 1 in OPMODE1 register.
nication from the first command byte. SPI timeout count Otherwise, the MAXQ3180 assumes no CRC byte is
starts after receiving the first command byte from the used. The 8-bit CRC is calculated for all bytes in a
master (after the 8th SPI clock of the first byte). The transaction, from the first command byte sent by the
count stops and clears after receiving the last byte of a master through the last data byte excluding sync bytes,
transaction (after the 8th SPI clock of the last byte). using the polynomial P = x8 + x5 + x4 + 1. If the trans-
If the timeout count expires (exceeds COM_TIMO) mitted CRC byte does not match the calculated CRC
before the transaction completes, the MAXQ3180 aban- byte (for a write command), the MAXQ3180 ignores the
dons the unfinished transaction and resets the SPI logic command.
to be ready for the next transaction. The default SPI The length of the transfer is defined by the first com-
timeout is 320ms. mand byte and the status of the CRCEN bit in the
Optionally, a CRC byte can be appended to each OPMODE1 register. There is no special synchronization
transaction. For write commands, the CRC byte is sent mechanism provided in this simple protocol. Therefore,
by the master, and for read commands the CRC byte is the master is responsible for sending/receiving the cor-
rect number of bytes. If the master mistakenly sends

______________________________________________________________________________________ 23
 Low-Power, Multifunction, Polyphase AFE
MAXQ3180

READING DATA FROM MAXQ3180 THROUGH SPI INTERFACE

SSEL

SCLK

MOSI 00 01 ADDRESS DUMMY DUMMY DUMMY DUMMY

MISO 0xC1 0xC2 NACK (0x4E) ACK (0x41) DATA LSB DATA MSB

Figure 5. Read SPI Transfer

WRITING DATA TO MAXQ3180 THROUGH SPI INTERFACE

SSEL

SCLK

MOSI 10 01 ADDRESS DATA LSB DATA MSB DUMMY DUMMY

MISO 0xC1 0xC2 ACK (0x41) ACK (0x41) NACK (0x4E) ACK (0x41)

Figure 6. Write SPI Transfer

more bytes than are required by the current command, To read any virtual power registers, the host must first
the extra bytes are either ignored (if the MAXQ3180 is confirm that the DSPRDY bit of the IRQ_FLAG register
busy processing the previous command) or are inter- is set, which indicates the last DSP cycle has complet-
preted as the beginning of a new command. If the mas- ed, then proceed to reading all the desired virtual
ter sends fewer bytes than are required by the current power registers. For best communication efficiency, it is
command, the MAXQ3180 waits for SPI timeout, then recommended to complete reading the virtual power
drops the transaction and resets the communication registers before reading other registers. Virtual power
channel. The duration of the timeout can be configured register reads must be completed within 50% of DSP
through the COM_TIMO register. cycle time, from the moment the DSPRDY bit is set. Do
Figures 5 and 6 show typical 2-byte reading and writing not forget to clear the DSPRDY bit, otherwise, host soft-
transfers (without CRC byte). ware is not able to detect the completion of the new
DSP cycle. The MAXQ3180 does not clear the bit; it
Host Software Design only sets the bit whenever a DSP cycle processing is
Individual message bytes sent through the SPI are completed. Users can clear the bit directly after the
processed in a software routine contained in the ROM confirmation that the bit is set. Clearing the DSPRDY bit
firmware. For this reason, it is necessary to provide a does not affect the DSP processing. It is strongly rec-
delay between successive bytes. This byte spacing ommended that CRC be enabled for both read and
must be no less than 400 system clocks to ensure that write to achieve reliable communications.
the MAXQ3180 has a chance to read and process the
byte before the arrival of the next one.

24 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
WRITE MAXQ3180
READ MAXQ3180

SPI TIMEOUT (320ms) SEND COMMAND BYTE 1

SPI TIMEOUT (320ms) SEND COMMAND BYTE 1

N
N GET 0xC1?
GET 0xC1?

DELAY > 400 SYSCLK

DELAY > 400 SYSCLK

SEND COMMAND BYTE 2

SEND COMMAND BYTE 2

N
N GET 0xC2?
GET 0xC2?

DELAY > 400 SYSCLK

DELAY > 400 SYSCLK

SEND DATA BYTE

SEND 0x00

N
Y GET 0x41?
GET 0x4E?

N
N DONE?
GET 0x41?

DELAY > 400 SYSCLK

DELAY > 400 SYSCLK

SEND 0x00
SEND 0x00

Y
GET DATA BYTE GET 0x4E?

N
DONE? N
GET 0x41?

EXIT
EXIT

Figure 7. Flowchart for Reading from MAXQ3180 Figure 8. Flowchart for Writing to MAXQ3180

Register Set The virtual registers contain calculated values derived

from one or more real registers. They are calculated at
Data and device command and control information are
the time they are requested, and thus can involve addi-
located in internal registers. Registers range from 8 to 64
tional time to return a value. Most virtual registers are 8
bits in length and are divided into RAM-based registers
bytes in length and are delivered least significant byte
and virtual registers. The RAM-based registers contain
first.
both operating parameters and measurement results.

______________________________________________________________________________________ 25
 Low-Power, Multifunction, Polyphase AFE
MAXQ3180

Table 3. RAM Register Map

x0h x1h x2h x3h x4h x5h x6h x7h x8h x9h xAh xBh xCh xDh xEh xFh
OP OP OP SCAN SCAN SCAN SCAN SCAN SCAN SCAN SCAN
0x00 STATUS IRQ_FLAG IRQ_MASK
MODE0 MODE1 MODE2 _IA _VA _IC _VC _IB _VB _IN _TE
PLSCFG PLSCFG
0x01 AUX_CFG SYS_KHZ VOLT_CC AMP_CC PWR_CC ENR_CC CYCNT
1 2
0x02 PLS1_WD THR1 PLS2_WD THR2 REJ_NS AVG_NS
0x03 AVG_C HPF_C B0FUND A1FUND B0HARM A1HARM
0x04 NS OCLVL OVLVL UVLVL NOLOAD R_ACFG R_ADCRATE
R_
0x05 R_ADCACQ NZX_TIMO COM_TIMO ACC_TIMO ZC_LPF I1THR I2THR
SPICF
0x06 CHKSUM LINEFR
0x11 N.IRMS
0x12 N.I_GAIN
PHASE A CALIBRATION AND STATUS REGISTERS
0x13 A.I_GAIN A.V_GAIN A.E_GAIN A.EF_GAIN A.OFFS_HI A.GAIN_LO A.OFFS_LO A.PA0
A. A. A. A.
0x14 A.PA1 A.PA2
FLAGS MASK EOVER EFOVER
PHASE B CALIBRATION AND STATUS REGISTERS
0x21 B.I_GAIN B.V_GAIN
0x22 B.E_GAIN B.EF_GAIN B.OFFS_HI B.GAIN_LO B.OFFS_LO B.PA0 B.PA1 B.PA2
B. B. B. B.
0x23
FLAGS MASK EOVER EFOVER
PHASE C CALIBRATION AND STATUS REGISTERS
0x30 C.I_GAIN C.V_GAIN C.E_GAIN C.EF_GAIN
C. C. C. C.
0x31 C.OFFS_HI C.GAIN_LO C.OFFS_LO C.PA0 C.PA1 C.PA2
FLAGS MASK EOVER EFOVER
0x32
PHASE A MEASUREMENT REGISTERS*
0x1C A.PF A.VRMS A.IRMS
0x1D A.ACT A.REA A.APP A.ACTF
0x1E A.REAF A.APPF A.EAPOS A.EANEG
0x1F A.ERPOS A.ERNEG A.ES A.EAFPOS
0x20 A.EAFNEG A.ERFPOS A.ERFNEG A.ESF
PHASE B MEASUREMENT REGISTERS*
0x2B B.PF B.VRMS B.IRMS B.ACT
0x2C B.REA B.APP B.ACTF B.REAF
0x2D B.APPF B.EAPOS B.EANEG B.ERPOS
0x2E B.ERNEG B.ES B.EAFPOS B.EAFNEG
0x2F B.ERFPOS B.ERFNEG B.ESF
PHASE C MEASUREMENT REGISTERS*
0x39 C.PF
0x3A C.VRMS C.IRMS C.ACT C.REA
0x3B C.APP C.ACTF C.REAF C.APPF
0x3C C.EAPOS C.EANEG C.ERPOS C.ERNEG
0x3D C.ES C.EAFPOS C.EAFNEG C.ERFPOS
0x3E C.ERFNEG C.ESF
*Read-only.

26 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
Table 4. Virtual Register Map
x0 x1 x2 x3 x4 x5 x6 x7
0x80 PWRP.A PWRP.B PWRP.C PWRP.T
0x81 PWRQ.A PWRQ.B PWRQ.C PWRQ.T
0x82 PWRS.A PWRS.B PWRS.C PWRS.T
0x83 V.HARM V.A V.B V.C
0x84 I.N, I.HARM I.A I.B I.C
0x85 HARM_NF VBPH VCPH
0x86 PF.T
0x87 ENRS.A ENRS.B ENRS.C ENRS.T
0x88 PWRPF.A PWRPF.B PWRPF.C PWRPF.T
0x89 PWRQF.A PWRQF.B PWRQF.C PWRQF.T
0x8A PWRSF.A PWRSF.B PWRSF.C PWRSF.T
0x8B ENRSF.A ENRSF.B ENRSF.C ENRSF.T
0x8C ENRP.A ENRP.B ENRP.C ENRP.T
0x8D ENRQ.A ENRQ.B ENRQ.C ENRQ.T
0x8E ENRPF.A ENRPF.B ENRPF.C ENRPF.T
0x8F ENRQF.A ENRQF.B ENRQF.C ENRQF.T
SPECIAL FUNCTION REGISTERS
ENTER
0xC0 DSPVER RAWTEMP ENTER STOP EXIT LOWPM
LOWPM
Note: All virtual registers are read-only.

______________________________________________________________________________________ 27
 Low-Power, Multifunction, Polyphase AFE
RAM-Based Registers
MAXQ3180

The RAM-based registers contain both operating parameters and measurement results. They are divided into a num-
ber of categories that are described in the following sections.
General Operating Registers
Global Status Register (STATUS) (0x000)
Bit: 7 6 5 4 3 2 1 0
Name: — CROFF PORF WDTR — PHSEQ REVCFQ REVCFP
Reset: 0 0 0 0 0 0 0 0

This register contains bits that reflect the global status of the device.

BIT NAME FUNCTION

7, 3 — Reserved.
When set, the high-frequency crystal has failed and the MAXQ3180 is operating from its internal ring
6 CROFF oscillator. Under these circumstances, energy accumulation is not accurate and the SPI bus does not
operate at full speed.

When set, the last reset was due to power-on-reset. Host should clear this bit to allow the next POR
5 PORF
detection.
When set, the last reset was caused by expired watchdog. The bit should be cleared (set to 0) by the
4 WDTR
host to allow the next watchdog reset detection.

0 = The sequence of voltages presented to the voltage inputs is (-A-B-C-).

2 PHSEQ 1 = The sequence of voltages presented to the voltage inputs is reversed (-A-C-B-).
This bit is meaningful only for connection systems that include all three voltages.

0 = The quantity being output on the CFQ pin is positive (direct).

1 REVCFQ
1 = The quantity being output on the CFQ pin is negative (reverse).
0 = The quantity being output on the CFP pin is positive (direct).
0 REVCFP
1 = The quantity being output on the CFP pin is negative (reverse).

28 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Operating Mode Register 0 (OPMODE0) (0x001)

MAXQ3180
Bit: 7 6 5 4 3 2 1 0
Name: — — — EXTCLK SWRES DSPDIS LOWPM —
Reset: 0 0 0 0 0 0 0 0

BIT NAME FUNCTION

7:5, 0 — Reserved.
When set, the high-frequency crystal oscillator is disabled and the XTAL1 pin is configured to be a
4 EXTCLK clock input for the device. This is used when it is desired to operate multiple devices from the same
clock source for purposes of maintaining synchronization.

When set, forces the internal software to restart from the reset vector. This has the same effect as a
3 SWRES power-on reset, but does not specifically reset any hardware peripherals. This bit is automatically
cleared after the reset.

When set, disables the signal processing software routines. The CPU continues to run at full speed,
2 DSPDIS
but only to perform supervisory functions (such as servicing the SPI port).

When set, causes the CPU to switch its clock source from the external crystal to an internal ring oscillator
that operates at a nominal frequency of 1MHz. In this mode, the CPU continues to run, but the host must
1 LOWPM
reconfigure the parameters configured for crystal operation (such as filter settings, timeouts, and pulse
widths).

Operating Mode Register 1 (OPMODE1) (0x002)

Bit: 7 6 5 4 3 2 1 0
Name: — — — — CRCEN POPOL CONCFG
Reset: 0 0 0 0 0 0 0x0

BIT NAME FUNCTION

7:4 — Reserved.
If set, a 1-byte CRC is appended to the end of each SPI read and is expected at the end of each SPI
3 CRCEN write. See the SPI Communication Protocols section for details about how to use the CRC byte for error
checking on the SPI bus.

This bit sets the polarity of the output pulse generators. If clear, the pulse outputs are active low; that
is, they remain in the high state until a pulse event occurs, at which time they switch low for one
2 POPOL pulse-width interval before reverting to the high state. If set, the pulse outputs are active high; that is,
they remain in the low state until a pulse event occurs, at which time they switch to the high state for
one pulse-width interval before reverting to the low state.

______________________________________________________________________________________ 29
 Low-Power, Multifunction, Polyphase AFE
Operating Mode Register 1 (OPMODE1) (0x002) (continued)
MAXQ3180

BIT NAME FUNCTION

These bits determine how power is calculated on each of the three phases.
V

I
Use this configuration when the load is
connected in a wye arrangement and
neutral is connected to MAXQ3180 ground, I I
PA = IA x VA or when the load is connected in a delta
V V
00 PB = IB x VB arrangement and isolated voltage and
PC = IC x VC current sensors are used. This
arrangement measures power in each load
branch rather than power in each source V I V
branch.
I

I V
Use this configuration when the load is
connected in a four-wire delta
PA = IA x VA
arrangement. In this arrangement, the BC
01 PB = IB x (-VC)
1:0 CONCFG leg is split and VB-N is expected to be
PC = IC x VC
equal to -VC-N. Voltages are referenced to
neutral.
I I
V V

Use this configuration when the load is

PA = IA x VA connected in a four-wire wye arrangement, I N
10 PB = IB x (-VA - VC) but only two voltage sensors are
PC = IC x VC available. When connected in this way,
phase B is assumed to be ground. I I
V V

V
Use this configuration when the load is
connected as a three-wire delta and it is
PA = IA x VA desired to measure the voltage and current I
11 PB = IB x (VA - VC) inside the delta legs, but to calculate the
I
PC = IC x VC power in each of the source circuits. When
connected this way, source phase B is I
considered ground. V

30 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Operating Mode Register 2 (OPMODE2) (0x003)

MAXQ3180
Bit: 7 6 5 4 3 2 1 0
Name: — DHARA DFUNA DFUN LINFRM WIRSYS APPSEL
Reset: 0 0 0 0 0 0 0 0

BIT NAME FUNCTION

7 — Reserved.
When set, disables automatic determination of the filter parameters for the harmonic filter coefficient. If
set by the host software, the host must set a value in the A1HARM filter coefficient register to
6 DHARA establish the operating frequency of this filter if harmonic-mode calculations are used. When cleared,
the MAXQ3180 automatically determines the value of the harmonic-filter coefficient based on the
measured line frequency and the harmonic-order requested (AUX_CFG.ORDH).

When set, disables automatic determination of the filter parameters for the fundamental-mode filter
described above. If set by the host software, the host must set a value in the A1FUND filter coefficient
5 DFUNA register to establish the operating frequency of this filter if fundamental-mode calculations are used.
When clear, the MAXQ3180 automatically determines the value of the fundamental-mode filter
coefficient based on the measured line frequency.
When set, fundamental-mode calculations are disabled. Fundamental-mode calculations provide
information about power and energy that are consumed only at the fundamental line frequency apart
from any harmonics that could be present. Setting this bit disables all fundamental frequency registers
4 DFUN
but allows the MAXQ3180 to calculate other parameters at a higher rate. Set this bit when (1)
fundamental mode values do not need to be read, and (2) R_ADCRATE needs to be reduced below its
default value.

Selects the current linearity offset calibration method. See the Calibrating Current Offset section for
more information.
3 LINFRM
0 = IRMS 2 + OFFS
1 = IRMS + OFFS

These bits select the coefficient used in calculating apparent power.

00 = 1-phase, 3-wire (1P3W), or 3-phase, 4-wire (3P4W) (C = 1)
01 = 3-phase, 3-wire (3P3W) (C =
3/2)
10 = three voltages, three currents (3V3A) (C =
3/3)

2:1 WIRSYS VAB IA

3P3W Wiring (01) IC

VCB

______________________________________________________________________________________ 31
 Low-Power, Multifunction, Polyphase AFE
Operating Mode Register 2 (OPMODE2) (0x003) (continued)
MAXQ3180

BIT NAME FUNCTION

V

IA N
3P4W Wiring (00)

IB IC

VB V

VAB IA VAC

3V3A (10) IB IC
2:1 WIRSYS

VBC

VAN

IA

1P3W (00)
N
IB
VBN

Selects the mechanism to use for calculating apparent power.

Apparent power is calculated by multiplying, on a per-DSP cycle basis, the
0 APPSEL 0: S = VRMS x IRMS
product of the RMS volts and RMS amps.
1: S = P 2 + Q2 Apparent power is calculated by finding the length of the power vector.

32 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Global Interrupt Registers

MAXQ3180
Interrupt Request Flag Register (IRQ_FLAG) (0x004)
Bit: 15 14 13 12 11 10 9 8
Name: DSPOR DSPRDY DCHR DCHA NOZX UV OV OC
Reset: 0 0 0 0 0 0 0 0

Bit: 7 6 5 4 3 2 1 0
Name: — — — — — EOVF CHSCH PWRF
Reset: 0 0 0 0 0 0 0 0

The interrupt request flag register contains bits that indicate the reason the IRQ pin has become active. The active
bit must be cleared by the host to avoid continuing firing of the interrupt by the MAXQ3180.

BIT NAME FUNCTION

When set, the DSP was unable to complete processing one cycle when another cycle was due to
begin. This indicates that the R_ADCRATE is set too low, and that samples are arriving more quickly
15 DSPOR
than they can be processed. Either increase the value of the R_ADCRATE register or set the DFUN bit
in the OPMODE2 register to disable fundamental frequency calculations to reduce the load on the DSP.
14 DSPRDY Set when the DSP cycle completes.
When set, the direction of reactive energy flow has changed (that is, from capacitive to inductive or
13 DCHR
from inductive to capacitive).
When set, the direction of real energy flow has changed (that is, from toward the load to away from the
12 DCHA
load, or from away from the load to toward the load).
When set, the MAXQ3180 has failed to detect zero crossings on one or more voltage channels for the
11 NOZX
time defined by the NZX_TIMO register.
When set, the absolute instantaneous voltage level in one or more voltage channels failed to exceed
10 UV
the trip level set in the UVLVL (Undervoltage Level) register for one DSP cycle.
When set, the absolute instantaneous voltage level in one or more voltage channels has exceeded the
9 OV
trip level set in the OVLVL (Overvoltage Level) register.
When set, the absolute instantaneous current in one or more current channels has exceeded the trip
8 OC
level set in the OCLVL (Overcurrent Level) register.
7:3 — Reserved.
2 EOVF When set, one or more energy accumulators have an MSB overflow condition.
When set, indicates a change of the CHKSUM. The CHKSUM is computed over the configuration and
1 CHSCH calibration data. The host should review a change in CHKSUM because any change in the
configuration or calibration data affects the metering operation and accuracy.

When set, a power-supply failure is imminent and the supervisory processor should begin taking steps
0 PWRF
to save its state and prepare for a loss of power.

______________________________________________________________________________________ 33
 Low-Power, Multifunction, Polyphase AFE
Interrupt Mask Register (IRQ_MASK) (0x006)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: EDSPOR EDSPRDY EDCHR EDCHA ENOZX EUV EOV EOC
Reset: 0 0 0 0 0 0 0 0

Bit: 7 6 5 4 3 2 1 0
Name: — — — — — EEOVF ECHSCH EPWRF
Reset: 0 0 0 0 0 0 0 0

BIT NAME FUNCTION

15 EDSPOR When set, this flag causes the IRQ pin to become active.
14 EDSPRDY When set, this flag causes the IRQ pin to become active.
When set, this flag causes the IRQ pin to become active when the direction of reactive energy flow has
13 EDCHR
been observed to have changed (that is, from capacitive to inductive or from inductive to capacitive).

When set, this flag causes the IRQ pin to become active when the direction of real energy flow has
12 EDCHA been observed to have changed (that is, from toward the load to away from the load, or from away from
the load to toward the load).

When set, this flag causes the IRQ pin to become active when the MAXQ3180 has failed to detect zero
11 ENOZX
crossings on one or more voltage channels for at least one DSP cycle.

When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage
10 EUV level in one or more voltage channels failed to exceed the trip level set in the UVLVL (Undervoltage
Level) register for one DSP cycle.

When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage
9 EOV level in one or more voltage channels has exceeded the trip level set in the OVLVL (Overvoltage Level)
register.

When set, this flag causes the IRQ pin to become active when absolute instantaneous current in one
8 EOC
or more current channels has exceeded the trip level set in the OCLVL (Overcurrent Level) register.
7:3 — Reserved.
When set, this flag causes the IRQ pin to become active when one or more energy accumulators have
2 EEOVF
an overflow condition from their MSB.
1 ECHSCH When set, this flag enables the IRQ pin to become active when a CHKSUM change is detected.
When set, this flag causes the IRQ pin to become active when a power-supply failure is imminent and
0 EPWRF
the supervisory processor should begin taking steps to save its state and prepare for a loss of power.

34 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Meter Pulse Configuration

MAXQ3180
Pulse Configuration—CFP Output (PLSCFG1) (0x01E)
Bit: 7 6 5 4 3 2 1 0
Name: QNSEL PHASEC PHASEB PHASEA
Reset: 0x0 0 0 0

This register selects which phases are included in the CFP pulse output and also selects which quantity is accumu-
lated to drive the pulse output.

BIT NAME FUNCTION

CFP Pulse Output Source Select. This five-bit field determines what meter value will be accumulated in
each of the phases to produce the CFP pulse output. All other values are reserved.
00000 = Net real energy
00001 = Absolute real energy
00010 = Net reactive energy
00011 = Absolute reactive energy
00100 = Apparent energy
7:3 QNSEL 00110 = IRMS
00111 = VRMS
01000 = Real energy delivered to load
01001 = Real energy delivered to line
01010 = Reactive energy, quadrant I
01011 = Reactive energy, quadrant II
01100 = Reactive energy, quadrant III
01101 = Reactive energy, quadrant IV
2 PHASEC CFP Phase C Inclusion. When this bit is set, phase C is included in CFP pulse generation.
1 PHASEB CFP Phase B Inclusion. When this bit is set, phase B is included in CFP pulse generation.
0 PHASEA CFP Phase A Inclusion. When this bit is set, phase A is included in CFP pulse generation.

______________________________________________________________________________________ 35
 Low-Power, Multifunction, Polyphase AFE
Pulse Configuration—CFQ Output (PLSCFG2) (0x01F)
MAXQ3180

Bit: 7 6 5 4 3 2 1 0
Name: QNSEL PHASEC PHASEB PHASEA
Reset: 0x0 0 0 0

This register selects which phases are included in the CFQ pulse output and also selects which quantity is accumu-
lated to drive the pulse output.

BIT NAME FUNCTION

CFQ Pulse Output Source Select. This five-bit field determines what meter value is accumulated in
each of the phases to produce the CFQ pulse output. All other values are reserved.
00000 = Net real energy
00001 = Absolute real energy
00010 = Net reactive energy
00011 = Absolute reactive energy
00100 = Apparent energy
7:3 QNSEL 00110 = IRMS
00111 = VRMS
01000 = Real energy delivered to load
01001 = Real energy delivered to line
01010 = Reactive energy, quadrant I
01011 = Reactive energy, quadrant II
01100 = Reactive energy, quadrant III
01101 = Reactive energy, quadrant IV
2 PHASEC CFQ Phase C Inclusion. When this bit is set, phase C is included in CFQ pulse generation.
1 PHASEB CFQ Phase B Inclusion. When this bit is set, phase B is included in CFQ pulse generation.
0 PHASEA CFQ Phase A Inclusion. When this bit is set, phase A is included in CFQ pulse generation.

CFP Pulse Width (PLS1_WD) (0x020)

Bit: 15 14 13 12 11 10 9 8
Name: CFP Pulse-Width High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: CFP Pulse-Width Low Byte
Reset: 0x9C

This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the
active state. This value is given in ADC frame times (about 320μs). The default value of 0x9C (156 decimal) provides
a pulse width of about 50ms.

36 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
CFP Pulse Threshold (THR1) (0x022)

MAXQ3180
Bit: 31 30 29 28 27 26 25 24
Name: THR1 Byte 3
Reset: 0x00

Bit: 23 22 21 20 19 18 17 16
Name: THR1 Byte 2
Reset: 0x10

Bit: 15 14 13 12 11 10 9 8
Name: THR1 Byte 1
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: THR1 Byte 0
Reset: 0x00

This register designates the threshold of the CFP pulse. This value is used to set the meter constant for the CFP
pulse output. When the CFP pulse accumulator exceeds the value set in this register, the CFP pulse output is activat-
ed and the CFP pulse accumulator is reduced by the amount in this register.

CFQ Pulse Width (PLS2_WD) (0x026)

Bit: 15 14 13 12 11 10 9 8
Name: CFQ Pulse-Width High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: CFQ Pulse-Width Low Byte
Reset: 0x9C

This register designates the width of the CFQ pulse; that is, the duration of the period that the CFQ pulse is in the
active state. This value is given in ADC frame times (about 320μs). The default value of 0x9C (156 decimal) provides
a pulse width of about 50ms.

______________________________________________________________________________________ 37
 Low-Power, Multifunction, Polyphase AFE
CFQ Pulse Threshold (THR2) (0x028)
MAXQ3180

Bit: 31 30 29 28 27 26 25 24
Name: THR2 Byte 3
Reset: 0x00

Bit: 23 22 21 20 19 18 17 16
Name: THR2 Byte 2
Reset: 0x10

Bit: 15 14 13 12 11 10 9 8
Name: THR2 Byte 1
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: THR2 Byte 0
Reset: 0x00

This register designates the threshold of the CFQ pulse. This value is used to set the meter constant for the CFQ
pulse output. When the CFQ pulse accumulator exceeds the value set in this register, the CFQ pulse output is acti-
vated and the CFQ pulse accumulator is reduced by the amount in this register.

Calibration Registers
Current Gain, Phase X = A/B/C/N (X.I_GAIN) (A: 0x130, B: 0x21C, C: 0x308, N: 0x12E)
Bit: 15 14 13 12 11 10 9 8
Name: Current Gain Coefficient High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Current Gain Coefficient Low Byte
Reset: 0x00

This register contains gain coefficient for phase X current channel. The raw values are taken from the selected mea-
surement quantity and scaled by the factor:

X.I _ GAIN
2 14
Note: Bit 15 of this register must be set to zero for correct operation.

38 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Voltage Gain, Phase X = A/B/C (X.V_GAIN) (A: 0x132, B: 0x21E, C: 0x30A)

MAXQ3180
Bit: 15 14 13 12 11 10 9 8
Name: Voltage Gain Coefficient High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Voltage Gain Coefficient Low Byte
Reset: 0x00

This register contains gain coefficient for phase X voltage channel. The raw values are taken from the selected mea-
surement quantity and scaled by the factor:
X.V _ GAIN
2 14
Note: Bit 15 of this register must be set to zero for correct operation.

Energy Gain, Phase X = A/B/C (X.E_GAIN) (A: 0x134, B: 0x220, C: 0x30C)

Bit: 15 14 13 12 11 10 9 8
Name: Energy Gain Coefficient High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Energy Gain Coefficient Low Byte
Reset: 0x00

This register contains gain coefficient for phase X energy. The raw values are taken from the selected measurement
quantity and scaled by the factor:
X.E _ GAIN
2 14
Note: Bit 15 of this register must be set to zero for correct operation.

Phase-Angle Compensation, High Range, Phase X = A/B/C (X.PA0)

(A: 0x13E, B: 0x22A, C: 0x316)
Bit: 15 14 13 12 11 10 9 8
Name: Phase-Angle Offset High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Phase-Angle Offset Low Byte
Reset: 0x00

This signed register contains the angle as a fraction of one radian to add to the measured phase angle when the
measured current is above the value given in I1THR. This signed value ranges from -0.5 radian (at a value of
0x8000) to +(0.5 - 2-16) radian (at a value of 0x7FFF).

______________________________________________________________________________________ 39
 Low-Power, Multifunction, Polyphase AFE
Phase-Angle Compensation, Medium Range, Phase X = A/B/C (X.PA1)
MAXQ3180

(A: 0x140, B: 0x22C, C: 0x318)

Bit: 15 14 13 12 11 10 9 8
Name: Phase-Angle Offset High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Phase-Angle Offset Low Byte
Reset: 0x00

This signed register contains the angle, as a fraction of one radian, to add to the measured phase angle when the
measured current is between the values given in I1THR and I2THR. This signed value ranges from -0.5 radian (at a
value of 0x8000) to +(0.5 - 2-16) radian (at a value of 0x7FFF).

Phase-Angle Compensation, Low Range, Phase X = A/B/C (X.PA2)

(A: 0x142, B: 0x22E, C: 0x31A)
Bit: 15 14 13 12 11 10 9 8
Name: Phase-Angle Offset High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Phase-Angle Offset Low Byte
Reset: 0x00

This signed register contains the angle, as a fraction of one radian, to add to the measured phase angle when the
measured current is below the value given in I2THR. This signed value ranges from -0.5 radian (at a value of 0x8000)
to +(0.5 - 2-16) radian (at a value of 0x7FFF).

Limit Registers
Overcurrent Level (OCLVL) (0x044)
Bit: 15 14 13 12 11 10 9 8
Name: Overcurrent Level High Byte
Reset: 0xFF

Bit: 7 6 5 4 3 2 1 0
Name: Overcurrent Level Low Byte
Reset: 0xFF

This register specifies the fraction of full-scale current that is declared to be an overcurrent condition. When X.IRMS
exceeds this level for one DSP cycle, the OCF flag in the X.FLAGS register is set. If the OCM flag is set in the
X.MASK register, setting the OCF flag will cause the interrupt bit OC to be set in the IRQ_FLAG register. If the inter-
rupt is enabled, the interrupt pin is driven active. Full scale is represented by 0x10000. The maximum value for this
register is 0xFFFF.

40 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Overvoltage Level (OVLVL) (0x046)

MAXQ3180
Bit: 15 14 13 12 11 10 9 8
Name: Overvoltage Level High Byte
Reset: 0xFF

Bit: 7 6 5 4 3 2 1 0
Name: Overvoltage Level Low Byte
Reset: 0xFF

This register specifies the fraction of full-scale voltage that is declared to be an overvoltage condition. When X.VRMS
exceeds this level for one DSP cycle, the OVF flag in the X.FLAGS register is set. If the OVM flag is set in the
X.MASK register, setting the OVF flag will cause the interrupt bit OV to be set in the IRQ_FLAG register. If the inter-
rupt is enabled, the interrupt pin is driven active. Full scale is represented by 0x10000. The maximum value for this
register is 0xFFFF.

Undervoltage Level (UVLVL) (0x048)

Bit: 15 14 13 12 11 10 9 8
Name: Undervoltage Level High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Undervoltage Level Low Byte
Reset: 0x00

This register specifies the fraction of full-scale voltage below which an undervoltage condition is declared. When
X.VRMS falls below this level for one DSP cycle, the UVF flag in the X.FLAGS register is set. If the UVM flag is set in
the X.MASK register, setting the UVF flag will cause the interrupt bit UV to be set in the IRQ_FLAG register. If the
interrupt is enabled, the interrupt pin is driven active. Full scale is represented by 0x10000. The maximum value for
this register is 0xFFFF.

No-Load Level (NOLOAD) (0x04A)

Bit: 15 14 13 12 11 10 9 8
Name: No-Load Level High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: No-Load Level Low Byte
Reset: 0x03

This register specifies the fraction of full-scale current below which a no-load condition is declared. When X.IRMS
falls below this level, the MAXQ3180 no longer accumulates power for phase X. Full scale is represented by
0x10000. The maximum value for this register is 0xFFFF.

______________________________________________________________________________________ 41
 Low-Power, Multifunction, Polyphase AFE
Phase Status Registers
MAXQ3180

Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C)

Bit: 7 6 5 4 3 2 1 0
Name: — — DCHRF DCHAF NOZXF UVF OVF OCF
Reset: 0 0 0 0 0 0 0 0

The X.FLAGS register contains condition flags that relate to the function of phase X (A/B/C) measurements. Once
set, these bits can be cleared only by the host.

BIT NAME FUNCTION

7:6 — Reserved.
Reactive Energy Direction Change. Set when the direction of reactive power flow changes (from
5 DCHRF capacitive to inductive or from inductive to capacitive). If the DCHRM bit is set, this bit sets the DCHR
flag in the IRQ_FLAG register.

Real Energy Direction Change. Set when the direction of real power flow changes (from toward the load
4 DCHAF to toward the line, or from toward the line to toward the load). If the DCHAM bit is set, this bit sets the
DCHA flag in the IRQ_FLAG register.
No-Zero Crossing. Set when the voltage waveform in phase X fails to exhibit a zero crossing during
3 NOZXF NZX_TIMO of the ADC sample periods. If the NOZXM bit is set, this bit sets the NOZX flag in the
IRQ_FLAG register.
Undervoltage. Set when the RMS voltage in phase X falls below the undervoltage threshold set in
2 UVF
UVLVL. If the UVM bit is set, this bit sets the UV flag in the IRQ_FLAG register.
Overvoltage. Set when the RMS voltage in phase X exceeds the overvoltage threshold set in OVLVL. If
1 OVF
the OVM bit is set, this bit sets the OV flag in the IRQ_FLAG register.
Overcurrent. Set when the RMS current in phase X exceeds the overcurrent threshold set in OCLVL. If
0 OCF
the OCM bit is set, this bit sets the OC flag in the IRQ_FLAG register.

42 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Interrupt Mask, Phase X = A/B/C (X.MASK) (A: 0x145, B: 0x231, C: 0x31D)

MAXQ3180
Bit: 7 6 5 4 3 2 1 0
Name: DIR_R DIR_A DCHRM DCHAM NOZXM UVM OVM OCM
Reset: 0 0 0 0 0 0 0 0

BIT NAME FUNCTION

Reactive Energy Direction Status
7 DIR_R 0 = positive
1 = negative

Active Energy Direction Status

6 DIR_A 0 = positive
1 = negative

Reactive Energy Direction Change Mask. If set, a change in reactive power direction on phase X
5 DCHRM
causes the DCHR flag in the IRQ_FLAG register to be set.
Real Energy Direction Change Mask. If set, a change in real power direction on phase X causes the
4 DCHAM
DCHA flag in the IRQ_FLAG register to be set.
No-Zero Crossing Mask. If set, a no-zero crossing on phase X causes the NOZX flag in the IRQ_FLAG
3 NOZXM
register to be set.
Undervoltage Mask. If set, an undervoltage condition on phase X causes the UV flag in the IRQ_FLAG
2 UVM
register to be set.
Overvoltage Mask. If set, an overvoltage condition on phase X causes the OV flag in the IRQ_FLAG
1 OVM
register to be set.
Overcurrent Mask. If set, an overcurrent condition on phase X causes the OC flag in the IRQ_FLAG
0 OCM
register to be set.

Energy Overflow Flags, Phase X = A/B/C (X.EOVER) (A: 0x146, B: 0x232, C: 0x31E)
Bit: 7 6 5 4 3 2 1 0
Name: — — — SOV RNOV RPOV ANOV APOV
Reset: 0 0 0 0 0 0 0 0

These bits indicate that an overflow condition has occurred on an energy accumulator. An overflow condition is not
an error condition. Rather, it simply indicates that the value in the energy accumulator could be smaller than the pre-
vious reading due to the overflow in the counter. To obtain the actual energy usage since the previous reading,
0x100000000 must be added to the difference. These bits, once set, can be cleared only by the host.

BIT NAME FUNCTION

7:5 — Reserved.
4 SOV When set, indicates an overflow condition on the apparent energy accumulator.
3 RNOV When set, indicates an overflow condition on the reactive negative energy accumulator.
2 RPOV When set, indicates an overflow condition on the reactive positive energy accumulator.
1 ANOV When set, indicates an overflow condition on the real negative energy accumulator.
0 APOV When set, indicates an overflow condition on the real positive energy accumulator.

______________________________________________________________________________________ 43
 Low-Power, Multifunction, Polyphase AFE
Measurements
MAXQ3180

Line Frequency (LINEFR) (0x062)

Bit: 15 14 13 12 11 10 9 8
Name: Line Frequency High Byte
Reset:

Bit: 7 6 5 4 3 2 1 0
Name: Line Frequency Low Byte
Reset:

Line frequency, LSB = 0.001Hz.

Power Factor, Phase X = A/B/C (X.PF) (A: 0x1C6, B: 0x2B2, C: 0x39E)

Bit: 15 14 13 12 11 10 9 8
Name: Power Factor High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Power Factor Low Byte
Reset: 0x00

Power factor of phase A/B/C, LSB = 1/214. Note that the power factors are signed integers, and a negative value
indicates a reversed power flow direction.

RMS Voltage, Phase X = A/B/C (X.VRMS) (A: 0x1C8, B: 0x2B4, C: 0x3A0)

Bit: 31 30 29 28 27 26 25 24
Name: RMS Voltage Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: RMS Voltage Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: RMS Voltage Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: RMS Voltage Byte 0

This register provides the raw RMS voltage over the most recent DSP cycle, LSB = VFS/224.

44 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
RMS Current, Phase X = A/B/C (X.IRMS) (A: 0x1CC, B: 0x2B8, C: 0x3A4)

MAXQ3180
Bit: 31 30 29 28 27 26 25 24
Name: RMS Current Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: RMS Current Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: RMS Current Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: RMS Current Byte 0

This register provides the raw RMS current over the most recent DSP cycle, LSB = IFS/224.

Energy, Real Positive, Phase X = A/B/C (X.EAPOS)

(A: 0x1E8, B: 0x2D4, C: 0x3C0)
Bit: 31 30 29 28 27 26 25 24
Name: Real Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Real Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Real Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Real Energy Byte 0

On every DSP cycle, the contents of the X.ACT register are tested, and, if positive, are added to this register. When
this register overflows, the APOV bit in the X.EOVER register is set.

______________________________________________________________________________________ 45
 Low-Power, Multifunction, Polyphase AFE
Energy, Real Negative, Phase X = A/B/C (X.EANEG)
MAXQ3180

(A: 0x1EC, B: 0x2D8, C: 0x3C4)

Bit: 31 30 29 28 27 26 25 24
Name: Real Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Real Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Real Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Real Energy Byte 0

On every DSP cycle, the contents of the X.ACT register are tested, and, if negative, absolute values are added to
this register. When this register overflows, the ANOV bit in the X.EOVER register is set.

Energy, Reactive Positive, Phase X = A/B/C (X.ERPOS)

(A: 0x1F0, B: 0x2DC, C: 0x3C8)
Bit: 31 30 29 28 27 26 25 24
Name: Reactive Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Reactive Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Reactive Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Reactive Energy Byte 0

On every DSP cycle, the contents of the X.REA register are tested, and, if positive, are added to this register. When
this register overflows, the RPOV bit in the X.EOVER register is set.

46 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Energy, Reactive Negative, Phase X = A/B/C (X.ERNEG)

MAXQ3180
(A: 0x1F4, B: 0x2E0, C: 0x3CC)
Bit: 31 30 29 28 27 26 25 24
Name: Reactive Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Reactive Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Reactive Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Reactive Energy Byte 0

On every DSP cycle, the contents of the X.REA register are tested, and, if negative, absolute values are added to
this register. When this register overflows, the RNOV bit in the X.EOVER register is set.

Energy, Apparent, Phase X = A/B/C (X.ES) (A: 0x1F8, B: 0x2E4, C: 0x3D0)

Bit: 31 30 29 28 27 26 25 24
Name: Apparent Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Apparent Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Apparent Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Apparent Energy Byte 0

On every DSP cycle, the contents of the X.APP register are added to this register. When this register overflows, the
SOV bit in the X.EOVER register is set.

______________________________________________________________________________________ 47
 Low-Power, Multifunction, Polyphase AFE
Virtual Register Conversion Coefficients
MAXQ3180

Voltage Units Conversion Coefficient (VOLT_CC) (0x014)

Bit: 15 14 13 12 11 10 9 8
Name: Voltage Units Conversion Coefficient High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Voltage Units Conversion Coefficient Low Byte
Reset: 0x01

This register contains the value by which the raw voltage value in each phase (A.VRMS, B.VRMS, and C.VRMS) is
multiplied before being presented to the virtual RMS voltage registers (V.A, V.B, and V.C).
To determine the value of VOLT_CC, a voltage value for the least significant bit (VOLT_LSB) of the V.X registers must
be selected. Typical values might range from 1mV to 1nV. To avoid significant conversion loss, VOLT_LSB should be
chosen such that VOLT_CC is >1000. Once VOLT_LSB is determined, calculate VOLT_CC from the following equa-
tion:
VFS
VOLT _ CC =
24
2 × VOLT _ LSB

Current Units Conversion Coefficient (AMP_CC) (0x016)

Bit: 15 14 13 12 11 10 9 8
Name: Current Units Conversion Coefficient High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Current Units Conversion Coefficient Low Byte
Reset 0x01

This register contains the value by which the raw current value in each phase (A.IRMS, B.IRMS, C.IRMS, and
N.IRMS) is multiplied before being presented to the virtual RMS current registers (I.A, I.B, I.C, and I.N). To determine
the value of AMP_CC, a current value for the least significant bit (AMP_LSB) of the I.X registers must be selected.
Typical values might range from 1nA to 10μA. To avoid significant conversion loss, AMP_LSB should be chosen
such that AMP_CC is >1000. Once determined, calculate AMP_CC from the following equation:

IFS
AMP _ CC =
24
2 × AMP _ LSB

48 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Power Units Conversion Coefficient (PWR_CC) (0x018)

MAXQ3180
Bit: 15 14 13 12 11 10 9 8
Name: Power Units Conversion Coefficient High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Power Units Conversion Coefficient Low Byte
Reset: 0x01

This register contains the value by which the raw power value in each phase is multiplied before being presented to
the virtual power registers. The table below lists the raw power registers and the corresponding virtual registers.

DESCRIPTION RAW VIRTUAL

Real power, phase A A.ACT PWRP.A
Real power, phase B B.ACT PWRP.B
Real power, phase C C.ACT PWRP.C
Real power, total — PWRP.T
Reactive power, phase A A.REA PWRQ.A
Reactive power, phase B B.REA PWRQ.B
Reactive power, phase C C.REA PWRQ.C
Reactive power, total — PWRQ.T
Apparent power, phase A A.APP PWRS.A
Apparent power, phase B B.APP PWRS.B
Apparent power, phase C C.APP PWRS.C
Apparent power, total — PWRS.T
Real power, phase A, fundamental frequency only A.ACTF PWRPF.A
Real power, phase B, fundamental frequency only B.ACTF PWRPF.B
Real power, phase C, fundamental frequency only C.ACTF PWRPF.C
Real power, total, fundamental frequency only — PWRPF.T
Reactive power, phase A, fundamental frequency only A.REAF PWRQF.A
Reactive power, phase B, fundamental frequency only B.REAF PWRQF.B
Reactive power, phase C, fundamental frequency only C.REAF PWRQF.C
Reactive power, total, fundamental frequency only — PWRQF.T
Apparent power, phase A, fundamental frequency only A.APPF PWRSF.A
Apparent power, phase B, fundamental frequency only B.APPF PWRSF.B
Apparent power, phase C, fundamental frequency only C.APPF PWRSF.C
Apparent power, total, fundamental frequency only — PWRSF.T

PWR_CC establishes the amount of power represented by one PWR_LSB of the power registers. To avoid significant
conversion loss, PWR_LSB should be chosen such that PWR_CC is > 1000. Calculate the value of PWR_CC accord-
ing to the following formula:

IFS × VFS
PWR _ CC =
32
2 × PWR _ LSB

______________________________________________________________________________________ 49
 Low-Power, Multifunction, Polyphase AFE
Energy Units Conversion Coefficient (ENR_CC) (0x01A)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: Energy Units Conversion Coefficient High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Energy Units Conversion Coefficient Low Byte
Reset: 0x01

This register contains the value by which the raw accumulated energy value in each phase is multiplied before being
presented to the virtual energy registers. The table below lists the raw energy accumulators and the corresponding
virtual registers.

DESCRIPTION RAW VIRTUAL

Real energy, phase A, positive direction A.EAPOS
ENRP.A*
Real energy, phase A, reverse direction A.EANEG
Real energy, phase B, positive direction B.EAPOS
ENRP.B*
Real energy, phase B, reverse direction B.EANEG
Real energy, phase C, positive direction C.EAPOS
ENRP.C*
Real energy, phase C, reverse direction C.EANEG
Real energy, total — ENRP.T
Reactive energy, phase A, positive direction A.ERPOS
ENRQ.A*
Reactive energy, phase A, reverse direction A.ERNEG
Reactive energy, phase B, positive direction B.ERPOS
ENRQ.B*
Reactive energy, phase B, reverse direction B.ERNEG
Reactive energy, phase C, positive direction C.ERPOS
ENRQ.C*
Reactive energy, phase C, reverse direction C.ERNEG
Reactive energy, total — ENRQ.T
Apparent energy, phase A A.ES ENRS.A
Apparent energy, phase B B.ES ENRS.B
Apparent energy, phase C C.ES ENRS.C
Apparent energy, total — ENRS.T
Real energy, phase A, positive direction, fundamental only A.EAFPOS
ENRPF.A*
Real energy, phase A, reverse direction, fundamental only A.EAFNEG
Real energy, phase B, positive direction, fundamental only B.EAFPOS
ENRPF.B*
Real energy, phase B, reverse direction, fundamental only B.EAFNEG
Real energy, phase C, positive direction, fundamental only C.EAFPOS
ENRPF.C*
Real energy, phase C, reverse direction, fundamental only C.EAFNEG
Real energy, total, fundamental only — ENRPF.T
Reactive energy, phase A, positive direction, fundamental only A.ERFPOS
ENRQF.A*
Reactive energy, phase A, reverse direction, fundamental only A.ERFNEG
Reactive energy, phase B, positive direction, fundamental only B.ERFPOS
ENRQF.B*
Reactive energy, phase B, reverse direction, fundamental only B.ERFNEG
*These registers represent the algebraic sum of the positive and reverse energy in the two “raw” registers noted. Thus, the energy
returned in these virtual registers represents the net energy.
50 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Energy Units Conversion Coefficient (ENR_CC) (0x01A) (continued)

MAXQ3180
DESCRIPTION RAW VIRTUAL
Reactive energy, phase C, positive direction, fundamental only C.ERFPOS
ENRQF.C*
Reactive energy, phase C, reverse direction, fundamental only C.ERFNEG
Reactive energy, total, fundamental only — ENRQF.T
Apparent energy, phase A, fundamental only A.ESF ENRSF.A
Apparent energy, phase B, fundamental only B.ESF ENRSF.B
Apparent energy, phase C, fundamental only C.ESF ENRSF.C
Apparent energy, total, fundamental only — ENRSF.T
*These registers represent the algebraic sum of the positive and reverse energy in the two “raw” registers noted. Thus, the energy
accumulated in these virtual registers represents the net energy.

To avoid significant conversion loss, ENR_LSB should be chosen such that ENR_CC is > 1000. Calculate the value
of ENR_CC according to the following formula:

I × VFS × t FR
ENR _ CC = FS
2 16 × ENR _ LSB

Virtual Registers
The virtual registers are calculated values derived from one or more real registers. They are calculated at the time
they are requested, and thus could involve additional time to return a value. Most virtual registers are 8 bytes in
length and are delivered least significant byte first.
Power
Real Power, Phase X = A/B/C/T (PWRP.X) (A: 0x801, B: 0x802, C: 0x804, T: 0x807)
This signed register contains the real instantaneous power delivered into phase A/B/C or total. Power is calculated
from the instantaneous energy measurement according to the following equation:

X.ACT × PWR _ CC × 2 16
PWRP.X =
NS
The register is 8 bytes long, but the most significant 2 bytes are not used. See the PWR_CC register description for
more details.

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Note that the sign bit is bit 47 for all 8-byte signed virtual registers.

______________________________________________________________________________________ 51
 Low-Power, Multifunction, Polyphase AFE
Reactive Power, Phase X = A/B/C/T (PWRQ.X) (A: 0x811, B: 0x812, C: 0x814, T: 0x817)
MAXQ3180

This signed register contains the reactive instantaneous power delivered into phase A/B/C or total. Power is calculat-
ed from the instantaneous energy measurement according to the following equation:

X.REA × PWR _ CC × 2 16
PWRQ.X =
NS
The register is 8 bytes long, but the most signficant 2 bytes are not used. See the PWR_CC register description for
more details.

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Apparent Power, Phase X = A/B/C/T (PWRS.X) (A: 0x821, B: 0x822, C: 0x824, T: 0x827)
This register contains the apparent instantaneous power delivered into phase A/B/C or total. Power is calculated
from the instantaneous energy measurement according to the following equation:

X.APP × PWR _ CC × 2 16
PWRS.X =
NS
The register is 8 bytes long, but the most significant 2 bytes are not used. See the PWR_CC register description for
more details.

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

52 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Voltage and Current

MAXQ3180
RMS Volts, Phase X = A/B/C (V.X) (A: 0x831, B: 0x832, C: 0x834)
This register contains the RMS voltage on phase A/B/C. The units are defined by the VOLT_CC setting such that V.X
= X.VRMS x VOLT_CC. In this equation, VOLT_CC is the conversion coefficient. See the VOLT_CC register for more
information.
Byte 7 (MSByte unused) Byte 6 (unused)
Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

RMS Amps, Phase X = A/B/C/N (I.X) (A: 0x841, B: 0x842, C: 0x844, N: 0x840)
This register contains the RMS current on phase A/B/C or the neutral channel. The units are defined by the AMP_CC
setting such that I.X = X.IRMS x AMP_CC. In this equation, AMP_CC is the conversion coefficient. See the AMP_CC
register for more information.
Byte 7 (MSByte unused) Byte 6 (unused)
Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Power Factor
Power Factor (PF.T) (0x867)
This signed register contains the power factor of the total power. The power factor is calculated as:
A.ACT + B.ACT + C.ACT
PF.T =
A.APP + B.APP + C.APP
It is expressed in units of 0.00001; thus, unity power factor is expressed as decimal 100,000
(0x00000000000186A0). This register is presented as a two’s complement value, so that a load delivering real power
to the line (that is, reverse power) is seen as having a power factor of -1 (0x0000FFFFFFFE7960).
Byte 7 (MSByte unused) Byte 6 (unused)
Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

______________________________________________________________________________________ 53
 Low-Power, Multifunction, Polyphase AFE
Energy
MAXQ3180

Real Energy, Phase A/B/C/T (ENRP.X) (A: 0x8C1, B: 0x8C2, C: 0x8C4, T: 0x8C7)
This signed register contains the real accumulated energy delivered into phase A/B/C or total. The register is calcu-
lated according to the following formula:
ENRP.X = ENR_CC x (X.EAPOS - X.EANEG)

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Reactive Energy, Phase A/B/C/T (ENRQ.X) (A: 0x8D1, B: 0x8D2, C: 0x8D4, T: 0x8D7)
This signed register contains the reactive accumulated energy delivered into phase A/B/C or total. The register is
calculated according to the following formula:
ENRQ.X = ENR_CC x (X.ERPOS - X.ERNEG)

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Apparent Energy, Phase A/B/C/T (ENRS.X) (A: 0x871, B: 0x872, C: 0x874, T: 0x877)
This register contains the apparent accumulated energy delivered into phase A/B/C or total. The register is the prod-
uct of the ENR_CC and X.ES registers.

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

54 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Theory of Operation Digital Signal Processing (DSP)

MAXQ3180
Terminology
Analog Front-End Operation Establishing the precise definitions of some of the terms
Whenever the MAXQ3180 is in one of the active operat- used in this document will assist in understanding how
ing modes (Run Mode or LOWPM Mode), the analog the DSP functions.
front-end operates continuously, scanning up to eight
Sample Period: The amount of time required to mea-
scan slots depending on the selected front-end config-
sure a single data element; 40μs, by default.
uration. For each analog scan slot that is enabled, one
of the eight differential input pairs is measured. ADC Frame Period: The amount of time required for
the ADC to sample all analog inputs; always equal to 8
The SCAN_IX and SCAN_VX (X = A/B/C), SCAN_IN,
sample periods. The inverse of this value is the frame
and SCAN_TE registers contain the settings for each
rate; by default 3125 samples per second. This is the
slot, which include whether the slot is enabled and the
rate at which any particular signal is sampled by the
differential input pair to measure during that scan slot.
MAXQ3180.
The logical mapping of the slots is fixed in following
order: Line Cycle: The period of time from one positive-going
zero crossing on a voltage channel to the next positive-
• Slot 0—Phase A Current (IA)
going zero crossing. At 50Hz, this is nominally 20ms; at
• Slot 1—Phase A Voltage (VA) 60Hz, this is nominally 16.67ms.
• Slot 2—Phase C Current (IC) Cycle Count: The number of line cycles contained in a
• Slot 3—Phase C Voltage (VC) single DSP cycle. An integer, this is typically set to
some value greater than one to minimize the effect of
• Slot 4—Phase B Current (IB)
load variations that may not occur in every line cycle.
• Slot 5—Phase B Voltage (VB) By default, this value is 16.
• Slot 6—Neutral Current (IN)—disabled by default DSP Cycle: The period of time over which line parame-
• Slot 7—Temperature Measurement—disabled by ters are calculated. Energy and other parameters are
default accumulated once per DSP cycle. One DSP cycle is
the time of a line cycle multiplied by the cycle count.
The required time for each analog scan slot measure-
ment (t C ) is determined by the MAXQ3180 system NS: This value represents the number of ADC frame
clock frequency and the setting of the R_ADCRATE periods in a DSP cycle. This is a noninteger calculated
hardware register, as shown below: value. For example, if the cycle count is set to unity,
and the line frequency is exactly 50Hz, the NS value
tC = 1/fCLK x (R_ADCRATE[8:0] + 1)
would be 20ms/320μs = 62.5.
Using the default register settings (R_ADCRATE = 13Fh
= 319d), the time for each analog slot measurement Digital Processing
(tC) is 40μs when the MAXQ3180 is running at 8MHz. As voltage and current samples are collected, the
Since there are eight analog scan slots in the measure- MAXQ3180 performs a variety of digital filtering,
ment frame, the total time for all measurements (tFR) is accumulation, and processing calculations to arrive at
tC x 8. Using the default settings with the MAXQ3180 meter-reading values (such as line frequency, RMS
running at 8MHz, the entire sequence of measurements voltage and current, and active and reactive power)
takes 320μs to complete, which, in turn, means that that can then be read by the master. The MAXQ3180
320μs will elapse, for example, between one phase A calculates and detects values and conditions including
current measurement and the next. the following:
Even if some of the analog measurement slots (such as • Zero-crossing detection
neutral current or temperature measurement) are • Line frequency and line period calculation
skipped by setting the DADCNV bit in that slot’s regis-
ter to 1, the time period for that slot will remain in the • RMS voltage (phase A, phase B, phase C)
frame, ensuring that the total frame time is always tC x • RMS current (phase A, phase B, phase C, neutral
8, regardless of which individual slots are enabled or current)
disabled.

______________________________________________________________________________________ 55
 Low-Power, Multifunction, Polyphase AFE
• Power (active, reactive, and apparent) for each imaginary components of energy at this point do not yet
MAXQ3180

phase represent real and reactive power; to obtain usable

• Energy accumulation (including energy pulse output power values further processing is required. Each of
function) these values is further processed at the end of each
DSP cycle.
• Overvoltage detection
• Overcurrent detection Per DSP Cycle Operations
At the end of each DSP cycle, accumulated information
• Undervoltage detection is available that is used to calculate all other opera-
Per Sample Operations tional results in the meter. DSP cycles track the line fre-
On every ADC frame, the input samples are processed quency and have a duration of the number of cycles
as follows: specified in the CYCNT register. On each phase, the
time required for CYCNT cycles to complete is calculat-
• The voltage and current samples are read. The cur- ed and this value is used to update the duration of one
rent sample is shifted to account for the gain applied DSP cycle, specified in the NS register.
in the PGA. The phase- and gain-corrected samples
are passed to the next stage. NS contains the number of ADC frame periods in a sin-
gle DSP cycle. Because line frequency varies slightly
• Both the current and voltage signals are passed from cycle to cycle, and because the ADC frame clock
through highpass filters (HPF) specified by the is not synchronized to the line, the value of NS is not an
HPF_C variable. integer, and varies slightly from DSP cycle to DSP cycle.
• The current and voltage signals are now split into Because the value of NS is so critical to accurate calcu-
several components. The first of these components is lation of energy, ensuring that it is correct on every
squared and accumulated to begin the RMS current cycle is essential. There are two ways to manage the
and voltage process. The second is processed and slight variation of NS from cycle to cycle: first, one
accumulated to begin the real/reactive power calcu- could simply replace the old value of NS with the newly
lation. And a third is processed through a peak filter calculated value on each DSP cycle. This means that
(specified by B0FUND and A1FUND registers) and NS (and every other value in the meter, since they
then accumulated to provide information for the fun- depend on NS) would have a significant amount of
damental frequency power calculations. uncertainty. A better method is to use each newly cal-
The result is a set of accumulated values that represent culated value of NS as an input to a filter. The output of
squared voltage, squared current, and real (active) and the filter is then the value of NS that is actually used in
reactive (P and Q) energies for both the entire usable calculations. In the MAXQ3180, this filter is controlled
spectrum and as filtered by the peak filter. The real and by the AVG_NS register.

X2 I2

GAIN SEL I_GAIN HPF

CURRENT INPUT ADC BPF

ENERGY PROCESSING

ENERGY PROCESSING

EP EPF
EQ EQF
V_GAIN

VOLTAGE INPUT ADC BPF

HPF

X2 V2

Figure 9. Per Sample Operations

56 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
A second problem with updating NS on every line added to the raw RMS current signal when the current

MAXQ3180
cycles is the fact that noise impulses that occur at near- signal is below a low current threshold (1/32 of the full
ly the same time as the zero crossing can shift the zero scale) value; and the X.GAIN_LO register contains a
crossing, affecting the accuracy of the energy mea- gain adjustment that is applied to the current signal
sured during the preceding period. For this reason, a when the current signal is below the threshold value.
second register, REJ_NS contains a value that specifies The practical effect of this is to turn what may be a
how far a particular sample can deviate from the aver- somewhat nonlinear response curve for the current sen-
age and still be considered valid. If the period of the sor to a much more linear response by two-piece
newly acquired DSP cycle differs from the previously approximation.
accumulated average value by more than REJ_NS ADC The “high current” calibration term X.OFFS_HI is used
frames, NS is not updated with the new period (but the so long as the instantaneous current exceeds the low-
energy is still accumulated). current threshold at some instant during a DSP cycle. As
With this discussion in mind, the signal path for the vari- long as this threshold is crossed during a DSP cycle, the
ous reported parameters can be reviewed. value in X.OFFS_HI controls the offset current.
RMS Volts and RMS Amps: First, the squared voltage When the input stays below the low-current threshold
accumulation is divided by NS. This accomplishes the for one DSP cycle, the X.OFFS_LO and X.GAIN_LO are
“mean” part of the “root-mean-square” calculation. applied. The low-current calibration terms (X.GAIN_LO
Then, the square root of the result is taken, producing and X.OFFS_LO) remain in effect until the peak of input
the raw RMS calculation value. current waveform exceeds 1/32 of full-scale current at
On the voltage channel, the signal is ready for gain any time during a DSP cycle.
compensation to be applied. But on the current channel, As a final step, both voltage and current are passed
there is an additional twist: depending on the amplitude through an averaging filter that provides smoothing for
of the current, there may be a gain factor pre-applied the signals. The amount of filtering is given in AVG_C.
before the raw sample is available. To compensate for Energy: The per-sample processing produces a pair of
inaccuracy in the gain factor for the amplifier and for digital signals that represent the complex energy sig-
noise seen in the channel at high gain settings, it may nal. From this complex signal, it is desired to extract the
be necessary to provide linearity compensation. real portion and the reactive portion. At first glance, this
There are three registers that manage the linearization seems trivial: the real portion is the real part of the com-
of the current signal: the X.OFFS_HI (X = A/B/C) regis- plex signal, and the reactive portion is the imaginary
ter contains a signed value that is added to the raw part of the complex signal. Apparent power (in volt-
RMS current signal before further processing; the amperes) is the magnitude of the complex signal, and
X.OFFS_LO register contains a signed value that is power angle is the argument of the complex signal.

OFFS_HI
GAIN_LO AVG_C
OFFS_LO
I2
LINEARIZATION AVERAGE IRMS
NS

RAW_I

RAW_V

V2
AVERAGE VRMS
NS

AVG_C

Figure 10. Computation of RMS Values

______________________________________________________________________________________ 57
 Low-Power, Multifunction, Polyphase AFE
But current sensors and other external circuitry compo- square this value, then subtract the squared real
MAXQ3180

nents introduce a phase distortion to the current signal, power. The square root of this value is the reactive
and this phase distortion may not be constant at all cur- energy.
rent values. Consequently, for the most precise mea- Similarly, apparent energy can be calculated in either
surements, the phase between the voltage and current of two ways: either as the product of the raw RMS volts
signals must be compensated. In the MAXQ3180, the and amps, or as the square root of the sum of the
energy signals are compensated for phase offset by squares of the real and reactive energy. Which of these
performing a complex multiplication of the signal with is selected depends on the value of the APPSEL bit in
the contents of the appropriate phase offset register. the OPMODE2 register: if 0, then apparent energy is
Determining which phase offset register is appropriate is the product of the raw RMS volts and amps and reac-
a matter of comparing the incoming RMS current for the tive energy is calculated using the difference of
phase with the contents of the I1THR and I2THR regis- squares method; if 1, apparent energy is calculated
ters. It is the responsibility of the administrative software using the sum of squares method and reactive energy
to ensure that I1THR is greater than or equal to I2THR. If is calculated directly from the complex energy.
the raw RMS current is greater than or equal to the con- Line Frequency and Phasor Angles: Line frequency
tents of I1THR, then the angle expressed in PA0 is used can be taken directly from the NS value. Recall that NS
to compensate the phase angle. If the raw RMS current is the number of frames in a DSP cycle. Since each
is less than I2THR, then the angle expressed in PA2 is frame is 320μs, simply multiply NS by 320μs and divide
used to compensate the phase angle. And if the raw by CYCNT to obtain the line period. The reciprocal of
RMS current falls between I1THR and I2THR then PA1 is this is the line frequency.
used to compensate the phase angle. In this way, a
three-piece stepwise approximation of the phase To calculate phasor angles, the numbers of samples
response of the current sensor is available. between zero crossings on phase A and B and on phase
A and C are taken. Since NS is the number of samples
⎧PA0, IRMS ≥ I1THR ⎫ during a complete DSP cycle, it is easy to calculate the
⎪ ⎪ fraction of a complete cycle. The software then converts
PA = ⎨PA1, I1THR > IRMS ≥ I2THR) ⎬ this value to degrees and adjusts it such that no negative
⎪PA2, I ⎪
⎩ RMS < I2THR ⎭ angles are reported. No calibration is required for line
frequency and phasor angle calculation.
To use a constant phase compensation, set I1THR and
I2THR to zero and insert the phase compensation value Energy Accumulation
into PA0. Once real and reactive energy over the most recent
DSP cycle has been calculated, it is necessary to accu-
The same processing can be performed to calculate mulate the result.
the reactive energy value. But reactive energy can be
calculated in another way: calculate apparent energy For reactive energy, the result accumulated during any
by multiplying the raw RMS volts and raw RMS current, DSP cycle may be positive (for an inductive load) or

OFFS_HI
GAIN_LO E_GAIN AVG_C
OFFS_LO
PA0 LINEARIZATION AVERAGE EREAL
PA1
REAL/REACTIVE

EP PA2
PROCESSING

PHASE E_RAWREAL
COMPENSATION OFFS_HI
GAIN_LO
EQ OFFS_LO

LINEARIZATION E_RAWREACTIVE

Figure 11. Phase Compensation for Energy Calculations

58 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
E_RAWREAL E_GAIN AVG_C
X2 + Y2
E_RAWREACTIVE
AVERAGE EAPPARENT
RAW_I
X×Y
RAW_V
APPSEL

E_GAIN

AVERAGE EREACTIVE

X2 - Y2
AVG_C
APPSEL

Figure 12. Apparent and Reactive Energy Calculations

negative (for a capacitive load). These values are sepa- 1. The master can clear NOZXF and NOZX back to 0 to
rately accumulated. This means that during any one remove the interrupt condition.
DSP cycle, only positive or negative reactive energy will
be accumulated. Phase Sequence Status
A phase sequence status bit PHSEQ indicates the
Similarly, for real energy, the result accumulated during order in which zero crossings are detected. When a
any DSP cycle can be positive (that is, energy is deliv- zero-crossing event occurs on the phase A voltage sig-
ered to the load) or negative (that is, energy is driven nal, followed by phase B, phase C, and then phase A
back into the line). As is performed for reactive energy, again, this bit cleared. If a zero crossing on phase A is
these values are separately accumulated. then followed by a zero crossing on phase C, then
Apparent energy is also accumulated, but since this phase B, this bit set to 1.
value is always positive or zero, there is only one
apparent energy accumulator. RMS Voltage, RMS Current, and Energy
Calculation
From time to time, the accumulators generate an over-
For each of the three phases, the MAXQ3180 calcu-
flow. When this occurs, the appropriate bit is set in the
lates RMS voltage and RMS current values, as well as
overflow status register X.EOVER.
determines active and reactive energy, using a line-
When an overflow occurs, supervisory code running on cycle-based integration process.
the host processor must make the appropriate adjust-
ments in the reported energy. In many cases, this could Power Calculation (Active, Reactive,
simply involve incrementing an overflow counter. The Apparent)
host processor must then clear the overflow indication. The power, energy, and RMS calculation process con-
sists of two tasks: continuous accumulation and post-
No-Zero-Crossing Detection processing triggered every CYCNT line cycles. The
The MAXQ3180 monitors the voltage signal on each accumulation task accumulates raw data obtained from
phase for zero-crossing events. If no ascending zero the AFE during CYCNT line cycles. This task is per-
crossings are detected within a specified number formed continuously in the background by the
(NZX_TIMO) of analog scan sample periods, the MAXQ3180. When a CYCNT line cycles accumulation
NOZXF (X.FLAGS) flag is set by the MAXQ3180 to noti- stage has completed, which is determined by a dedi-
fy the master of this condition. If the NOZXM bit is set, cated frame counter exceeding the NS level, the raw
this flag sets the NOZX bit in the IRQ_FLAG. If the inter- integral accumulator values are saved for postprocess-
rupt enable bit ENOZX is set to 1, the interrupt signal ing and cleared, beginning the next cycle of accumula-
IRQ is driven low by the MAXQ3180 whenever NOZX = tion task. Then, the DSP postprocessing is triggered to

______________________________________________________________________________________ 59
 Low-Power, Multifunction, Polyphase AFE
process saved integrals and calculate energy, power, On Demand Calculations
MAXQ3180

etc., values. Note that the background accumulation So far in this discussion, the values being calculated
task continues while foreground postprocessing is tak- and managed in the MAXQ3180 have been based on
ing place, i.e., both tasks are executed simultaneously fundamental units meaningful to the device itself: volt-
sharing CPU time. It is essential that the DSP postpro- age as a binary fraction of full-scale voltage; current as
cessing calculations be completed before the next DSP a binary fraction of full-scale current, and time as a non-
trigger to avoid losing accumulated data. The master integer multiple of the ADC frame time.
should allow enough processing time by adjusting the But a practical electricity meter must report its results in
R_ADCRATE register. Default settings provide plenty of standard units, such as volts, amperes, and watts. The
CPU time for both tasks. MAXQ3180 contains a mechanism to convert the inter-
The MAXQ3180 accumulates raw sums and calculates nal units (“meter units”) to real world units (“display
line-cycle integrals for each voltage-current pair sepa- units”). This conversion is performed in the conversion
rately. The individual power accumulators are: constant (CC) registers.
• PA = VA x IA For some of these values (voltage, current) the calcula-
• PB = IB x VB or -IB x VC or -IB x (VA + VC) or -IB x tion is simple: multiply by the conversion constant. For
(VA - VC) other values (power, energy) the calculation is more
complex. In any case, the value in the CC register
• PC = VC x IC affects only the conversion from a meter unit to a dis-
The PA and PC accumulators always operate in a sin- play unit; calibration is handled separately in the gain
gle mode: (VA x IA) for the PA accumulator, (VC x IC) for adjustment registers for each recorded value.
the PC accumulator. Alternately, the operating mode of The results of all on-demand calculations are reported
the PB accumulator is defined by setting the as 8-byte (64-bit) values of which no more than 6 bytes
CONCFG[1:0] bits in the OPMODE1 register. (48 bits) are significant. Eight bytes are used as a com-
Energy Accumulation Start Delay mon length; however, fewer bytes can be requested for
All filters have a certain settling time before accurate those registers known to have smaller maximum values.
energy readings can be accumulated. To avoid accu- For example, the power factor virtual register has a
mulation of invalid data from filters that are still settling, maximum value that is expressed in only 3 bytes; con-
an energy accumulation timeout period can be set in sequently, the register can be requested with a length
the ACC_TIMO register. When ACC_TIMO > 0, comput- of 4 bytes without loss of data.
ed energy is not accumulated for ACC_TIMO of DSP RMS Volts, RMS Amps
cycles. The MAXQ3180 will decrement the ACC_TIMO These registers (V.A, V.B, V.C, I.A, I.B, I.C) are calculat-
register every DSP cycle until it becomes 0. When ed by simply multiplying the calculated RMS value
ACC_TIMO reaches 0 value, energy accumulation (A.VRMS, B.VRMS, C.VRMS, A.IRMS, B.IRMS, C.IRMS)
begins (or resumes, if ACC_TIMO was set to nonzero by the contents of the VOLT_CC or AMP_CC register.
value by the master). Pulse outputs are also disabled Since the RMS voltage and RMS current are given in
when ACC_TIMO > 0. The default value of ACC_TIMO 32-bit registers and the conversion coefficients are
is 0x05. given in 16-bit registers, the result of the product is 48
No-Load Feature bits.
To avoid “meter creep,” no energy accumulation should Regardless of the internal units used, VOLT_CC and
take place when measured current is less than a cer- AMP_CC can be tailored so that the LSB of the virtual
tain threshold. The NOLOAD register can be pro- register can be any value. For example, if one wished
grammed to enable and configure this feature. If the to have a 32-bit value representing milliamps, one
measured X.IRMS value for a phase (A, B, or C) falls could multiply by a value that scaled the register such
below the NOLOAD threshold, the energy accumulators that the LSB was 2-16mA. Then, discard the low-order
for this phase are not incremented. Setting NOLOAD = 16 bits. The result is milliamps with 32 bits of precision;
0 disables this feature. Full scale is represented by thus, the maximum current that could be represented
0x10000. would be 4,294,967,296mA, or just over 4MA.

60 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
The VOLT_CC and AMP_CC values can be calculated voltage and current measurement. The power factor as

MAXQ3180
from the full-scale voltage or full-scale current and the reported could change when one or the other of these
desired value of one LSB in the display register: methods is used.
IFS The power factor is multiplied by 214 before it is report-
AMP _ CC = ed; thus, unity power factor is given by 16,384 decimal
2 24 × AMP _ LSB (0x4000).
VFS Line Frequency
VOLT _ CC =
24
2 × VOLT _ LSB The line frequency is derived directly from the mean NS
values over the three phases. It is reported as millihertz;
Example: Assume the full-scale current is 102.4A, and thus, a 50Hz line frequency is reported as decimal
that we desire a 1nA LSB. The calculation would pro- 50,000 (0xC350).
vide an AMP_CC value of:
Phasor Angles
102.4/(224 x 10-9) = 6104 = 0x17D8 The phasor angles are taken directly from the angular
Power measurement values determined at each DSP cycle.
The MAXQ3180 measures energy. But power is just The angle is reported in units of 0.01 degree; thus, a
energy per unit time, and the MAXQ3180 keeps track of 120° phasor is reported as decimal 12,000 (0x2EE0).
the time unit over which energy is accumulated. This is Energy
simply the NS value, the fractional number of samples Energy is read as the net energy directly scaled from
that comprises one DSP cycle. So converting energy to the appropriate registers. For example, the energy read
power is as simple as dividing the accumulated energy from the ENRP.A register (real energy, phase A) is
over one DSP cycle by NS. Multiplying by a conversion composed of the difference between the A.EAPOS (real
constant (PWR_CC) gives power in user-established energy, positive direction, phase A) and A.EANEG (real
units. energy, negative direction, phase A) registers scaled
The power registers (PWRP.A, PWRP.B, PWRP.C, by the ENR_CC register.
PWRQ.A, PWRQ.B, PWRQ.C, PWRS.A, PWRS.B, Note that the energy registers (ENRP.A, ENRP.B,
PWRS.C) are calculated by multiplying the accumulat- ENRP.C, ENRP.T, ENRQ.A, ENRQ.B, ENRQ.C, ENRQ.T,
ed energy (A.ACT, A.REA, A.APP, B.ACT, B.REA, ENRS.A, ENRS.B, ENRS.C, ENRS.T) represent the ener-
B.APP, C.ACT, C.REA, C.APP) by the conversion coeffi- gy, in every case, since the last overflow event. For this
cient (PWR_CC) and then dividing by NS. The result is reason, software must keep track of overflow and make
the 48-bit average power over the most recent DSP adjustments accordingly when using this register set.
cycle, in units established by the conversion coefficient.
To calculate the ENR_CC register value, begin with the
The PWR_CC value can be calculated from the full- full-scale voltage and full-scale current, the frame time,
scale voltage, the full-scale current, and the desired and the desired LSB value for energy. Then perform the
value of one LSB in the display register: following calculation:
IFS × VFS I × VFS × t FR
PWR _ CC = ENR _ CC = FS
2 32 × PWR _ LSB 2 16 × ENR _ LSB
Example: For this example, assume the full-scale cur- Example: It is essential to ensure that the correct units
rent is 102.4A, the full-scale voltage is 558.1V, and that are maintained throughout the calculation. In this exam-
the desired LSB is milliwatts after discarding the 16 ple, assume that the full-scale voltage is 558.1V, the
LSB; that is, the desired LSB is 2-16 milliwatts. Perform full-scale current is 102.4A, the frame time is the default
the following calculation: of 320μs, and the desired LSB is 100 milliwatt-hours
102.4 x 558.1/(232 x 2-16 x 10-3) = 872 = 0x0368 after the 32 bits are discarded; that is, the LSB is 0.1 x
2-32 watt-hours. Notice, however, that the frame time is
Power Factor given in microseconds and must be converted to hours
Power factor is calculated as real power divided by before the calculation can be performed: 320μs is 88.9
apparent power. But note that apparent power can be x 10-9 hours. So the calculation proceeds as follows:
calculated in either of two ways: either as a square root
of the sum of the squares of the real and reactive 102.4 x 558.1 x 88.9 x 10-9/(216 x 0.1 x 2-32) = 3329 =
power, or more commonly as the product of the RMS 0x0D01

______________________________________________________________________________________ 61
 Low-Power, Multifunction, Polyphase AFE
Meter Pulse Meter Constant
MAXQ3180

The purpose of a meter pulse is generally to advance a A meter constant is the number of pulses that are gen-
mechanical counter when such a device is used as a erated during a standard measurement interval; for
display. Meter pulses are also used during calibration example, a meter might specify a meter constant of
since time intervals can be measured with great preci- 1600 pulses per kilowatt-hour. The THR1 and THR2
sion. registers are used to specify the meter constant
The MAXQ3180 supports two meter pulse outputs. according to the following formula:
These outputs can be configured for either active posi- 2 16
tive or active negative pulses by means of the POPOL THR =
bit in the OPMODE1 register. When triggered, the pulse K M × IFS × VFS × t FR
goes to its active state and remains there for a period of In this formula, THR is the value to be written to the
time defined by the PLS1_WD or PLS2_WD register, threshold register, KM is the desired meter constant (in
and then returns to the inactive state (unless triggered pulses per kilowatt hour), IFS and VFS are the full-scale
again). voltage and current, respectively, and tFR is the frame
The PLS1_WD and PLS2_WD registers contain the time period in units of hours, as in the previous calculation.
in ADC frame periods that the pulses remain in the As an example, assume once again a full-scale voltage
active state when triggered. By default, these registers value of 558.1V = 0.5581kV, a full-scale current value of
contain decimal 156 (0x9C) giving, at the default frame 102.4A, a desired meter constant of 1600 pulses per
rate, a pulse width of 50ms. kilowatt hour, and a default frame time of 320μs (88.9 x
Each pulse generator can select one parameter to be 10-9 hours). The threshold register value can be calcu-
accumulated over any combination of the three phases. lated as:
For example, one could select real energy accumulated 65,536/(1600 x 102.4 x 0.5581 x 88.9 x 10-9) =
over all three phases for pulse output 1, and reactive 8,063,071 = 0x7B085F
energy accumulated over all three phases for pulse
output 2. The particular parameters that can be accu- Increasing the value of the threshold register reduces
mulated are given in the register table. the meter constant (that is, there are fewer pulses per
kilowatt-hour); reducing the threshold register increases
Among the quantities that can be accumulated by the the meter constant (that is, there are more pulses per
pulse subsystem are the arithmetic active energy (that kilowatt-hour.)
is, the accumulated positive real energy minus the
accumulated negative real energy) and the absolute Interrupts
active energy (that is, accumulated positive real ener- The MAXQ3180 contains an interrupt subsystem to
gy plus accumulated negative real energy). Other relieve the host processor of the burden of constantly
quantities include RMS voltage and current, positive polling the device for status. Instead, under certain cir-
and negative real energy and reactive energy in each cumstances, the MAXQ3180 can activate an external
of the four quadrants. Select the desired accumulation pin to alert the host processor that some condition
value in the QNSEL field of the PLSCFG1 and requiring host attention has occurred.
PLSCFG2 register. Interrupts are managed globally by the IRQ_MASK and
Also in the pulse configuration registers you can select IRQ_FLAG registers. In general, when a bit becomes
which phases to include in the accumulation. Set any or set in the IRQ_FLAG register, an interrupt is generated
all the PHASEA, PHASEB, and PHASEC bits in the if the corresponding bit is set in the IRQ_MASK register.
PLSCFG1 or PLSCFG2 registers to include them in the Interrupts can be configured for the following conditions:
accumulation.
PWRF: This flag indicates the V DVDD to the
Generating Pulses MAXQ3180 has fallen below its nominal operating
On every DSP cycle, the MAXQ3180 adds the value in threshold (about 2.85V). This can be taken as an
the selected register (or set of registers) to the pulse indication that power failure is imminent and that the
accumulator. If the value in the pulse accumulator host processor should begin taking steps to ensure
exceeds the value in the associated threshold register an orderly shutdown.
(THR1 or THR2), then a pulse is started and the value in CHSCH: This flag indicates that the CHKSUM regis-
the threshold register is subtracted from the value in the ter changed its value.
pulse accumulator.

62 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
EOVF: Energy overflow. This flag indicates that one or Each phase has a local register that contains copies of

MAXQ3180
more energy accumulators (X.EAPOS, X.EANEG, etc.) the OC, OV, UV, NOZX, DCHA, and DCHR bits. Thus,
have overflowed. In a traditional meter, the host to determine which phase(s) have exception conditions
processor would poll the MAXQ3180 to determine requires four reads: the IRQ_FLAG register to deter-
which of the energy accumulators have overflowed and mine which conditions are active that are causing the
adjust its internal accounting registers accordingly. interrupt to occur, and then a read to A.FLAGS,
OC: The RMS current value on one or more of the B.FLAGS, and C.FLAGS to determine which of the
phases over the most recent DSP cycle has exceed- phases have the indicated condition.
ed the value set in the OCLVL register. Finally, each phase has a pair of local registers that
OV: The RMS voltage on one or more of the phases contain overflow flags for each energy accumulator. If
over the most recent DSP cycle has exceeded the the EOVF bit is set in the IRQ_FLAG register, the host
value set in the OVLVL register. should then read the A.EOVER, B.EOVER, and
C.EOVER registers to determine which of the phases
UV: The RMS voltage on one or more of the phases have overflow conditions. If fundamental mode opera-
over the most recent DSP cycle has failed to exceed tion is enabled, the host should read A.EFOVER,
the value set in the UVLVL register. B.EFOVER, and C.EFOVER as well. Each of these reg-
NOZX: Zero crossings were not detected on one or isters contains a bit for each of real and reactive energy
more of the phases. The detection time is defined in in both positive and negative direction as well as
the NZX_TIMO register. The resolution for the apparent energy.
NZX_TIMO register is the duration of one ADC sam-
ple time (nominally 40μs). Overvoltage and Overcurrent Detection
The MAXQ3180 detects overvoltage and overcurrent
DCHA: Tells the host processor that the direction of events and can issue interrupt request signals to the
net real energy flow on one of the three phases has master when these events occur. The overvoltage level
changed during the current DSP cycle as compared can be programmed into the OVLVL register, while the
to the previous DSP cycle. overcurrent level is determined by the OCLVL register.
DCHR: Tells the host processor that the direction of Both OVLVL and OCLVL registers represent the bits
net reactive energy flow on one of the three phases 23:8 of the VRMS or IRMS registers. Any time the
has changed during the current DSP cycle as com- MAXQ3180 detects the RMS-value exceeding a thresh-
pared to the previous DSP cycle. old level, the OV or OC interrupt flag is set. If enabled,
DSPRDY: Indicates the latest DSP cycle has just any of these flags issues an interrupt request. All inter-
completed. rupt flags are “sticky” bits—the MAXQ3180 never
clears them on its own unless a reset occurs. The inter-
DSPOR: Indicates that the processing for the previ- rupt flags should be cleared by the master by writing
ous DSP cycle had not been completed before the the appropriate register.
current DSP cycle became available for processing.
This overflow indication should never be seen in the Meter Units to Real Units Conversion
default configuration; however, under some condi- All energy calculations, including various threshold
tions (faster ADC rate, slower CPU clock) the pro- checks, are performed internally in fixed format in meter
cessing requirements may exceed the number of units. Therefore, the threshold values must be supplied
CPU cycles available for DSP processing. Under by the user in meter units as well. This section summa-
these circumstances, the clock rate may be rizes how to convert real units (V, A, kWh, W, and kAh)
increased, the ADC rate may be reduced (that is, into meter units and vice versa.
the R_ADCRATE register may be increased), or the The conversion factors are based on the settings of tFR,
functional load (such as fundamental mode calcula- VFS, and IFS, defined by the user’s design.
tions) may be cut.
t FR is analog scan frame timing. This parameter is
Note that when DSPOR becomes set, all DSP calcu- defined by the R_ADCRATE setting and system clock
lations as well as all pulse outputs are invalidated. frequency fSYS:
The appropriate host response is to take the remedi-
al action described above and discard the current tFR = (R_ADCRATE + 1) x 8/fSYS
set of DSP result values. Default conditions are R_ADCRATE = 319, fSYS = 8MHz.

______________________________________________________________________________________ 63
 Low-Power, Multifunction, Polyphase AFE
VFS is full-scale voltage. This is the input voltage that IFS = VFSADC x ITR
MAXQ3180

produces full-scale ADC output; defined by the hard- Default conditions are VFSADC = 1.024V. ITR is design
ware voltage transducer ratio VTR and ADC full-scale dependent.
input voltage VFSADC:
Meter units are defined with respect to the base para-
VFS = VFSADC x VTR meters as shown in Table 5.
Default conditions are VFSADC = 1.024V. VTR is design When reading virtual registers, the MAXQ3180 uses the
dependent. configurable conversion coefficients AMP_CC,
IFS is full-scale current. This is the input current that VOLT_CC, PWR_CC, and ENR_CC to return meaningful
produces full-scale ADC output; defined by the hard- data. Table 6 describes how to set the coefficients.
ware current transducer ratio ITR and ADC full-scale
input voltage VFSADC:

Table 5. Meter Unit Definitions

REGISTER OR ACCUMULATOR METER UNIT (1 LSB)
Current RMS: X.IRMS
Pulse output current RMS MU_AMP = IFS/224
THR1 or THR2, when pulse output configured to IRMS
Voltage RMS: X.VRMS
Pulse output RMS voltage MU_VOLT = VFS/224
THR1, or THR2 when pulse output configured to VRMS
Energy: X.ACT, X.REA, X.APP, X.EAPOS, X.EANEG, X.ERPOS,
X.ERNEG, X.ES
Fundamental Energy: X.ACTF, X.REAF, X.APPF, X.EAFPOS, MU_ENR = VFS x IFS x tFR/216
X.EAFNEG, X.ERFPOS, X.ERFNEG, X.ESF
Pulse Output Energy: THR1 or THR2
Power: PWRP.X, PWRQ.X, PWRS.X MU_PWR = VFS x IFS/232
When X.ESF Contains Amp-Hours: X.ESF MU_AH = IFS x tFR/216
OCLVL, NOLOAD, I1THR, I2THR IFS/216
OVLVL, UVLVL VFS/216

Table 6. Virtual Register Coefficients

OUTPUT RESOLUTION
VIRTUAL REGISTER COEFFICIENT
(1 LSB), DEFINED BY USER

Power:
PWRP.X, PWRQ.X, PWRS.X, PWRPF.X, PWR_LSB PWR_CC = MU_PWR/PWR_LSB
PWRQF.X, PWRSF.X

Voltage:
VOLT_LSB VOLT_CC = MU_VOLT/VOLT_LSB
V.X
Current:
AMP_LSB AMP_CC = MU_AMP/AMP_LSB
I.X

Energy:
ENRP.X, ENRQ.X, ENRS.X, ENRPF.X, ENR_LSB ENR_CC = MU_ENR/ENR_LSB
ENRQF.X, ENRSF.X

64 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE

MAXQ3180
I0P
R1 R2
544kΩ 1kΩ R
10Ω MAXQ3180
VA (AC) VOP
IA (AC) VCOMM
MAXQ3180
R
VN 10Ω

I0N

Figure 13. Sample Voltage Input Circuit Figure 14. Sample Current Input Circuit

Units Conversion Examples operation to convert from the meter unit value
The conversions from meter units to physical units are 0x07654AF0, you would set AMP_CC to 0x0190, and
illustrated with the simplified input circuits in Figures 13 read from virtual register 0x831 (phase A RMS current).
and 14. The voltage input circuit is a voltage-divider. The output would be 0xB8E45170. Dropping the lower
Current input is through a current transfer with turn ratio 2 bytes (right shifting 16 bits) gives 0xB8E4, or 47332
of 2000:1. decimal (47332mA).
The voltage transducer ratio (VTR) = (R1 + R2)/R2 = AMP_CC is computed as follows:
545, VFS = 558.1V. AMP_CC = (IFS/224)/AMP_LSB = MU_AMP/AMP_LSB
The current transducer ratio (ITR) = CT_N/(2 x R) = AMP_LSB = 0.001/216 (A)
2000/(2 x 10) =100 (A/V), IFS = 102.4A.
IFS = 102.4A
The input circuits should be designed to avoid getting
too close to the ADC input full sale at the specified AMP_CC = (102.4/224)/(0.001/216) = 400d = 0x0190
maximum ratings. So for the above circuits, we would
specify the maximum input current = 70A (RMS) and Calibration Procedure
maximum voltage = 390V (RMS), to ensure that peak of Calibration Overview
sinusoudal waveform never exceeds IFS or VFS. Calibration ensures that the recorded voltage, current,
Use the default ADC timing tFR = 320μs, we get the fol- energy, and power are in accordance with the design
lowing meter unit to physical unit conversion coeffi- criteria. Before creating a calibration regimen, establish
cients (these coefficients are not part of the MAXQ3180 the fundamental units of the meter: the full-scale volt-
registers): age and current. Then adjust the gain registers using
calculated calibration constants to produce the expect-
MU_AMP = IFS/224 = 6.1E-6 (A)
ed reading in the raw current, voltage, energy, and
MU_VOLT = VFS/224 = 33.3E-6 (V) power factor registers.
MU_PWR = VFS x IFS/232 = 13.3E-6 (W) The calibration constants should be stored in non-
MU_ENR = VFS x IFS x tFR/216 = 77.5E-9 (Wh) volatile memory by the host microcontroller. Upon any
reset or loss of power, the host microcontroller must
For example, if we get 0x07654AF0 from reading
reload the MAXQ3180 with the constants.
0x1CC register (phase A current RMS), the current
value it represents is Calibration always follows a set of fundamental steps:
0x07654AF0 x MU_AMP = 47.33 (A) • Apply a known signal (voltage/current/power) to the
meter.
For some low-end host microcontrollers, doing the
above math multiplication above could be difficult. For • Read the meter.
this reason, the MAXQ3180 provides conversions for • Calculate the correction factor based on the differ-
some commonly needed parameters through the ence between the applied signal level and the meter
VOLT_CC, AMP_CC, PWR_CC, and ENR_CC registers. reading.
For example, if you want to display current in the reso- • Write the correction factor to the appropriate register.
lution of 1mA, without having to use a multiplication

______________________________________________________________________________________ 65
 Low-Power, Multifunction, Polyphase AFE
• Read the meter quantity again to verify the calibra- tions in the following sections deal specifically with
MAXQ3180

tion. phase A, but the same procedure is followed with phas-

Note that these steps can occur more than once for a es B and C.
given signal type to verify readings at different signal Calibrating Voltage
levels. Ensure that there is no previous value in the gain regis-
There are two methods to read the meter in the above ter, A.V_GAIN, by setting this register to 0x4000.
second step. The first is to read the raw register associ- • Apply a known voltage with RMS value close to the
ated with the value under calibration, for example, desired maximum operating voltage (and less than
A.VRMS for the phase A voltage channel; A.IRMS for VFS/√2).
the phase A current channel, and A.ACT for phase A
real power. • Read the A.VRMS register. Note the value.
The second calibration method assigns a pulse output • Convert the known value to meter units by dividing it
to the value being calibrated and measures the pulse by MU_VOLT (= VFS/224).
period. In practical use, the method chosen depends • Divide the applied value (in meter unit) by the value
on the specific application and the available equip- read from the MAXQ3180. The result should be a
ment. For example, in some applications the voltage value between 0 and 2. If the value falls outside of
and current are of no concern, but the energy accumu- this range, you have probably miscalculated VFS.
lation must be very accurate. For these applications, • Multiply the calculated value by 214. The result is the
meter calibration sets with built-in pulse measurement gain value to be programmed into A.V_GAIN. Ensure
facilities can make the most sense. the most significant bit is 0.
The calibration procedure involves the following gener- When the gain value is programmed, wait for 2 to 3
al steps: seconds, reread the RMS value from A.VRMS. Check
• Calibrate voltage for a given phase by applying a that the measured value is correct by comparing
known voltage and adjusting the voltage gain A.VRMS against the applied voltage in meter unit.
(A.V_GAIN for phase A) until the RMS voltage
(A.VRMS for phase A) reads the applied voltage in Voltage Calibration Example
the designated units. Assumptions: VFS is 558.1V. The applied voltage is 240
VRMS.
• Calibrate current by applying a known current and
adjusting the current gain (A.I_GAIN for phase A) • Convert the applied voltage to meter units. This cal-
until the RMS current (A.IRMS for phase A) reads the culation gives 240 x 2 24 /558.1 = 7,214,714 =
applied current in the designated units. If desired, 0x006E1679.
the current can be calibrated at two points (low • Read the A.VRMS register. You read 0x0708029.
range and high range) for more accuracy. This is 7,372,841 decimal.
• Once the current gain and voltage gain are calibrat- • Divide the applied voltage by the voltage read from
ed, the power/energy should not require any addi- the meter. The result is 7,214,714/7,372,841 =
tional adjustment for most situations. Although, a 0.97855.
separate power gain register is available for further • Convert to integer by multiplying 2 14 : 16,384 x
fine-tuning of the power/energy accuracy. One must 0.97855 = 16,033 = 0x3EA1. Write this value to the
keep in mind that anytime voltage or current is recali- A.V_GAIN register.
brated, the power or energy accuracy is naturally
affected. So the power gain should be recalibrated to Calibrating Current
achieve the desired accumulative effect of voltage, Ensure that there is no previous value in the gain regis-
current, and power gains. ter, A.I_GAIN, by setting this register to 0x4000.
• Calibrate the phase offset by applying a power factor • Apply a known current with RMS value close to the
load and adjusting the phase angle offset according- desired maximum operating current (and much lower
ly. If desired, the phase offset can be calibrated at than IFS/√2).
up to three points for more accuracy.
• Read the A.IRMS register. Note the value.
Once these elements are calibrated for each phase, all
• Convert the known value to meter units by dividing it
other information (power factor, reactive power, appar-
by MU_AMP (= IFS/224).
ent power, etc.)is also properly calibrated. The descrip-

66 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
• Divide the applied value (in meter unit) by the value from the angle read from the reference meter. The

MAXQ3180
read from the MAXQ3180. The result should be a result is the compensation angle.
value between 0 and 2. If the value falls outside of • Multiply the compensation angle (in radians) by
this range, you have probably miscalculated IFS. 65,536. This is the value to write into X.PA0.
• Multiply the calculated value by 214. The result is the If I1THR and I2THR are left at their default values
gain value to be programmed into A.I_GAIN. Ensure (0x0000), then the value in X.PA0 is applied to the full
the most significant bit is 0. measurement range. Alternatively, you could write the
When the gain value is programmed, wait for approxi- same value into X.PA0, X.PA1, and X.PA2. Then the
mately 2 to 3 seconds, then reread the RMS value from same compensation is applied through the whole mea-
A.IRMS. Check that the measured value is correct by surement range regardless of the I1THR and I2THR set-
comparing A.IRMS against the applied current in meter tings. If desired, calibrate for the phase angle at up to
unit. three different current levels to compensate for nonlin-
earity in the current sensor. See the Advanced
Current Calibration Example Operation section for more information.
Assume IFS is 102.4A and the meter has a base current
of 10A and a maximum current of 60A. Phase Offset Calibration Example
• The meter is calibrated at the base current of 10A. Assume the meter is a 10/60 meter; that is, the base
current is 10A and the maximum rated current is 60A.
• Convert the applied current to meter units. This cal- IFS is 102.4A and VFS is 558.1V. The test point is 10A
culation gives 10 x 2 24 /102.4 = 1,638,400 = and 240V.
0x00190000.
• Connect the MAXQ3180-based meter under test in
• Read the A.IRMS register. You read 0x0017DC85. series with a lab grade reference meter. See the con-
This is 1,563,781 decimal. figuration below.
• Divide the applied current by the current read from the • Apply power to the meter and apply a load of 10A
meter. The result is 1,638,400/1,563,781 = 1.0477. resistive.
• Multiply by 214 x 1.0477 = 17,166 = 0x430E. Write • Verify that the I1THR, I2THR, A.PA0, A.PA1, and
this value to the A.I_GAIN register. A.PA2 registers contain zero.
Calibrating Phase Offset • Read the power factor on the reference meter. You
For this calibration step, it is necessary to have a power read 1.5° capacitive. This is not unusual. The load
factor meter, capable of measuring phase angle, con- might not be truly resistive or reactance in the test
nected in the same circuit as the MAXQ3180 meter. configuration could be reflected in the measurement.
Note that calibration can be performed at any precision • Read the real energy from register A.ACT (0x1D0).
power factor setting. We use a pure resistive load (PF = You read 0x2865D6 (2,646,510 meter units).
1.0) load to illustrate the procedure.
• Read the reactive energy from register A.REA
• Apply a resistive load to the meter; the current drawn (0x1D4). You read 0xFFFFA5C0 (-23,104 meter
by the load should correspond to the base current of units).
your meter.
• Divide the reactive by the active power: -23,104/
• Record the phase angle and direction (capacitive or 2,646,510 = -0.009.
inductive) reported on the power factor meter.
• Read and record the real and reactive energy from
the X.ACT and X.REA registers. Divide the reactive
energy by the real energy. This is the tangent of the UNIT
LAB
power-phase angle. METER
UNDER
TEST
• Read the X.REA register. If the high-order bit is set, LOAD
the power factor reported in the above step is capac- V V
itive. If the high-order bit is clear, the power factor LINE
reported in the above step is inductive. NEUTRAL

• Now determine the correction factor: treating capaci-

tive values as negative and inductive values as posi-
tive, subtract the angle read from the MAXQ3180 Figure 15. Offset Testing Setup

______________________________________________________________________________________ 67
 Low-Power, Multifunction, Polyphase AFE
• Take the inverse tangent of this value. You get -0.5°; A delta-connected load can have current measured in
MAXQ3180

that is, 0.5° capacitive. two possible ways. If it is primarily desirable to know
• Subtract the UUT phase offset from the reference how much power is delivered to the load, one can place
meter phase offset. In this case, the phase needs to the current sensor in the load circuit between two phas-
move 1° toward the capacitive. Convert this value to es. But if it is more important to know how much current
radians: 1° x π/180° = 0.0175 radians. is being drawn from each supply phase, each current
sensor is placed in the line circuit of each single phase.
• Multiply this value by 65,536. The result is 572
(0x023C). Most utilities are only concerned with the total amount
of energy being consumed. If individually accounting
• Because the phase correction is toward the capaci- for the power delivered by each phase is not a require-
tive, the value must be complemented. The two’s ment, it is not necessary to measure all three voltages.
complement of 0x023C is 0xFDC4. This is the value Instead, knowing only two voltages and the three cur-
that should be written to the PA0 phase compensa- rents is all that is necessary to measure total energy
tion register. usage.
At this point, the meter is compensated for a single There are several ways of doing this. In a wye arrange-
phase offset. If the phase offset were perfectly flat over ment, one of the phases—usually phase B—–can be
all current levels, that would be sufficient (and for many considered the voltage reference point instead of neu-
current sensors, particularly current shunts, one point is tral. Then the voltage measurements can be made from
usually good enough.) phase A to phase B and from phase C to phase B. By
Interfacing the MAXQ3180 to using some simple arithmetic, the power delivered by
phase A, phase B, and phase C can be calculated
External Hardware even though only two voltages are available.
The MAXQ3180 has all the internal circuitry that is A second mechanism is to have a delta-connected
needed for a sophisticated electricity meter, but specif- load, but with one leg—usually the BC leg—split into
ic external hardware is required when configuring the two equal loads. The point where the load is split is
meter for a particular application. The most critical defined as the reference. In this arrangement, it is only
decision that must be made is how the load will be con- necessary to know the voltage between phase C and
nected to the power source, and how the meter will be the split and phase A and the split, since VC = -VA.
connected to measure power consumed in the load.
This section covers how to select hardware compo- Finally, there is the connection arrangement in which
nents for a MAXQ3180 electricity meter. the load is in a delta configuration with the current sen-
sor at each load, but it is still desired to determine how
Connections to the Power Source much current is in each supply branch. The MAXQ3180
Generally, three-phase power as delivered from the util- supports all of these connection arrangements.
ity consists of four wires: three voltage phases and a
neutral wire. In one typical three-phase delivery system, Sensor Selection
measuring from neutral to any phase would read 120V, The MAXQ3180 supports a variety of voltage and cur-
while measuring from any phase to any other phase rent sense elements. This section describes the proper-
would read 208V. Connecting a load so that load cur- ties of many of these sensing devices.
rent is taken from phase lines and returned to neutral is
called a wye-connected load. Connecting a load so Voltage Sensors
that load current is provided by one phase and Voltage-Divider
returned on another phase is called a delta-connected A voltage-divider is an ideal voltage-sensing element
load. The MAXQ3180 can measure power consumed in when there is no need for voltage isolation. Modern
either a wye-connected or a delta-connected load. resistors have virtually no parasitic capacitance or
If the load is connected in a wye fashion, the voltage is inductance at the frequencies of interest in an electrici-
measured from the neutral lead to each of the phases, ty meter and have extremely low variation with tempera-
and the current measuring device is placed in series ture. When selecting resistors for a voltage-divider,
with the load, most often in the hot lead. The sensor is keep the division ratio high enough so that the peak
not placed in the neutral lead to prevent a customer voltage value cannot exceed the maximum allowable
from defrauding the utility by returning the current to input voltage. In the MAXQ3180, the peak input voltage
ground rather than neutral. A current sensor placed in is about 1V; consequently, a divider in the range of
the hot lead makes fraud even more difficult. 400:1 to 600:1 is ideal.

68 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
The second consideration is the total power dissipation in a shunt produces only a few millivolts of output, mak-

MAXQ3180
and voltage hold-off requirements of the resistor. It is ing a front-end amplifier essential. The MAXQ3180
tempting to design a 400:1 divider with a 400kΩ resis- includes a gain-of-32 amplifier in the current channels
tor in series with a 1kΩ resistor, but that would force the that is automatically cycled in and out, depending on
400kΩ resistor to dissipate about 140mW. This is not an the input voltage of the current channels.
excessive amount of power, but if the design is to use Current shunts operate at line voltage, thus, the AFE
small SMT parts, it can handle greater than a 1/10W must be isolated from the line. That means that in a
SMT resistor. It is better to use a series of several small- wye-connected meter, the current sensing must be per-
er components to improve system reliability. formed in the neutral return circuit (so that all voltages
Voltage Transformer into the current-sense amplifiers are referenced to neu-
If isolation is required between the meter electronics tral). It also means that the use of a shunt is precluded
and the line, a voltage transformer is required. A volt- for delta-connected meters; the MAXQ3180 cannot tol-
age transformer is designed to faithfully transfer an AC erate the line-voltage differential between channels.
voltage applied on the primary side to a sensor on the Current Transformer
secondary side. On the primary side, a voltage-divider In a current transformer, the primary is usually one turn
is used to reduce the voltage to a workable level. On of thick wire or buss bar and the secondary is often
the secondary side, a load resistor is selected so that 1000 turns or more of magnet wire. A ferrite core mag-
the current in the transformer windings is safely within netically couples the two. Thus, a large current in the
the transformer’s linear operating region. primary turn creates a small current but large voltage in
Because the impedance seen in the primary side of the the secondary winding.
transformer is equal to the impedance of the load resis- For example, assume a current transformer with a 1000
tor in the secondary circuit plus impedance of the turn secondary. A 10A current in the primary winding
transformer secondary winding at the operating fre- induces a 10mA current in the secondary. This current
quency, it is easy to calculate the value of the required is made to flow through a so-called “burden” resistor,
voltage-divider resistors in the primary side. For exam- usually 10Ω to 20Ω. Assuming a 20Ω burden, our 10A
ple, assume we want a 500:1 divider ratio and assume current thus produces a 200mV signal in the secondary.
the load resistor is 600Ω and that the impedance of the
transformer secondary is 200Ω. The resistor required in Advanced Operation
the primary is
Modifying the ADC Operation
(600 + 200) x 500 = 400kΩ There are several other registers that directly affect the
Often, this resistor is constructed from multiple AFE function. These registers directly affect the hard-
instances of a smaller value resistor; in this case, one ware functionality, and should be modified only when it
might use eight 50kΩ resistors. Doing so minimizes the is explicitly required. For example, if the MAXQ3180 is
voltage requirements for the resistor chain and reduces operated at some frequency other than the nominal
the possibility that a single point of failure will cause a 8MHz system clock, modification of these registers by
catastrophic failure. supervisory code becomes necessary to maintain a
320μs frame time.
Current Sensors
• R_ACFG: This register contains bits that disable the
Current Shunt ADC entirely, disable the voltage reference buffer
A current shunt is a low-value (approximately 100μΩ to amplifier, and disable the ADC interrupt. Modifying
a 100mΩ) resistor that converts a large-value current this register will likely disable or impair operation of
into a small voltage. Shunts make good current sensors the MAXQ3180 internal firmware.
because the output is an extremely linear representa-
tion of the measured current, current shunts can have • R_ADCRATE: Modify this register to change the rate
very low temperature coefficients, and they are inex- at which the MAXQ3180 acquires samples. By
pensive. default, R_ADCRATE contains 319 decimal, which
means that the ADC acquires a sample every 320
The power dissipated by a current shunt is inversely system clocks. With an 8MHz clock, this translates to
proportional to its resistance and proportional to the 40μs. If the system clock is slower, it may be advan-
square of the output voltage. Consequently, there is tageous to reduce this value to keep a 40μs per sam-
great incentive to reduce the resistance (and hence, ple time constant.
the output voltage) of a shunt. Often, full-scale current

______________________________________________________________________________________ 69
 Low-Power, Multifunction, Polyphase AFE
• R_ADCACQ: Modify this register to change the coefficient and specifies the bandwidth of the funda-
MAXQ3180

acquisition time. The acquisition time is the time from mental mode filter; A1FUND is the feedback coefficient
ADC power-on until conversion starts, and is provid- and specifies the center frequency of the fundamental
ed to allow the input amplifiers to settle. By default mode filter.
this is set to 47 decimal, or 6μs at an 8MHz system In most cases, you can leave these filters at their
clock. If the system clock rate is changed, then default values. If you wish to change the filter parame-
R_ADCACQ should change so that this value ters, first choose the desired bandwidth:
remains about 6μs.
b0 = π x bw x tFR
Fine-Tuning the DSP Controls In this equation, bw is the desired bandwidth in hertz
Fine-Tuning the Line Frequency Measurement and t FR is the frame period, typically 320μs. Set
Line frequency measurement is based on zero-crossing B0FUND to b0 x 216. By default, B0FUND contains dec-
detection. For that purpose each voltage signal is imal 145 (0x91) giving a bandwidth of about 2.2Hz.
passed through a digital lowpass filter, controlled by To set the center frequency, calculate a1 according to
the ZC_LPF register. This register specifies the b0 coef- the following formula:
ficient of a first-order LPF using following formula:
a1 = 2 - 2(1 - b0) x cos(2π x fPK x tFR)
ZC _ LPF In this equation, b0 is the previously calculated feed-
b0 =
2 16 forward coefficient, fPK is the desired center frequency
in hertz, and tFR is the ADC frame period. Set A1FUND
The MSB of this register must be zero. to a1 x 216. By default, A1FUND contains decimal 950
For each phase A, B, and C, the MAXQ3180 counts the (0x3B6) giving a center frequency of 50Hz.
number of scan frames (NS) between zero crossings The fundamental mode filter is, by default, quite sharp
within a DSP cycle. Each individual phase A, B, or C with 3dB points only 1.1Hz off of the center frequency.
zero-crossing event contributes the raw NS count that This means that if the frequency drifts even only slight-
plugs as input to lowpass filter: ly, the fundamental mode power measurement is likely
Yn = Yn - 1 + (AVG_NS/65,536) x (Xn - Yn - 1) to have significant inaccuracy.
The filter coefficient is a signed 16-bit value and can be The MAXQ3180 provides a mechanism to track the fre-
configured by master. Here Y denotes the global NS quency by updating the A1FUND register on each DSP
value, X denotes individual NS measurements pro- cycle. This mechanism is automatically enabled by
duced by zero-crossing events detected on the phase default.
A, B, or C voltage channel. Note that if all three phase You may wish to disable the automatic tracking facility
voltages present, the filter above receives three inputs under some circumstances, particularly if you have
each DSP cycle. The global NS value is used to gener- defined a broader bandwidth than default and are com-
ate the trigger for DSP processing. Note that the NS fortable that the frequency will not drift beyond the
value can be configured by the master, which could be passband. To disable the filter, set the DFUNA bit in the
necessary if all three voltage signals are lost and no OPMODE2 register.
zero-crossings are detected. The line period is then
calculated as a product of NS and the scan frame tFR. You may also elect to disable fundamental mode oper-
The reciprocal of this value is the line frequency, which ation completely. To do this, set the DFUN bit in the
can be obtained as a fixed-point value with 1 LSB = OPMODE2 register.
0.001Hz by reading the LINEFR register. Harmonic Measurement
Fundamental Mode Registers In addition to the ability to measure power and energy
The MAXQ3180 keeps another set of real and virtual at the fundamental frequency, the MAXQ3180 provides
registers to track power and energy at the fundamental a mechanism to isolate a particular harmonic on any
line frequency. These “fundamental mode” registers voltage or current channel and measure the amplitude
behave identically to the standard power and energy of that harmonic.
registers, but are prefiltered to exclude harmonic To enable harmonic measurement, first select a voltage
power. or current channel to monitor. This is done in the
The fundamental mode filter is specified in the B0FUND AUX_CFG register. The AUX_MUX field is the 3-bit
and A1FUND registers. B0FUND is the feed-forward value that selects one of the three voltage channels or
one of the four current channels to monitor.

70 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
The order of the harmonic is set in ORDH field of the returns raw ADC reading of voltage produced by the

MAXQ3180
AUX_CFG register. temperature sensor.
Also in the AUX_CFG register are two bits that enable Conversion from the arbitrary units to useful units (such
the auxiliary channel and enable harmonic measure- as degrees Celsius) requires taking one calibration
ment on the auxiliary channel. To enable the auxiliary point and storing a conversion constant in the host
channel, set the ENAUX bit. Once set, the MAXQ3180 processor. The conversion constant is simply the value
will perform an RMS calculation on the selected chan- (in absolute degrees) of one LSB.
nel. This is useful only for the IN (neutral current) chan- To calculate the LSB value, take a reading at a known
nel, since every other voltage and current already have temperature and divide the known temperature by the
RMS calculations applied by default. (The DADCNV bit reading. For example, assume you take a reading at
should be cleared in the SCAN_IN register in order to room temperature (23°C), and the reading is 0x7F00.
enable sampling the IN channel.) The degrees per LSB are then:
To enable harmonic measurement, set the ENHARM (23 + 273.15)/0x7F00 = 0.00911K
bit. Now, the selected voltage or current signal is
passed to a filter that is identical to the second-order Now, assume at a later time you read the temperature
fundamental filter, but that has separate parameters and see it is 0x84F0. To find the temperature in Celsius,
(A1HARM, B0HARM). multiply by the degrees per LSB and subtract 273.15:
0x84F0 x 0.00911 - 273.15 = 36.8°C
Low-Power Measurement Mode (LOWPM)
This mode enables a subset of metering functions while Advanced Calibrations
operating from the lower frequency internal RC oscilla- Calibrating Current Offset
tor to conserve power. The actual system clock fre- Ideal hardware should produce a current reading lin-
quency used is the RC oscillator output frequency early proportional to the input current. However, due to
divided by 8, which results in a system clock frequency noise or other factors, the RMS current read by the
of approximately 1MHz. meter might not be precisely linear. The current offset
The parameters provided in the LOWPM are: (X.OFFS_HI, X = A/B/C) can be used to compensate
• Voltage RMS the current channel nonlinearity.
• Current RMS Since the MAXQ3180 tracks the input current to deter-
mine what linearity compensation factors to use, the
• Ampere-Hour user must choose two points (ilo and ihi) comfortably
The ampere-hour value is readable from the X.ESF reg- above the low current threshold, and get the X.IRMS
isters (X = A/B/C). Entry to LOWPM mode only occurs current readings (rlo and rhi). Then calculate the Y-inter-
at the request of the master. The master must set the cept of the line drawn between the two points, that is,
LOWPM_E bit (register address 0xC03) to 1 to place the offset. To calculate the value for the offset register,
the MAXQ3180 into LOWPM mode. Entering LOWPM use the following formula. If LINFRM = 0:
mode changes the clock frequency, thereby invalidat-
ing a number of configuration registers. As a result, the r 2i 2 − i hi 2rlo2
offs = hi lo
master must immediately reload the configuration regis- 2 24 (i hi 2 − i lo2 )
ters and filter with new, updated values before metering
measurement operations can continue. If LINFRM = 1:
The master instructs the MAXQ3180 to exit LOWPM r i −i r
mode by reading the LOWPM_X bit (register address offs = hi lo hi lo
0xC04). 2 4 (i lo − i hi )

Temperature In this equation, ihi and rhi are the applied current and
The MAXQ3180 contains a temperature sensor that can the current reading, respectively, in meter units at the
be used by host software for any purpose, including higher of the two reference currents; ilo and rlo are the
compensating power readings for temperature effects. applied current and the current reading, respectively, in
meter units at the lower of the two reference currents.
Use the virtual register command (RAWTEMP, 0xC01)
to perform a temperature conversion. The MAXQ3180 The gain (X.I_GAIN) may require recalibration after the
offset register updated.

______________________________________________________________________________________ 71
 Low-Power, Multifunction, Polyphase AFE
Calibrating Linearity cedure for power/energy gain calibration is outlined for
MAXQ3180

The current channel includes a variable-gain amplifier phase A.

that introduces a gain of 32 when the current falls • Apply a precision unity power factor power (applied
below the low current threshold (about 1/32 of full-scale value) that is close to the desired normal operating
current IFS). Because the gain of the amplifier cannot point.
be controlled with arbitrary precision, and because
high gain implies increased noise, it may be necessary • Read the PWRP.A register. Note the value.
to calibrate the MAXQ3180 to maintain linearity at the • Convert the applied value to meter units by dividing it
lowest inputs. by MU_PWR.
There are two settings that manage low-current lineari- • Divide the applied value (in meter unit) by the value
ty: an offset setting, OFFS_LO; and a gain setting, read from the MAXQ3180. The result should be a
GAIN_LO. Setting the offset is simple. Ensure no cur- value between 0 and 2. If the value falls outside of
rent is flowing in the current circuit. Read X.IRMS. To this range, IFS and/or VFS have probably been mis-
calculate offset use following formula: calculated.
If LINFRM = 0: • Multiply the calculated value by 214, and ensure the
MSB is zero. The result is the gain value to be pro-
(X.IRMS) 2
offs = − grammed into A.E_GAIN.
2 16 • When the gain value is programmed, wait for 1 to 2
If LINFRM = 1: seconds, then reread the power value from PWRP.A.
offs = -X.IRMS Check that the measured value is correct by compar-
ing PWRP.A against the applied power in meter unit.
Program the offs into the OFFS_LO register.
So, if the user reads 0x0113 from the X.IRMS register and Multipoint Phase Offset Calibration
LINFRM = 1, program 0xFEED into the OFFS_LO register. To perform the calibration at three current levels, note
Setting the GAIN_LO register means applying a current the raw current value (X.IRMS) at each point. Label the
below the low-current threshold, reading the value from current values, from highest to lowest, I0, I1, and I2.
the MAXQ3180, and adjusting the gain accordingly. Note Program X.PA0, X.PA1, and X.PA2 with the phase offset
that, unlike offset, the low-end gain is added to the overall values calculated at I 0 , I 1 , and I 2 , respectively, as
gain provided in the I_GAIN register. described in the Calibrating Phase Offset section.
Finally, program I1THR with the average of I0 and I1,
Apply a known current with peak value less than the and program I2THR with the geometric average of I1
low-current threshold. Ensure that there is no previous and I2. Now as the current changes the phase offset is
value in the low-current gain register, A.GAIN_LO, by adjusted accordingly. See Figure 16.
setting this register to 0x4000. Read the A.IRMS regis-
ter (0x1CC). Note the value. Convert the known value to
meter units by multiplying the known value (in amperes)
by 224 and dividing by IFS. Divide the results of this cal- PA2
culation by the value read from the MAXQ3180. The
result should be a value between 0 and 2. Convert the 2
integer by multiplying 214, and ensure MSB is zero. The I2THR
PHASE OFFSET

result is the gain value to be programmed into PA0

A.GAIN_LO.
Calibrating Power/Energy Gain 1
Once voltage and current have been calibrated, the
energy and power calculation automatically reflects the
PA1 I1THR
calibrated voltage and current. However the energy
gain factor (X.E_GAIN, X = A/B/C) can be further tuned
to achieve even more accurate power and energy 0
I2 I1 I0
result if necessary. For example, if the voltage and cur-
rent calibration sources are not as accurate as the INPUT CURRENT
power/energy calibration source, then the additional
gain calibration may be necessary. The following pro- Figure 16. Phase Offset vs. Input Current Calibration

72 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Advanced Register Configurations

MAXQ3180
Analog Scan Configuration Registers
Time Slot Assignment—Current Channel X = A/B/C (SCAN_IX)
(A: 0x008, B: 0x00C, C: 0x00A)
Bit: 7 6 5 4 3 2 1 0
Name: ADCMX DADCNV — — —
Reset A: 0x3 0 0 0 0
Reset B: 0x4 0 0 0 0
Reset C: 0x5 0 0 0 0

These registers configure the time slot normally assigned to current channels A/B/C. We recommend leaving these
registers at their default values. If they must be reassigned, one must ensure that all the current and voltage chan-
nels are reassigned properly so that the MAXQ3180 computes the power/energy parameters as intended by your
setup.

BIT NAME FUNCTION

Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled
during this time slot.
0000 = V0P - VN
0001 = V1P - VN
0010 = V2P - VN
7:4 ADCMX 0011 = I0P - I0N (Phase A Current: 0011)
0100 = I1P - I1N (Phase B Current: 0100)
0101 = I2P - I2N (Phase C Current: 0101)
0110 = INP - VN
1xxx = Temperature
All other values are reserved.
3 DADCNV ADC Disable. When set, disables the ADC for this time slot.
2:0 — Reserved.

______________________________________________________________________________________ 73
 Low-Power, Multifunction, Polyphase AFE
Time Slot Assignment—Voltage Channel X = A/B/C (SCAN_VX)
MAXQ3180

(A: 0x009, B: 0x00D, C: 0x00B)

Bit: 7 6 5 4 3 2 1 0
Name: ADCMX DADCNV PGG
Reset A: 0x0 0 0x0
Reset B: 0x1 0 0x0
Reset C: 0x2 0 0x0

These registers configure the time slot normally assigned to voltage channels A/B/C. The user may wish to change the
PGG settings to match the voltage sensor. However, it is recommended that the user not modify the ADCMX settings.

BIT NAME FUNCTION

Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled
during this time slot.
0000 = V0P - VN (Phase A Voltage: 0000)
0001 = V1P - VN (Phase B Voltage: 0001)
0010 = V2P - VN (Phase C Voltage: 0010)
7:4 ADCMX
0011 = I0P - I0N
0100 = I1P - I1N
0101 = I2P - I2N
0110 = INP - VN
1xxx = Temperature
3 DADCNV ADC Disable. When set, disables the ADC for this time slot.
Programmable Gain Amplifier Select. This three-bit field configures the programmable-gain amplifier at
the front-end of the analog input. The field has the following values:
000 = Gain of 1
001 = Gain of 2
2:0 PGG 010 = Gain of 4
011 = Gain of 8
100 = Gain of 16
101 = Gain of 32
All other values are reserved and can cause unpredictable behavior if selected.

74 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Time Slot Assignment—Neutral Current Channel (SCAN_IN) (0x00E)

MAXQ3180
Bit: 7 6 5 4 3 2 1 0
Name: ADCMX DADCNV — — —
Reset: 0x6 1 0 0 0

This register configures the time slot normally assigned to the neutral current channel. The user can change the
DADCNV bit to enable/disable neutral current sampling. It is recommended to leave the other bits of this register at
their default values.

BIT NAME FUNCTION

Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled
during this time slot. All other values are reserved. By default, this register is set to 0110.
0000 = V0P - VN
0001 = V1P - VN
0010 = V2P - VN
7:4 ADCMX
0011 = I0P - I0N
0100 = I1P - I1N
0101 = I2P - I2N
0110 = INP - VN
1xxx = Temperature
3 DADCNV ADC Disable. When set, disables the ADC for this time slot.
2:0 — Reserved.

______________________________________________________________________________________ 75
 Low-Power, Multifunction, Polyphase AFE
Time Slot Assignment—Temperature Channel (SCAN_TE) (0x00F)
MAXQ3180

Bit: 7 6 5 4 3 2 1 0
Name: ADCMX DADCNV PGG
Reset: 0x8 1 0x2

This register configures the time slot normally assigned to the temperature measurement device. This register is
managed by the firmware and should not be modified by the host.

BIT NAME FUNCTION

Analog Conversion Select. This four-bit field determines which of the following analog inputs are sampled
during this time slot.
0000 = V0P - VN
0001 = V1P - VN
0010 = V2P - VN
0011 = I0P - I0N
7:4 ADCMX
0100 = I1P - I1N
0101 = I2P - I2N
0110 = INP - VN
0111 = Auto-zero ADC
1xxx = Temperature
By default, this register is set to 1000.
3 DADCNV ADC Disable. When set, disables the ADC for this time slot.
Programmable Gain Amplifier Select. This three-bit field configures the programmable-gain amplifier at
the front end of the analog input. The field has the following values:
000 = Gain of 1
001 = Gain of 2
010 = Gain of 4
2:0 PGG
011 = Gain of 8
100 = Gain of 16
101 = Gain of 32
All other values are reserved and can cause unpredictable behavior if selected. This register is managed
by the firmware and should not be modified by the host.

76 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Neutral Current and Harmonics

MAXQ3180
Auxiliary Channel Configuration (AUX_CFG) (0x010)
Bit: 15 14 13 12 11 10 9 8
Name: — — — ORDH
Reset: 0 0 0 0 0 0 0 0

Bit: 7 6 5 4 3 2 1 0
Name: ENHARM ENAUX — — — AUX_MUX
Reset: 0 0 0 0 0 0 0 0

The MAXQ3180 can monitor the RMS value of one auxiliary channel in addition to its normal processing. The
Auxiliary Channel Configuration register selects which input the auxiliary channel processes and what processing is
applied to the auxiliary channel.

BIT NAME FUNCTION

15:13, 5:3 — Reserved.
Order of Harmonic (1–21). The output of harmonic voltage is read via virtual register 0x830 and current
12:8 ORDH
at 0x840.
Enable Auxiliary Channel Harmonic Filter. When set, the auxiliary channel is processed through the
7 ENHARM
harmonic filter. The parameters for this filter can be set in the B0HARM and A1HARM registers.
6 ENAUX Enable Auxiliary Channel. When set, enables auxiliary channel processing.
Auxiliary Channel Input Select. This three-bit field selects the input to be processed by the auxiliary
channel.
001 = IN
010 = VA
2:0 AUX_MUX 011 = IA
100 = VB
101 = IB
110 = VC
111 = IC

DSP System Configuration

System Clock Frequency (SYS_KHZ) (0x012)
Bit: 15 14 13 12 11 10 9 8
Name: System Clock Frequency High Byte
Reset: 0x1F

Bit: 7 6 5 4 3 2 1 0
Name: System Clock Frequency Low Byte
Reset: 0x40

This register contains the system clock frequency in kHz units. Because the default frequency is 8MHz, this register
defaults to 0x1F40.

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 Low-Power, Multifunction, Polyphase AFE
Cycle Count (CYCNT) (0x01C)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: Cycle Count High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Cycle Count Low Byte
Reset: 0x10

This register contains the number of line cycles that will be accumulated in a single DSP cycle. When CYCNT line
cycles have been accumulated, the DSP performs power, power factor, and energy calculations. By default, the
cycle count is 0x10 (16 decimal).

Number of Scan Frames per DSP Cycle (NS) (0x040)

Bit: 31 30 29 28 27 26 25 24
Name: Integer Portion, High Byte
Reset: 0x03

Bit: 23 22 21 20 19 18 17 16
Name: Integer Portion, Low Byte
Reset: 0xE8

Bit: 15 14 13 12 11 10 9 8
Name: Fractional Portion, High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Fractional Portion, Low Byte
Reset: 0x00

The NS register defines the fundamental timing for the electricity meter. It defines a DSP cycle in terms the period of
the ADC scan frame. Generally, this register is calculated and updated automatically by the MAXQ3180 firmware
based on the zero-crossing detection, and whether noise rejection (REJ_NS) and averaging (AVG_NS) are enabled.
Host code can write to this register in order to set the desired DSP cycle duration. The duration of one scan frame
(tFR) is represented as 0x00010000.

78 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Filter Coefficients

MAXQ3180
Line Cycle Noise Rejection Filter (REJ_NS) (0x02C)
Bit: 15 14 13 12 11 10 9 8
Name: Line Cycle Noise Rejection Filter High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Line Cycle Noise Rejection Filter Low Byte
Reset: 0xC8

This register establishes the sensitivity of the NS rejection filter setting. NS is a measure of the line frequency. If a line
cycle occurs that is shorter or longer than the line cycle represented in the NS register, this filter determines whether
the cycle is used to update the NS value. For more information, see the NS register description. If this register is
zero, noise rejection is disabled for the line cycle counter.

Line Cycle Averaging Filter (AVG_NS) (0x02E)

Bit: 15 14 13 12 11 10 9 8
Name: Line Cycle Averaging Filter High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Line Cycle Averaging Filter Low Byte
Reset: 0x00

This register determines whether the NS value is averaged over previous values or whether the most recently measured
value is used directly. If the value of this register is nonzero, the NS value is averaged using the following formula:
x − y n−1
y n = y n−1 + AVG _ NS n
2 16
If the value of this register is zero, NS is not averaged. The MSB of this register must be zero.

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 Low-Power, Multifunction, Polyphase AFE
Meter Measurement Averaging Filter (AVG_C) (0x030)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: Meter Measurement Averaging Filter High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Meter Measurement Averaging Filter Low Byte
Reset: 0x00

This register determines whether the all other measured values in the electricity meter are averaged over time. If the
value of this register is nonzero, all measured meter values are averaged using the following formula:
x − y n−1
y n = y n−1 + AVG _ C n
2 16
If the value of this register is zero, no averaging is performed. The MSB of this register must be zero.

Meter Measurement Highpass Filter (HPF_C) (0x032)

Bit: 15 14 13 12 11 10 9 8
Name: Meter Measurement Highpass Filter High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Meter Measurement Highpass Filter Low Byte
Reset: 0xC8

This register specifies the b0 coefficient of a first-order Butterworth filter using the following formula:
HPF _ C
b0 =
2 16
The MSB of this register must be zero.

80 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Fundamental Filter Feed-Forward Coefficient (B0FUND) (0x034)

MAXQ3180
Bit: 15 14 13 12 11 10 9 8
Name: Fundamental Filter Feed-Forward Coefficient High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Fundamental Filter Feed-Forward Coefficient Low Byte
Reset: 0x91

This register specifies the b0 (feed-forward) coefficient for the fundamental-mode filter using the following formula:
B0FUND
b0 =
2 16
The MSB of this register must be zero.

Fundamental Filter Feedback Coefficient (A1FUND) (0x036)

Bit: 31 30 29 28 27 26 25 24
Name: Fundamental Filter Feedback Coefficient Byte 3
Reset: 0x00

Bit: 23 22 21 20 19 18 17 16
Name: Fundamental Filter Feedback Coefficient Byte 2
Reset: 0x00

Bit: 15 14 13 12 11 10 9 8
Name: Fundamental Filter Feedback Coefficient Byte 1
Reset: 0x03

Bit: 7 6 5 4 3 2 1 0
Name: Fundamental Filter Feedback Coefficient Byte 0
Reset: 0xB6

This register specifies the a1 (feedback) coefficient for the fundamental-mode filter using the following formula:
A1FUND
a1 =
2 16

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 Low-Power, Multifunction, Polyphase AFE
Harmonic Filter Feed-Forward Coefficient (B0HARM) (0x03A)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: Harmonic Filter Feed-Forward Coefficient High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Harmonic Filter Feed-Forward Coefficient Low Byte
Reset: 0x91

This register specifies the b0 (feed-forward) coefficient for the harmonic-mode filter using the following formula:
B0HARM
b0 =
2 16
The MSB of this register must be zero.

Harmonic Filter Feedback Coefficient (A1HARM) (0x03C)

Bit: 31 30 29 28 27 26 25 24
Name: Harmonic Filter Feedback Coefficient Byte 3
Reset: 0x00

Bit: 23 22 21 20 19 18 17 16
Name: Harmonic Filter Feedback Coefficient Byte 2
Reset: 0x00

Bit: 15 14 13 12 11 10 9 8
Name: Harmonic Filter Feedback Coefficient Byte 1
Reset: 0x18

Bit: 7 6 5 4 3 2 1 0
Name: Harmonic Filter Feedback Coefficient Byte 0
Reset: 0x31

This register specifies the a1 (feedback) coefficient for the harmonic mode filter using the following formula:
A1HARM
a1 =
2 16

Zero-Cross Lowpass Filter (ZC_LPF) (0x05A)

Bit: 15 14 13 12 11 10 9 8
Name: Zero-Cross Lowpass Filter High Byte
Reset: 0x0B

Bit: 7 6 5 4 3 2 1 0
Name: Zero-Cross Lowpass Filter Low Byte
Reset: 0x00

This register specifies the lowpass filter applied for zero-cross detection. The MSB of this register must be zero.

82 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Hardware Mirror Registers

MAXQ3180
ADC Configuration (R_ACFG) (0x04C)
Bit: 7 6 5 4 3 2 1 0
Name: ADCASD ADCRY ADCCD ADCBY ADCIE ARBE ADCE
Reset: 0 0 0x0 0 1 1 1

This register is a mirror of a CPU register in the MAXQ3180. This register should not be modified by supervisory
code.

BIT NAME FUNCTION

Disable ADC Automatic Shutdown. Normally, the ADC analog section is powered off following a
7 ADCASD conversion to conserve power. If this bit is set, the ADC leaves the analog section powered on
following a conversion.

ADC Data Ready. When a conversion is complete, this bit is set to indicate that data is available. This
6 ADCRY
bit generates an interrupt if ADCIE is set.
ADC Clock Divider. Sets the division ratio between the CPU master and ADC clock.
00 = divide by 1
5:4 ADCCD 01 = divide by 2
10 = divide by 4
11 = reserved
ADC Busy. When set, a single ADC conversion cycle is in progress. The bit is cleared on the
3 ADCBY
conclusion of the conversion cycle.
2 ADCIE ADC Interrupt Enable. If set, the ADC interrupts the CPU at the completion of a conversion cycle.
1 ARBE Reference Buffer Enable. If set, the reference buffer is enabled to drive the REFO pin.
0 ADCE ADC Enable. If set, the ADC hardware is activated.

ADC Conversion Rate (R_ADCRATE) (0x04E)

Bit: 15 14 13 12 11 10 9 8
Name: ADC Conversion Rate High Byte
Reset: — — — — — — — 1

Bit: 7 6 5 4 3 2 1 0
Name: ADC Conversion Rate Low Byte
Reset: 0x3F

This register specifies the number of system clock cycles between consecutive ADC conversions. It defaults to
0x13F (319 decimal), which specifies 320 CPU clock cycles between conversions. This register is a mirror of a CPU
register in the MAXQ3180.

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 Low-Power, Multifunction, Polyphase AFE
ADC Settling Time (R_ADCACQ) (0x050)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: ADC Settling Time High Byte
Reset: — — — — — — — —

Bit: 7 6 5 4 3 2 1 0
Name: ADC Settling Time Low Byte
Reset: — 0x2F

This register is a mirror of a CPU register in the MAXQ3180. This register should not be modified by supervisory
code. This register specifies the time, in CPU clocks, that the ADC must wait after switching analog mux inputs
before beginning its conversion. This register defaults to 0x2F (47 decimal), which specifies a 48 CPU clock-cycle
delay from analog mux switching to the start of conversion.

SPI Configuration (R_SPICF) (0x052)

Bit: 7 6 5 4 3 2 1 0
Name: ESPII SAS — — — CHR CKPHA CKPOL
Reset: 1 0 0 0 0 0 0 0

This register is a mirror of a CPU register in the MAXQ3180. This register configures the SPI port of the MAXQ3180.

BIT NAME FUNCTION

7 ESPII Enable SPI Interrupt. If set, arrival of a character on the SPI bus causes a CPU interrupt.
SPI Slave Select Polarity. If clear, SSEL is assumed to be active low; if set, SSEL is assumed to be
6 SAS
active high.
5:3 — Reserved.
SPI Character Length. If clear, characters on the SPI bus are assumed to be 8 bits; if set, characters on
2 CHR
the SPI bus are assumed to be 16 bits.

SPI Clock Phase. If clear, data is sampled on the leading edge of the clock (low-to-high if the clock is
1 CKPHA active high, and high-to-low if the clock is active low). If set, data is sampled on the trailing edge of the
clock (high-to-low if the clock is active high, and low-to-high if the clock is active low).

SPI Clock Polarity. If clear, the clock is assumed to be active high; if set, the clock is assumed to be
0 CKPOL
active low.

84 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Timeouts

MAXQ3180
Zero-Crossing Timeout (NZX_TIMO) (0x054)
Bit: 15 14 13 12 11 10 9 8
Name: Zero-Crossing Timeout High Byte
Reset: 0x23

Bit: 7 6 5 4 3 2 1 0
Name: Zero-Crossing Timeout Low Byte
Reset: 0x28

This register specifies the time in ADC sample periods (default 40μs) that must elapse following a zero-crossing
event before the MAXQ3180 declares a “no-zero crossing” fault. When this fault is declared, the NOZXF bit in the
X.FLAGS register is set.

Communications Timeout (COM_TIMO) (0x056)

Bit: 15 14 13 12 11 10 9 8
Name: Communications Timeout High Byte
Reset: 0x03

Bit: 7 6 5 4 3 2 1 0
Name: Communications Timeout Low Byte
Reset: 0xE8

This register specifies the duration of SPI timeout in ADC frames (default 320μs).

Energy Accumulation Timeout (ACC_TIMO) (0x058)

Bit: 15 14 13 12 11 10 9 8
Name: Energy Accumulation Timeout High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Energy Accumulation Timeout Low Byte
Reset: 0x05

This register specifies the time in DSP cycles that the MAXQ3180 waits before accumulating energy. If this register is
nonzero, it is decremented on each DSP cycle. If the result of the decrement is nonzero, the results of the DSP cycle
are discarded and are not accumulated to the energy registers. This register is useful for delaying the initiation of
energy accumulation on startup or after some hardware function has been modified.

______________________________________________________________________________________ 85
 Low-Power, Multifunction, Polyphase AFE
Phase-Angle Compensation
MAXQ3180

Phase Offset Current Threshold 1 (I1THR) (0x05C)

Bit: 15 14 13 12 11 10 9 8
Name: Phase Accumulator Current Threshold 1 High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Phase Accumulator Current Threshold 1 Low Byte
Reset: 0x00

This register specifies the fraction of full-scale current that causes the MAXQ3180 to switch from PA0 to PA1 to pro-
vide phase-angle compensation. For more information, see the PA0, PA1, and PA2 register descriptions. The full-
scale current is represented by 0x10000.

Phase Offset Current Threshold 2 (I2THR) (0x05E)

Bit: 15 14 13 12 11 10 9 8
Name: Phase Accumulator Current Threshold 2 High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Phase Accumulator Current Threshold 2 Low Byte
Reset: 0x00

This register specifies the fraction of full-scale current that causes the MAXQ3180 to switch from PA1 to PA2 to pro-
vide phase-angle compensation. For more information, see the PA0, PA1, and PA2 register descriptions. The full-
scale current is represented by 0x10000.

Miscellaneous Gain
Neutral Current Gain (N.I_GAIN) (0x12E)
Bit: 15 14 13 12 11 10 9 8
Name: Compensation Coefficient High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Compensation Coefficient Low Byte
Reset: 0x00

This register contains gain compensation coefficient for the neutral current channel measurement. The raw values
are taken from the selected measurement quantity and scaled by N.I_GAIN/214.

86 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Gain, Fundamental Energy, Phase X = A/B/C (X.EF_GAIN) (A: 0x136, B: 0x222, C: 0x30E)

MAXQ3180
Bit: 15 14 13 12 11 10 9 8
Name: Gain Coefficient High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Gain Coefficient Low Byte
Reset: 0x00

This register contains gain coefficient for phase X fundamental energy. The raw values are taken from the selected
measurement quantity and scaled by the following factor:
X.EF _ GAIN
2 14
Linearity Compensation
Linearity Offset, High Range, Phase X = A/B/C (X.OFFS_HI) (A: 0x138, B: 0x224, C: 0x310)
Bit: 15 14 13 12 11 10 9 8
Name: Linearity Offset High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Linearity Offset Low Byte
Reset: 0x00

This signed register contains the linearity offset for phase X current channel when the programmable gain amplifier
is set to unity gain (that is, the measured current is above the low current threshold). The signed value represented
by this register is added to the current value according to following formula:

if LINFRM = 0: X.IRMS 2 + X.OFFS _ HI × 2 24

if LINFRM = 1: X.IRMS + X.OFFS_HI x 24

Linearity Gain Coefficient, Low Range, Phase X = A/B/C (X.GAIN_LO)

(A: 0x13A, B: 0x226, C: 0x312)
Bit: 15 14 13 12 11 10 9 8
Name: Linearity Coefficient High Byte
Reset: 0x40

Bit: 7 6 5 4 3 2 1 0
Name: Linearity Coefficient Low Byte
Reset: 0x00

This register contains the linearity coefficient for phase X current channel when the programmable gain amplifier is
set to gain of 32 (that is, the measured current is below the low current threshold). The effective gain is given by the
equation:
X.GAIN _ LO
2 14

______________________________________________________________________________________ 87
 Low-Power, Multifunction, Polyphase AFE
Linearity Offset, Low Range, Phase X = A/B/C (X.OFFS_LO) (A: 0x13C, B: 0x228, C: 0x314)
MAXQ3180

Bit: 15 14 13 12 11 10 9 8
Name: Linearity Offset High Byte
Reset: 0x00

Bit: 7 6 5 4 3 2 1 0
Name: Linearity Offset Low Byte
Reset: 0x00

This signed register contains the linearity offset for phase X current channel when the programmable gain amplifier
is set to gain of 32 (that is, the measured current is below the low current threshold). The signed value represented
by this register is added to the current value. The total linearity compensation is applied as follows:

if LINFRM = 0: X.GAIN_LO/214 x X.IRMS 2 + X.OFFS _ LO × 2 16

if LINFRM = 1: X.GAIN_LO/214 x (X.IRMS + X.OFFS_LO)

Measurements—RAM Registers
On-Demand RMS Result (N.IRMS) (0x11C)
Bit: 31 30 29 28 27 26 25 24
Name: RMS Result, Byte 3
Reset:

Bit: 23 22 21 20 19 18 17 16
Name: RMS Result, Byte 2
Reset:

Bit: 15 14 13 12 11 10 9 8
Name: RMS Result, Byte 1
Reset:

Bit: 7 6 5 4 3 2 1 0
Name: RMS Result, Byte 0
Reset:

This register contains the result of the RMS calculation on the AUX channel. Usually, this is the neutral current chan-
nel, but can be defined to be the RMS average of any harmonic of the quantities defined in the AUX_MUX field of the
AUX_CFG register.

88 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Fundamental Energy

MAXQ3180
Fundamental Energy Overflow Flags, Phase X = A/B/C (X.EFOVER)
(A: 0x147, B: 0x233, C: 0x31F)
Bit: 7 6 5 4 3 2 1 0
Name: — — — SFOV RNFOV RPFOV ANFOV APFOV
Reset: 0 0 0 0 0 0 0 0

These bits indicate an overflow condition has occurred on a fundamental frequency energy accumulator. An over-
flow condition is not an error condition. Rather, it simply indicates that the value in the energy accumulator could be
smaller than the previous reading due to the overflow in the counter. To obtain the actual energy usage since the
previous reading, 0x100000000 must be added to the difference. These bits, once set, can be cleared only by the
host.

BIT NAME FUNCTION

7:5 — Reserved.
4 SFOV When set, indicates an overflow condition on the apparent fundamental-mode energy accumulator.
3 RNFOV When set, indicates an overflow condition on the reactive negative fundamental-mode energy accumulator.
2 RPFOV When set, indicates an overflow condition on the reactive positive fundamental-mode energy accumulator.
1 ANFOV When set, indicates an overflow condition on the real negative fundamental-mode energy accumulator.
0 APFOV When set, indicates an overflow condition on the real positive fundamental-mode energy accumulator.

Energy, Fundamental, Real Positive, Phase X = A/B/C (X.EAFPOS)

(A: 0x1FC, B: 0x2E8, C: 0x3D4)
Bit: 31 30 29 28 27 26 25 24
Name: Real Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Real Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Real Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Real Energy Byte 0

On every DSP cycle, the contents of the X.ACTF register are tested, and if positive, are added to this register. When
this register overflows, the APFOV bit in the X.EFOVER register is set.

______________________________________________________________________________________ 89
 Low-Power, Multifunction, Polyphase AFE
Energy, Fundamental, Real Negative, Phase X = A/B/C (X.EAFNEG)
MAXQ3180

(A: 0x200, B: 0x2EC, C: 0x3D8)

Bit: 31 30 29 28 27 26 25 24
Name: Real Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Real Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Real Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Real Energy Byte 0

On every DSP cycle, the contents of the X.ACTF register are tested, and, if negative, absolute values are added to
this register. When this register overflows, the ANFOV bit in the X.EFOVER register is set.

Energy, Fundamental, Reactive Positive, Phase X = A/B/C (X.ERFPOS)

(A: 0x204, B: 0x2F0, C: 0x3DC)
Bit: 31 30 29 28 27 26 25 24
Name: Reactive Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Reactive Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Reactive Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Reactive Energy Byte 0

On every DSP cycle, the contents of the X.REAF register are tested, and, if positive, are added to this register. When
this register overflows, the RPFOV bit in the X.EFOVER register is set.

90 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Energy, Fundamental, Reactive Negative, Phase X = A/B/C (X.ERFNEG)

MAXQ3180
(A: 0x208, B: 0x2F4, C: 0x3E0)
Bit: 31 30 29 28 27 26 25 24
Name: Reactive Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Reactive Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Reactive Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Reactive Energy Byte 0

On every DSP cycle, the contents of the X.REAF register are tested, and, if negative, absolute values are added to
this register. When this register overflows, the RNFOV bit in the X.EFOVER register is set.

Energy Fundamental, Apparent, Phase X = A/B/C (X.ESF)

(A: 0x20C, B: 0x2F8, C: 0x3E4)
Bit: 31 30 29 28 27 26 25 24
Name: Apparent Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Apparent Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Apparent Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Apparent Energy Byte 0

On every DSP cycle, the contents of the X.ESF register are added to this register. When this register overflows, the
SFOV bit in the X.EFOVER register is set. When the MAXQ3180 is operating in low-power mode, energy is not accu-
mulated. However, during low-power mode, current values are accumulated to this register, making this register
accumulate ampere-hours.

______________________________________________________________________________________ 91
 Low-Power, Multifunction, Polyphase AFE
Energy Accumulated in the Last DSP Cycle
MAXQ3180

Real Energy, Phase X = A/B/C (X.ACT) (A: 0x1D0, B: 0x2BC, C: 0x3A8)

Bit: 31 30 29 28 27 26 25 24
Name: Real Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Real Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Real Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Real Energy Byte 0

This signed register provides the raw real energy accumulated over the most recent DSP cycle. For each ADC sam-
ple period, the real instantaneous power calculated from the instantaneous voltage and current is accumulated. At
the end of each DSP cycle, the result of the accumulation over the DSP cycle is copied to this register and is accu-
mulated in X.EAPOS or X.EANEG, depending on the sign of the accumulated energy.
LSB of the energy registers is VFS x IFS x tFR/216.

Reactive Energy, Phase X = A/B/C (X.REA) (A: 0x1D4, B: 0x2C0, C: 0x3AC)

Bit: 31 30 29 28 27 26 25 24
Name: Reactive Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Reactive Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Reactive Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Reactive Energy Byte 0

This signed register provides the raw reactive energy accumulated over the most recent DSP cycle. For each ADC
sample period, the reactive instantaneous power calculated from the instantaneous voltage and current is accumu-
lated. At the end of each DSP cycle, the result of the accumulation over the DSP cycle is copied to this register and
is accumulated in X.ERPOS or X.ERNEG, depending on the sign of the accumulated energy.

92 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Apparent Energy, Phase X = A/B/C (X.APP) (A: 0x1D8, B: 0x2C4, C: 0x3B0)

MAXQ3180
Bit: 31 30 29 28 27 26 25 24
Name: Apparent Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Apparent Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Apparent Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Apparent Energy Byte 0

This signed register provides the raw apparent energy accumulated over the most recent DSP cycle.

Fundamental Energy Accumulated in the Last DSP Cycle

Fundamental Real Energy, Phase X = A/B/C (X.ACTF) (A: 0x1DC, B: 0x2C8, C: 0x3B4)
Bit: 31 30 29 28 27 26 25 24
Name: Real Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Real Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Real Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Real Energy Byte 0

This signed register accumulates energy in the same fashion as the X.ACT register, but only at the fundamental line
frequency.

______________________________________________________________________________________ 93
 Low-Power, Multifunction, Polyphase AFE
Fundamental Reactive Energy, Phase X = A/B/C (X.REAF) (A: 0x1E0, B: 0x2CC, C: 0x3B8)
MAXQ3180

Bit: 31 30 29 28 27 26 25 24
Name: Reactive Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Reactive Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Reactive Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Reactive Energy Byte 0

This signed register accumulates energy in the same fashion as the X.REA register, but only at the fundamental line
frequency.

Fundamental Apparent Energy, Phase X = A/B/C (X.APPF) (A: 0x1E4, B: 0x2D0, C: 0x3BC)
Bit: 31 30 29 28 27 26 25 24
Name: Apparent Energy Byte 3

Bit: 23 22 21 20 19 18 17 16
Name: Apparent Energy Byte 2

Bit: 15 14 13 12 11 10 9 8
Name: Apparent Energy Byte 1

Bit: 7 6 5 4 3 2 1 0
Name: Apparent Energy Byte 0

This register accumulates energy in the same fashion as the X.APP register, but only at the fundamental line frequency.

94 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Checksum (CHKSUM) (0x060)

MAXQ3180
Bit: 15 14 13 12 11 10 9 8
Name: Checksum High Byte
Reset:

Bit: 7 6 5 4 3 2 1 0
Name: Checksum Low Byte
Reset:

This register contains the calculated 16-bit arithmetic checksum over critical configuration and calibration registers.
It is updated on every DSP cycle. In use, the administrative processor records the value in the CHKSUM register and
then checks it periodically to verify that no configuration or calibration registers have changed. The MAXQ3180 sets
the CHSCH bit when this register’s value changes.
The registers included in the checksum calculation include the following:

SYS_KHZ THR2 R_ADCRATE A.I_GAIN B.I_GAIN C.I_GAIN

VOLT_CC REJ_NS R_ADCACQ A.V_GAIN B.V_GAIN C.V_GAIN
AMP_CC AVG_NS R_SPICF A.E_GAIN B.E_GAIN C.E_GAIN
PWR_CC AVG_C NZX_TIMO A.EF_GAIN B.EF_GAIN C.EF_GAIN
ENR_CC HPF_C COM_TIMO A.OFFS_HI B.OFFS_HI C.OFFS_HI
CYCNT B0FUND ACC_TIMO A.GAIN_LO B.GAIN_LO C.GAIN_LO
PLSCFG1 OCLVL I1THR A.OFFS_LO B.OFFS_LO C.OFFS_LO
PLSCFG2 OVLVL I2THR A.PA0 B.PA0 C.PA0
PLS1_WD UVLVL ZC_LPF A.PA1 B.PA1 C.PA1
THR1 NOLOAD A.PA2 B.PA2 C.PA2
PLS2_WD R_ACFG

______________________________________________________________________________________ 95
 Low-Power, Multifunction, Polyphase AFE
Measurements—Virtual Registers
MAXQ3180

Fundamental Real Power, Phase A/B/C/T (PWRPF.X)

(A: 0x881, B: 0x882, C: 0x884, T: 0x887)
This signed register contains the real instantaneous power delivered into phase A/B/C or total at the fundamental line
frequency only. Power is calculated from the instantaneous energy measurement according to the following equation:
X.ACTF × PWR _ CC × 2 16
PWRPF.X =
NS

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Fundamental Reactive Power, Phase A/B/C/T (PWRQF.X)

(A: 0x891, B: 0x892, C: 0x894, T: 0x897)
This signed register contains the reactive instantaneous power delivered into phase A/B/C or total at the fundamental
line frequency only. Power is calculated from the instantaneous energy measurement according to the following
equation:
X.REAF × PWR _ CC × 2 16
PWRQF.X =
NS

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

96 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Fundamental Apparent Power, Phase A/B/C/T (PWRSF.X)

MAXQ3180
(A: 0x8A1, B: 0x8A2, C: 0x8A4, T: 0x8A7)
This register contains the instantaneous apparent power delivered into phase A/B/C or total at the fundamental line
frequency only. Power is calculated from the instantaneous energy measurement according to the following equation:
X.APPF × PWR _ CC × 2 16
PWRSF.X =
NS

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Fundamental Real Energy, Phase A/B/C/T (ENRPF.X)

(A: 0x8E1, B: 0x8E2, C: 0x8E4, T: 0x8E7)
This signed register contains the real accumulated energy delivered into phase A/B/C or total. The register is calcu-
lated according to the following formula:
ENRPF.X = ENR_CC x (X.EAFPOS - X.EAFNEG)

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Fundamental Reactive Energy, Phase A/B/C/T (ENRQF.X)

(A: 0x8F1, B: 0x8F2, C: 0x8F4, T: 0x8F7)
This signed register contains the reactive accumulated energy delivered into phase A/B/C or total. The register is
calculated according to the following formula:
ENRQF.X = ENR_CC x (X.ERFPOS - X.ERFNEG)

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

Fundamental Apparent Energy, Phase A/B/C/T (ENRSF.X)

(A: 0x8B1, B: 0x8B2, C: 0x8B4, T: 0x8B7)
This register contains the apparent accumulated energy delivered into phase A/B/C or total. The register is the prod-
uct of the ENR_CC and X.ESF registers.

Byte 7 (MSByte unused) Byte 6 (unused)

Byte 5 Byte 4
Byte 3 Byte 2
Byte 1 Byte 0 (LSByte)

______________________________________________________________________________________ 97
 Low-Power, Multifunction, Polyphase AFE
Phasors AUX_CFG to configure the phase (A/B/C) and harmonic
MAXQ3180

Phase B Phasor (VBPH: 0x852) order desired.

This register reports phase angle of voltage phase B Ratio of Harmonic/Fundamental (HARM_NF) (0x850)
with respect to voltage phase A. The value is This register reports the ratio of the selected harmonic
expressed in units of 0.01 degree; thus, the nominal RMS over the fundamental RMS of the same signal
value is 12000 decimal (0x2EE0). This value is calculat- (except IN). The master must configure the AUX_CFG
ed based on zero-crossing detection. It may exhibit register to enable the AUX channel, enable harmonics,
noticable error in the presence of harmonics on voltage and select AUX_MUX before reading this register. This
channels. This register is 2 bytes wide. register is 4 bytes wide with the resolution of 1/216.
Phase C Phasor (VCPH: 0x854) Special Commands
This register reports phase angle of voltage phase C Table 7 shows the read-only virtual registers that acti-
with respect to voltage phase A. The value is vate special commands when read by the master.
expressed in units of 0.01 degree; thus, the nominal Some commands return dummy values.
value is 24000 decimal (0x5DC0). This value is calcu-
lated based on zero-crossing detection. It may exhibit Applications Information
noticable error in the presence of harmonics on voltage
channels. This register is 2 bytes wide. Grounds and Bypassing
Careful PCB layout significantly minimizes noise on the
Harmonics analog inputs, resulting in less noise on the digital I/O
RMS Voltage, Harmonic (V.HARM) (0x830) that could cause improper operation. The use of multi-
This register reports the RMS voltage. The units are layer boards is essential to allow the use of dedicated
defined by the VOLT_CC setting. Use AUX_CFG to power planes. The area under any digital components
configure the phase (A/B/C) and harmonic order should be a continuous ground plane if possible. Keep
desired. any bypass capacitor leads short for best noise rejec-
tion and place the capacitors as close to the leads of
RMS Current, Harmonic/Neutral (I.N, I.HARM) (0x840) the devices as possible.
This register reports the harmonic RMS current of The MAXQ3180 must have separate ground areas for
selected phase (A/B/C) and harmonic order, harmonic, the analog (AGND) and digital (DGND) portions, con-
or the RMS current of the neutral current channel. The nected together at a single point.
units are defined by the AMP_CC setting. Use

Table 7. Virtual Registers That Activate Special Commands

DATA
NAME ADDRESS DESCRIPTION LENGTH
(BYTES)
Reading this register copies the mirror registers (R_ADCF, R_ADCRATE,
UPD_SFR 0x900 1
R_ADCACQ, R_SPICF) into hardware SFR registers. The read returns dummy data.
Reading this register copies hardware SFR registers into mirror registers (R_ADCF,
UPD_MIR 0xA00 1
R_ADCRATE, R_ADCACQ, R_SPICF). The read returns dummy data.
DSPVER 0xC00 Reading this register returns the DSP firmware version number. 2
Reading this register initiates the sampling and averaging of two internal
temperature readings. The result in internal temperature units is read from this
register LSB first. Use the following equation to convert a raw temperature reading to
RAWTEMP 0xC01 2
Celsius: T[c] = T[raw] x TempFactor - 273.15
where TempFactor is a value to be determined by calibration. Note that the final
value may be slightly higher than ambient due to internal die heating.
ENTER STOP 0xC02 Reading this register places the device into Stop Mode. 1
ENTER LOWPM 0xC03 Reading this register places the device into LOWPM Mode. 1
EXIT LOWPM 0xC04 Reading this register exits LOWPM Mode. 1

98 ______________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
CMOS design guidelines for any semiconductor require Additional Documentation

MAXQ3180
that no pin be taken above DVDD or below DGND. Designers must ensure they have the latest MAXQ3180
Violation of this guideline can result in a hard failure errata documents. Errata sheets contain deviations
(damage to the silicon inside the device) or a soft fail- from published specifications. A MAXQ3180 errata
ure (unintentional modification of memory contents). sheet for any specific device revision is available at
Voltage spikes above or below the device’s absolute www.maxim-ic.com/errata.
maximum ratings can potentially cause a devastating
IC latchup. Technical Support
Microcontrollers commonly experience negative volt- For technical support, go to https://support.maxim-
age spikes through either their power pins or general- ic.com/micro.
purpose I/O pins. Negative voltage spikes on power
pins are especially problematic as they directly couple Pin Configuration
to the internal power buses. Devices such as keypads
can conduct electrostatic discharges directly into the TOP VIEW
microcontroller and seriously damage the device.
System designers must protect components against
VN 1 28 V2P
these transients that can corrupt system memory.
INP 2 27 V1P
Specific Design Considerations for I0P 3 26 V0P
MAXQ3180-Based Systems I0N 4 25 AVDD
To reduce the possibility of coupling noise into the
I1P 5 24 VREF
microcontroller, the system should be designed with a
crystal or oscillator in a metal case that is grounded to I1N 6 23 VCOMM
the digital plane. Doing so reduces the susceptibility of I2P 7 22 DVDD
the design to fast transient noise. I2N 8 MAXQ3180 21 RESET
Because the MAXQ3180 is designed for use in systems AGND 9 20 CFQ
where high voltages are present, care must be taken to XTAL2 10 19 CFP
route all signal paths, both analog and digital, as far
XTAL1 11 18 DGND
away as possible from the high-voltage components.
IRQ 12 17 DVDD
It is possible to construct more elaborate metering
SSEL 13 16 MISO
designs using multiple MAXQ3180 devices. This can be
accomplished by using a single SPI bus to connect all SCLK 14 15 MOSI
the MAXQ3180 devices together but using separate
slave select lines to individually select each MAXQ3180. TSSOP

Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TSSOP U28+3 21-0066

______________________________________________________________________________________ 99
 Low-Power, Multifunction, Polyphase AFE
Typical Application Circuit
MAXQ3180

VOLTAGE SENSE
R1
VA V0P

R2

R1
VB V1P

R2
MAXQ3180
R1
VC V2P

R2

VCOMM
CURRENT TRANSFORMER VN
I0P

R3

R3

I0N
I1P

R3

R3

I1N
I2P

R3

R3

I2N
SCLK
MOSI
MISO
SSEL

LA LB LC

N
MASTER

100 _____________________________________________________________________________________
 Low-Power, Multifunction, Polyphase AFE
Revision History

MAXQ3180
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 2/08 Initial release. —

1 1/09 Updated data sheet to be consistent with additional device features. All
Removed reference to the device supporting IEC standards in the Features section;
1
changed the precision internal voltage reference spec from 1.23V to 2.048V.
In the Electrical Characteristics table, changed stop-mode current TYP and MAX from
1μA and 0μA to 0.2μA and 12μA, respectively; changed the input voltage range MAX
from 2V to VREF V; added VREF to output voltage SYMBOL; changed the t SCH and tSCL
MIN to 4 x tSYS and added Note 3 to CONDITIONS; changed the output voltage spec
10, 11, 12
for the internal voltage reference from 1.23V (typ) to 2.048V (typ); changed the
maximum SPI clock rate spec for the SPI slave-mode interface timing from 2MHz
(max) to f SYS/4MHz (max), and changed the t SE, t SD, t SIS, t SIH, and t SOV specs;
updated the SPI Slave Mode Timing diagram.

Updated the CFP and CFQ descriptions in the Pin Description table. 14
Removed statement about the IRQ line dropping low when reset causes the device
17
to enter Initialization Mode in the Watchdog Reset section.
Added new paragraph to the Host Software Design section about reading the virtual
24
registers.
2 8/09 Removed the Code Examples section. 26, 27, 28
Updated the bit functions for PORF and WDTR in the Global Status Register (STATUS)
28
(0x000) section.
Added bit 14 functionality (DSPRDY) to the IRQ_FLAG register. 33
Added bit 14 functionality (EDSPRDY) to the IRQ_MASK register and updated the
34
EDSPOR function description.
Corrected the reset valued for the OCLVL, OVLVL, and SYS_KHZ registers. 40, 41, 77
Corrected the reference of V/A to A/V in the Units Conversion Examples section
65
current transducer ratio (ITR) equation.
Updated the bit description for ADCMX (SCAN_IX.7:4, SCAN_VX.7:4, SCAN_IN.7:4)
73, 74
and PGG.
Updated the descriptions of the SCAN_IN and SCAN_TE registers. 75, 76

Corrected the reset value to 1 for bit 8 in the R_ADCRATE register. 83

Updated the phase B phasor and phase C phasor nominal values. 98

Changed the voltage range on VxP, IxN relative to AGND to -0.3V to +4.0V in the
10
Absolute Maximum Ratings section.
3 12/09
Added a statement that the CRC be enabled for read and write in the Host Software
24
Design section.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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