Deep Learning Creativity in EDA

* Cheng-Kuang (CK) Lee

*NVIDIA AI Technology Center - Taiwan
* CKL@nvidia.com

ABSTRACT positions are to be inserted CPs and OPs is a difficult question.

Inserting more CPs and OPs would degrade chip performance. Fault
Computing power brings new technologies into human life. coverage may be poor in fewer CPs and OPs. The goal is to use
NVIDIA devoted to accelerating parallel computing through CPU- minimum number of CPs/OPs and maximize the fault coverage at the
GPU cooperating architecture since we invented CUDA in 2007. In same time. In this work, they proposed a high-performance graph
the last decade, one of the most important technologies, deep convolutional network to predict “Is this node a good OP?” by
learning, became feasible and realistic because GPU accelerates the embedding each node in a netlist.
optimizing process of neural network over 60x, which means that the
model training time shortens from weeks to hours. DL not only In a netlist, each node consists of four features: LL-logic level of
performed superior to human in some computer vision tasks like corresponding gate, C0-controllability0, C1-controllability1, and O-
ImageNet but also made significant progress of many fields like observability. The four feature values are measured from SCOAP.
medical, autonomous, manufacturing, finance, electronic design The ground-truth of good OP or bad OP is provided by commercial
automation (EDA) etc. DFT tools. For most of the design with high sparsity as 99.95%, they
incorporate a compressed sparse format, e.g., the coordinate (COO)
In this paper, we introduced two deep learning innovations in format to represent the netlist for reducing the netlist matrix. With
EDA field including (1) Graph Convolutional Network in Testability the advantage of COO format, the inference time can be only 1.5
Analysis and (2) DREAMPlace. In (1), graph convolutional network seconds for 106 nodes. And the GCN method can reach the same
can predict observation point candidates in a netlist more efficiently fault coverage rate as industrial tools of using fewer OPs (89%) and
compared to commercial tools. In (2), DREAMPlace significantly fewer test patterns (94%).
accelerates the VLSI placement process by using deep learning
framework of GPU for optimizing process. (2) DREAMPlace: Deep Learning Toolkit-Enabled GPU
Acceleration for Modern VLSI Placement
INTRODUCTION
Yibo Lin, et al. adapt deep learning framework to accelerate an
Due to the physical limitation, Moore’s law is slowing down important Modern VSLI problem – Placement. Placement is a
recent years. Single-threaded performance incremental is only about complex work to properly place every cell position to make the
1.1x per year since 2010. NVIDIA invented CUDA in 2007 to utilize routing wires possible and feasible. Placement plays a critical role in
CPU-GPU cooperating architecture of parallel computing. GPU the design flow. The process generally contains three stages: global
computing performance incremental keeps 1.5x per year and shows placement (GP), legalization, and detailed placement (DP). Currently,
no trend degrading. Deep learning generally consists of three major the state-of-the-art are nonlinear optimization methods like
components – data, algorithm, and compute. Huge amount of data is ePlace/RePLAce families or NTUplace. The optimization goals are
iteratively fed into designed algorithms for optimizing the model trying to minimize the wire length of the netlist and reduce the
performance in specific task. Leveraging on GPU computing power, density of cells. However, the challenges to ePlace family contain
deep learning demonstrated many amazing progresses, like AlexNet low efficiency. For example, it takes RePlace more than three hours
in ImageNet Challenge in 2012, generative adversarial network to finish a ten million-cell design.
(GAN) in 2014, AlphaGo in 2015, BERT in 2018, etc. All the
DREAMPlace leveraged the deep learning toolkits to develop this
progress inspired many new applications and chances across various
placement engine. They use GPU as the hardware and PyTorch as
fields, e.g. computer vision, medical imaging, autonomous,
the software framework. And develop some CUDA codes for the
manufacturing, finance and so on.
wire length or density calculation to enable the acceleration. At the
In the field of EDA, deep learning also brings new methodologies same time, the quality of the results is still matching the state-of-the-
like RouteNet for predicting routability, Conditional GAN for art ePlace of RePlace. The evaluation on ISPD 2005 benchmarks
generating OPC mask. Most of the methodologies are based on achieved 34x speedup over multi-thread CPU implementation. Large
convolutional neural network architecture, which means that it industrial designs (ranging from 1M-10M cells) achieved over 40x
basically uses image-based data. However, there are many non- speedup. Eventually, a 10M-cell design can be finished within 5min
image-based data representations in EDA field. Fundamental objects compared with the 3h on multi-thread CPU.
such as cells and nets (or netlists) are common data types in EDA. In
this paper, we briefly review two deep learning innovations in 2019 REFERENCES
related to netlists data rather than image-based data in EDA field.
[1] Y. Ma, H. Ren, B. Khailany, H. Sikka, L. Luo, K. Natarajan,
(1) High Performance Graph Convolutional Networks with and B. Yu, “High Performance Graph Convolutional
Applications in Testability Analysis Networks with Applications in Testability Analysis,” in Proc.
DAC, 2019, pp. 18:1-18:6.
Yuzhe Ma, et al. propose a graph convolutional based method to [2] Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan,
tackle graph-type data onto EDA problems. As we know, test point “DREAMPlace: Deep Learning Toolkit-Enabled GPU
insertion (TPI) is widely used methodology in design-for-testability Acceleration for Modern VSLI Placement,” in Proc. DAC,
(DFT) tasks. In TPI, we need to insert control points (CPs) and 2019, pp. 117:1-117:6.
observation points (OPs) into the circuit. However, where the proper

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