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 GATE QUESTION BANK Contents

Contents

Subject Name Page No.

#1. Engineering Mathematics 1 – 163

#2. Network Theory 164 – 248

#3. Signals and Systems 249 - 311

#4. Control Systems 312 – 390

#5. Analog Circuits 391 – 482

#6. Digital Circuits 483 – 545

#7. Communications 546 – 583

#8. Electronic Devices and Circuits 584 – 614

#9. Electromagnetic Theory 615 – 660

#10. General Aptitude 661 – 729

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 6 Digital Circuits

Contents
Topics Page No.

#1. Number Systems & Code Conversions 483 – 484

#2. Boolean Algebra & Karnaugh Maps 485 – 491

#3. Logic Gates 492 – 499

#4. Logic Gate Families 500 – 503

#5. Combinational and Sequential Digital Circuits 504 – 528

#6. AD/DA Convertor 529 – 534

#7. Semiconductor Memory 535 – 536

#8. Introduction to Microprocessors 537 – 545

 Syllabus

Syllabus for Digital Circuits

Number Systems, Combinatorial Circuits, Boolean Algebra, Minimization of Functions using Boolean
Identities and Karnaugh Map, Logic Gates and their Static CMOS Implementations, Arithmetic
Circuits, Code Converters, Multiplexers, Decoders and PLAs, Sequential Circuits Latches and
Flip‐Flops, Counters, Shift‐Registers and Finite State Machines, Data Converters, Sample and Hold
Circuits, ADCs and DACs, Semiconductor Memories, ROM, SRAM, DRAM, 8-bit Microprocessor
(8085), Architecture, Programming, Memory and I/O Interfacing.

Analysis of GATE Papers

Year ECE EE IN

2016 8.30 4.00 12.00

2015 9.00 6.00 9.00

2014 8.75 6.00 11.00

2013 6.00 5.00 5.00

2012 6.00 5.00 5.00

2011 9.00 5.00 10.00

2010 9.00 8.00 8.00

2009 13.00 4.00 12.00

2008 10.67 6.00 18.00

2007 10.67 3.00 23.00

Overall Percentage 9.04% 5.2% 11.3%

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 GATE QUESTION BANK Digital Circuits

Number Systems & Code Conversions

ECE-2007 IN-2008
1. X = 01110 and Y = 11001 are two 5-bit 7. The result of (45)10 – (45)16 expressed in
binary numbers represented in two’s 6-bit 2’s complement representation is,
complement format. The sum of X and Y (A) 011000 (C) 101000
represented in two’s complement format (B) 100111 (D) 101001
using 6 bits is,
(A) 100111 (C) 000111 IN-2009
(B) 001000 (D) 101001 8. The binary representation of the decimal
number 1.375 is,
ECE-2008 (A) 1.111 (C) 1.011
2. The two numbers represented in signed (B) 1.010 (D) 1.001
2’s complement form are P = 11101101
and Q = 11100110. If Q is subtracted IN-2011
from P, the value obtained in signed 2’s 9. The base of the number system for the
complement form is addition operation 24 + 14 = 41 to be
(A) 100000111 (C) 11111001 true is
(B) 00000111 (D) 111111001 (A) 8 (C) 6
(B) 7 (D) 5
ECE-2014
3. The number of bytes required to
represent the decimal number 1856357
in packed BCD (Binary Coded Decimal)
form is __________

EE-2007
4. The octal equivalent of the HEX number
AB.CD is
(A) 253.314 (C) 526.314
(B) 253.632 (D) 526.632

EE-2014
5. A cascade of three identical modulo-5
counters has an overall modulus of
(A) 5 (C) 125
(B) 25 (D) 625

6. Which of the following is an invalid state

in an 8-4-2-1 Binary Coded Decimal
counter
(A) 1 0 0 0 (C) 0 0 1 1
(B) 1 0 0 1 (D) 1 1 0 0

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 GATE QUESTION BANK Digital Circuits

Answer Keys & Explanations

ECE 6. [Ans. D]
1. [Ans. C] BCD counter counts up to 1001
= 01110
y = 11001 IN
y( ) = 100111 7. [Ans. C]
Carry discard it ( ) ( ) = ( 2 ) = (101000)
00111 in 6 bits will be 000111
8. [Ans. C]
2. [Ans. B] 0.375 × 2 = 0.750
i ned 2 s complement of 0.750 × 2 = 1.5
P = 11101101 1.5 × 2 = 1.0
o P = 00010011 Hence answer is 1.011
i ned 2 scomplement of
= 11100110 9. [Ans. B]
P = P (2 s complement of ) Let the base is x, Here
= 00010011 (2 ) (1 ) = ( 1)
11100110 ( 2 ) ( 1 )
11111001 =( 1 )
2 s complement of (P ) = 00000111 4 + 2x + 4 + x = 4x + 1
x=7
3. [Ans. *] Range: 3.9 to 4.1
A decimal digit is represented by 4 bit in
BCD format, so for a decimal number with
digits requires 4d bit and
1 byte = 8 bit so
Here d = 7
No. of bits = 28
2
byte = = =

EE
4. [Ans. B]
Hex number (AB.CD)

⏞
1010 ⏞1011 ⏞ 1100 ⏞1101
For finding its octal number, we add one
zero in both extreme and group 3 bit
together
010
⏟ 101
⏟ 011⏟ 110 ⏟ 011
⏟ 010⏟

ui alent octal number 2 2

5. [Ans. C]
Overall modulus = = 12

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 GATE QUESTION BANK Digital Circuits

Boolean Algebra & Karnaugh Maps

ECE-2007 ECE-2014
1. The Boolean expression 5. The Boolean expression ( )( ̅)
̅̅ ̅ ̅ ̅ ̅̅ ̅ ̅ can ̅̅̅̅̅̅̅̅̅̅̅
( ̅) ̅ simplifies to
be minimized to (A) X (C) XY
(A) ̅̅ ̅ ̅ ̅ ̅ (B) Y (D) X+Y
(B) ̅̅ ̅ ̅ ̅̅
(C) ̅ 6. Consider the Boolean function, F(w, x, y,
(D) z) = wy + xy + ̅ xyz + ̅ ̅ y + xz + ̅ ̅ ̅.
Which one of the following is the
ECE-2009 complete set of essential prime
2. If X = 1 in the logic equation implicates?
[X+Z{ ( +X ) }] { + ( X + Y)} (A) ̅̅ (C) ̅ ̅̅
=1 then (B) (D) ̅̅
(A) Y = Z (C) Z = 1
(D) Z = 0 7. For an n-variable Boolean function, the
(B) Y =
maximum number of prime implicants is
(A) ( ) (C)
EC/EE/IN -2012
3. In the sum of products function
(B) (D) ( )
( ) ∑( ), the prime implicants
are ECE - 2015
8. The Boolean expression ( )
(A) ̅ ̅
̅ ̅ ̅̅ ̅ ̅ ̅̅ ̅ converted into
(B)
canonical product of sum (POS) form is
(C) ̅ ̅ ̅ ̅
(A) ( )( ̅ )( ̅ ̅)
(D) ̅ ̅ ̅ ̅̅ ̅
(̅ ̅)
(B) ( ̅ )(̅ ̅ )(̅ ̅ )
ECE-2013
( ̅ ̅ ̅ )
4. In the circuit shown below, Q1 has
negligible collector – to – emitter (C) ( )(̅ ̅ )( ̅ )
( ̅ ̅ ̅ )
saturation voltage and the diode drops
(D) ( ̅ ̅ )(̅ )(̅ ̅ )
negligible voltage across it under forward
bias. If Vcc is +5 V, X and Y are digital ( )
signals with 0 V as logic 0 and as logic
1, then the Boolean expression for Z is 9. A 3-input majority gate is defined by the
logic function ( ) .
Which one of the following gate is
R1
Z represented by the function
R2 (̅̅̅̅̅̅̅̅̅̅̅̅
( ), ( ̅ )?
X Q1
Diode
(A) 3-input NAND gate
(B) 3-input XOR gate
(C) 3-input NOR gate
Y (D) 3-input XNOR gate
(A) XY (C) X
(B) (D)

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 GATE QUESTION BANK Digital Circuits

10. In the figure shown, the output Y is 13. A minimized form of the function is
required to be ̅ ̅ . The gates (A) (C)
G1 and G2 must be, respectively. (B) (D)

14. Which of the following circuits is a

realization of the above function ?
(A)
X
(A) NOR, OR (C) NAND, OR
F
(B) OR, NAND (D) AND, NAND (A) Y
Z
X
11. A function of Boolean variables X,Y and Z (B) F
is expressed in terms of the min terms as X Y
F(X, Y, Z) = ∑(1, 2, 5, 6, 7). Which one of Z
F
the product of sums given below is equal (B) Y
to the function F(X, Y, Z)? X
Z
(A) (̅ ̅ ̅ ) (̅ ) ( ̅ ̅) (C) F
(B) ( ) ( ̅ ̅ ) ( ̅ ) Y
(C) ( ̅ ̅ ) ( ̅ ̅ ) ( ̅ ) X Z

( ̅) ( ) (C) F
(D) ( ̅ ) (̅ ) (̅ Y
Z
̅ ) (̅ ̅ ) (̅ ̅ ̅ ) X
(D) F
Y
ECE - 2016 X Z
12. Following is the K-map of a Boolean
(D) F
function of five variables P, Q, R, S and X.
Y
The minimum sum-of-product (SOP) X Z
expression for the function is F
EE-2014Y
Z
15. Which of the following logic circuits is a
realization of the function F whose
Karnaugh map is shown in figure

EE-2010
Statement for Linked Answer Q.No. 13 & 14 ( )
The following Karnaugh map represent a
function .
F
YZ
X 00 01 11 10

0 1 1 1 0
F
YZ
1 000 001 1 11 0
X
10 0
0 1 1 1
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1 0 0 1
 GATE QUESTION BANK Digital Circuits

( ) (A) ( ̅ )(̅ )(̅ ̅ )

(B) ( ̅ ̅ )( )(̅ ̅ ̅)
(C) (̅ )( ̅ ̅ )( )
(D) (̅ ̅ )( ̅ )( )

EE - 2016
( )
19. The output expression for the
Karnaugh map shown below is

( ) ̅
(A) (C) ̅ ̅
(B) ̅ (D) ̅

20. The Boolean expression

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( ̅ ̅) ( ̅) simplifies to
(A) 1 (C)
16. The SOP (sum of products) form of a (B) ̅̅̅̅ (D) 0
Boolean function is (0, 1, 3, 7, 11), where
inputs are A, B, C, D (A is MSB, and D is IN-2007
LSB). The equivalent minimized 21. A logic circuit implements the Boolean
expression of the function is function F = ̅ . Y + X .̅ . ̅ . It is found that
(A) (̅ )(̅ )(̅ ̅)( ̅ ) the input combination X = Y = 1 can
(B) (̅ )(̅ )(̅ ̅ )( ̅ ) never occur. Taking this into account, a
(C) (̅ )(̅ )(̅ ̅ )( ̅ ̅ ) simplified expression for F, is given by
(D) (̅ )( ̅)(̅ ̅)( ̅ ) (A) ̅ + ̅. ̅ (C) X + Y
(B) X + Z (D) Y + X. ̅
EE - 2015
17. ( ) Π ( 7 9 22. Let X and Y = be unsigned
12, 13, 14, 15) is a maxterm 2-bit numbers. The function F = 1 if X > Y
representation of Boolean function f(A, B, and F = 0 otherwise. The minimized sum
C, D) where A is the MSB and D is the LSB. of products expression for F is
The equivalent minimized representation (A) + ̅ .̅ .̅
of this function is (B) ̅ + ̅ + ̅
(A) ( ̅ )( ̅ ) (C) ̅ + ̅ ̅ + ̅
(B) ̅ ̅ ̅ + ̅ .̅ + ̅
(D)
(C) ̅ ̅ ̅ ̅ ̅̅ ̅
(D) ( ̅ )( ̅ ̅ )( ̅ ) IN-2008
23. The minimum sum of products form of
18. Consider the following Sum of Products the Boolean expression
expression, F. Y = ̅̅ ̅̅ ̅̅̅ ̅̅ ̅
̅̅ ̅ ̅ ̅̅ ̅ ̅ ̅ ̅̅ ̅
The equivalent Product of Sums (A) Y = P ̅ + ̅ ̅ (C) Y = P ̅ ̅ ̅ ̅
expression is (B) Y = P ̅ ̅ ̅ (D) Y = ̅ ̅ ̅

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 GATE QUESTION BANK Digital Circuits

IN-2009 IN-2011
24. The minimal sum-of-products expression 25. For the Boolean expression
for the logic function f represented by the ̅ ̅̅ ̅ ̅ ̅̅ ̅, the
given Karnaugh map is minimized Product of Sum (PoS)
PQ expression is
RS (A) ( ̅) ( ̅)
00 01 11 10
(B) ( ̅ ) (̅ )
00 0 1 0 0
0 1 1 1 (C) ( ̅ )( ̅)
01
1 1 1 0 (D) ̅
11
10 0 0 1 0
IN - 2016
(A) QS + 26. The Boolean expression (
(B) + ) is equivalent to
(C) + (A) (C) ( )( )
(D) (B) (D) ( )( )

Answer Keys & Explanations

ECE 3. [Ans. A]
1. [Ans. D] ( ) ∑( )
K-map corresponding to given Boolean
expression ̅̅ ̅ YZ ̅
̅ 1
CD
00 01 11 10
1
AB
1 1
00 1
( ) ̅ ̅
01 1
So prime implicants are ̅ and ̅ .
11 1

10 1 4. [Ans. B]
X Y Z Comments
̅̅ ̅ ̅ ̅̅ 0 0 0 Transistor off diode ON
OR 0 1 1 Transistor off diode rev biases
̅̅ ̅ ̅ ̅ ̅̅ ̅̅ 1 0 0 Transistor ON diode rev biases
1 1 0 Transistor ON diode rev biased
[ ] ̅̅ So, ̅Y=Z

5. [Ans. A]
( )( ̅) ̅̅̅̅̅̅̅̅̅̅̅
( ̅) ̅
2. [Ans. D]
( ̅ ̅) ̅̅̅̅ ̅
[ ( ( ̅))] [ ( )]
̅̅̅̅
̅
By putting X = 1
[ ( ( ))] [ ̅( )]
[ ]

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 GATE QUESTION BANK Digital Circuits

6. [Ans. D] 10. [Ans. A]

yz Given expression is ̅̅
wx ̅̅ The first term can be obtained by considering
1 1
as NOR gate, and second term is ( ̅ ̅ )
1 1 xz obtained from another lower NOR-Gate. So,
final expression can be implemented by
1 1 1 1
y considering as OR-Gate.
1 1 1 1
11. [Ans. B]
So, P.I. are ̅̅ Given minterm is:
( ) ( 7)
7. [Ans. D] o : ( ) Π ( )
Maximum P.I will occurs at condition like ( )( ̅ ̅ )(̅ )

12. [Ans. B]
1 1 PQ PQ
RS 00 01 11 10 RS 00 01 11 10
1 1 00 00 1 1
01 1 1 01
1 1
11 1 1 11
1 1 01 01 1 1
i.e., no grouping at all so
So, ( ) o ( ) ( )

8. [Ans. A] EE
( ) ̅ ̅ ̅̅̅ ̅ 13. [Ans. B]
∑ ( 7) Π ( ) YZ
( )( ̅ )( ̅ ̅ )(̅ ̅) X 00 01 11 10
0 1 1 1 0
9. [Ans. B] 1 0 0 1 0
Three input majority gate F = ̅ ̅ + YZ
M(a,b,c)
(̅̅̅̅̅̅̅̅̅̅̅̅
( ) ( ̅) 14. [Ans. D]
( ) ( ) From the figure it is clear that, two NAND
( ) ( ) gates generate the ̅ ̅ and now two
( )( )( )( AND gates with inputs ̅ ̅ and inputs
) ( )( )( ) Y and Z is used to generate two terms of
( ) SOP form and now OR gate is used to sum
( )( )( ) them and generate the F.
( )( )
15. [Ans. C]
( 7) ̅̅
̅̅ [by consensus theorem]
Odd number in the minterms = XOR
gate

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 GATE QUESTION BANK Digital Circuits

16. [Ans. A] K – map

̅ ̅ ̅ ̅ YZ
(̅ )(̅ ̅)( ̅)( ̅) X 00 01 11 10
0 0 0 1 1
1 1 0 x x

X
F=Y+X
9
22. [Ans. D]
17. [Ans. A] F = 1 if X > Y, so following will be K – map
of function F.
18. [Ans. A]
Given minterm is 00 01 11 10
00 0 0 0 0
∑ ( 7)
Π ( ) 01 1 0 0 0
o o o o
11 1 1 0 1
( ̅ )(̅ )(̅ ̅ )
10 1 0
1 1
19. [Ans. B] ̅ + ̅ ̅̅̅ + ̅̅̅
F=

23. [Ans. A]

̅
By K – map

20. [Ans. D] PQ RS
00 01 11 10
(̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ ̅) ( ̅) 00 1 0 0 1

(̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ ̅ ) ̅̅̅̅̅̅̅̅̅
( ̅) 01 0 0 0 0

̅ ̅ ̅ 11 0 0 0 0
10 1 1 1 1
IN
21. [Ans. D]
̅ ̅̅ 24. [Ans. A]
Truth table: PQ
RS 00 01 11 10
Q
X Y Z F S 00 0 1 0 0
0 0 0 0
01 0 1 1 1
0 0 1 0
0 1 0 1 11 1 1 1 0
0 1 1 1
10 0 0 1 0
1 0 0 1
1 0 1 0
1 1 0 x
1 1 1 x

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 GATE QUESTION BANK Digital Circuits

25. [Ans. A]
̅ ̅̅ ̅ ̅ ̅̅ ̅
̅ ̅( ̅ ) ̅̅ ( ̅)
̅̅ ̅ ̅
̅̅ [ ̅ ̅]
̅̅ [( ̅ )( ̅)]
̅̅ ( ̅)
̅̅ ̅
̅( ̅)
̅
(̅ )(̅ )
( ̅)( ̅)
Alternative method:

00 01 11 10
0 1 0 0 1

0 1 0 1 1

( ̅)( ̅)

26. [Ans. C]
(̅ ̅) ̅̅̅̅
( ̅̅̅̅)( )

( )( )

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 GATE QUESTION BANK Digital Circuits

Logic Gates

ECE-2007 5. Match the logic gates in Column A with

1. The Boolean function Y =AB + CD is to be their equivalents in Column B.
realized using only 2 – input NAND gates. Column A Column B
The minimum number of gates required P 1
is
(A) 2 (C) 4 Q 2
(B) 3 (D) 5
R 3
ECE-2008
2. The logic function implemented by the S 4
following circuit at the terminal OUT is
(A) P-2, Q-4, R-1, S-3 (C) P-2, Q-4, R-3, S-1
(B) P-4, Q-2, R-1, S-3 (D) P-4, Q-2, R-3, S-1
OUT
P Q ECE-2011
6. The output Y in the circuit below is
always “1” when
(A) P NOR Q (C) P OR Q P
(B) P NAND Q (D) P AND Q
Q
Y
3. Which of the following Boolean
R
Expressions correctly represents the
relation between P, Q, R and ? (A) Two or more of the inputs P, Q, R are
“0”
P X
Z (B) Two or more of the inputs P, Q, R are
Q
“1”
Y (C) Any odd number of the inputs P, Q, R
R is “0”
(A) = (P OR Q)XOR R (D) Any odd number of the inputs P, Q, R
(B) = (P AND Q) XOR R is “1”
(C) = (P NOR Q) XOR R
(D) = (P XOR Q) XOR R ECE-2012
7. In the circuit shown
ECE-2010 5 Volts
4. For the output F to be 1 in the logic circuit
A
shown, the input combination should be
A C
B
B
Y
F
C
C

(A) A=1, B=1, C=0 (C) A=0, B=1, C=0 A B

(B) A=1, B=0, C=0 (D) A=0, B=0, C=1

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 GATE QUESTION BANK Digital Circuits

(A) ̅̅ ̅ (C) (̅ ̅) ̅ ECE - 2015

(B) ( ) (D) 11. All the logic gates shown in the figure
have a propagation delay of 20 ns. Let
ECE-2013 0 and B = 1 until time t = 0. At
8. There are four chips each of 1024 bytes 0, all the inputs flip (i.e. A = C = 1 and
connected to a 16 bit address bus as B = 0) and remain in that state. For t > 0,
shown in the figure below. RAMs 1, 2, 3 output Z = 1 for a duration (in ns) of
and 4 respectively are mapped to A
addresses B Z
C
10
E

10
8 bit data bus 12. In the circuit shown diodes , and
E are ideal, and the inputs an are
A0 A9
10 ‘0 ’ for logic ‘0’ an ‘’10 ’’ for logic ‘1’.
E
A10
1
What logic gate does the circuit
A11
A12
11
10 represent?
A13
A14 10
input 01 E
S1 S0 00
A15

(A) 0C00H 0FFFH, 1C00H 1FFFH,

2C00H 2FFFH, 3C00H 3FFFH
(B) 1800H 1FFFH, 2800H 2FFFH,
3800H 3FFFH, 4800H 4FFFH 1
(C) 0500H 08FFH, 1500H 18FFH, 10
3500H 38FFH, 5500H 58FFH
(D) 0800H 0BFFH, 1800H 1BFFH, (A) 3 input OR gate
2800H 2BFFH, 3800H 3BFFH (B) 3 input NOR gate
(C) 3 input AND gate
ECE-2014 (D) 3 input XOR gate
9. The output F in the digital logic circuit
shown in the figure is 13. A universal logic gate can implement any
Boolean function by connecting sufficient
number of them appropriately. Three
gates are shown.
1

(A) ̅y y̅ (C) ̅y̅ y 1

(B) ̅y̅ y̅̅ (D) ̅y̅̅ y
Which one of the following statements is
10. In the circuit shown in the figure, if 0, TRUE?
the expression for is (A) Gate 1 is a universal gate.
(B) Gate 2 is a universal gate.
(C) Gate 3 is a universal gate.
(D) None of the gates shown is a
universal gate.

(A) ̅ ̅ (C) ̅ ̅
(B) (D)

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 GATE QUESTION BANK Digital Circuits

ECE - 2016 (A) S is always either zero or odd

14. The logic functionality realized by the (B) S is always either zero or even
circuit shown below is (C) S = 1 only if the sum of A, B, C and D
̅ is even
(D) S = 1 only if the sum of A, B, C and D
is odd

EE-2009
18. The complete set of only those Logic
Gates designated as Universal Gates is
(A) OR (C) NAND (A) NOT, OR and AND Gates
(B) XOR (D) AND (B) XNOR, NOR and NAND Gate
(C) NOR and NAND Gates
15. The minimum number of 2-input NAND (D) XOR, NOR and NAND Gates
gates required to implement a 2-input
XOR gate is EE-2011
(A) 4 (C) 6 19. The output Y of the logic circuit given
(B) 5 (D) 7 below is
16. For the circuit shown in the figure, the
delays of NOR gates, multiplexers and
inverters are ns, 1. ns and 1 ns, (A) 1 (C) X
respectively. If all the inputs P, Q, R, S and (B) 0 (D) ̅
T are applied at the same time instant, the
maximum propagation delay (in ns) of IN-2007
the circuit is __________ 20. Two square waves of equal period T, but
wi h a ime elay τ are applie o a igi al
circuit whose truth table is shown in the
0 0 following figure.
X Y Output
0 0 1
1 1 0 1 0
1 0 0
1 1 1
X
EE-2007
17. A, B, C and D are input bits, and Y is the 1
output bit in the XOR gate circuit of the
figure below. Which of the following
t
statements about the sum S of A, B, C, D T/2 T
and Y is correct? Y
A
XOR
B
1
XOR Y
τ τ / t
C
XOR
D

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 GATE QUESTION BANK Digital Circuits

The high and the low levels of the output IN-2010

of the digital circuit are 5 V and 0 V, 22. The logic gate circuit shown in the figure
respectively. Which one of the following realizes the function
figures shows the correct variation of the A

average value of the output voltage as X

function of τ for 0 ( )?
(A) Z
Vav

5V Y

(A) XOR (C) Half adder

τ (B) XNOR (D) Full adder
T/2
(B) EC/EE/IN-2013
Vav
23. A bulb in a staircase has two switches,
5V one switch being at the ground floor and
the other one at the first floor. The bulb
Vav can be turned ON and also can be turned
τ
T/2 OFF by any one of the switch irrespective
(C)
Vav Vav of the state of the other switch. The logic
of switching of the bulb resembles
5V (A) An AND gate (C) A XOR gate
(B) An OR gate (D) A NAND gate
τ
T/2 IN - 2015
(D) 24. Consider the logic circuit with input
Vav
signal TEST shown in the figure. All gates
in the figure shown have identical non-
2.5V zero delay. The signal TEST which was at
τ logic LOW is switched to logic HIGH and
T/2 maintained at logic HIGH. The output
TEST Output
IN-2009
21. The diodes in the circuit shown are ideal.
(A) Stays HIGH throughout
A voltage of 0V represents logic 0 and
(B) Stays LOW throughout
+5V represents logic1.The function Z
(C) Pulses from LOW to HIGH to LOW
realized by the circuit for inputs X and Y
(D) Pulses from HIGH to LOW to HIGH
is
+ 5V
25. The logic evaluated by the circuit at the
output is
X
Output

X Z

Y
Y
(A) Z=X + Y (C) Z =̅̅̅̅̅̅̅̅ (A) ̅ ̅ (C) ̅̅̅̅
(B) Z=XY (D) Z=̅̅̅̅ (B) (̅̅̅̅̅̅̅ ) (D) ̅ ̅

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 GATE QUESTION BANK Digital Circuits

26. In the circuit shown, the switch is

momentarily closed and then opened.
Assuming the logic gates to have equal
non-zero delay, at steady state, the logic
states of X and Y are

1
(A) X is latched, Y toggles continuously
(B) X and Y are both latched
(C) Y is latched, X toggles continuously
(D) X and Y both toggle continuously

IN - 2016
27. In the digital circuit given below, F is

(A) (C)
(B) ̅ (D)

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 GATE QUESTION BANK Digital Circuits

Answer Keys & Explanations

ECE 7. [Ans. A]
1. [Ans. B] In NMOS circuit
A Since are in parallel so those
B
represent ( ) is in sense, so it
AB + CD
represen s ‘ o ’ opera ion an he whole
C
D function should be inverted or it is
complementary logic.
2. [Ans. D] So,
When P = Q = 1, then OUT = 1 ̅̅̅̅̅̅̅̅̅̅̅̅
( ) ̅̅̅̅̅̅̅ ̅ ̅ ̅ ̅
P = Q = 0, then OUT = 0
P = 0, Q = 1, then OUT = 0 8. [Ans. D]
P = 1, Q = 0, then OUT = 0 For RAM #1
So, it is AND gate
⏟0 0 0 0 ⏟1 0 0 0 ⏟ ⏟
0 0 ower a
0 0 0
3. [Ans. D] ⏟
0000 ⏟ 1 0 1 1 ⏟ 1⏟1 ighes a
X= ;Y=P+Q 0
Z = XY = . (P + Q) So range of add for RAM #1 0 00
=( )( ) 0
Which is present only in option D
⊕
∴ ⊕ ⊕
9. [Ans. A]
4. [Ans. D] ( ⊕ )(( ⊕ ) )
For 3 input XNOR for output to be one, ( ⊕ )(( ⊕ ) ( )̅)
two input must be one, and we know that ( ⊕ )
2- input XOR & XNOR gate are (̅ ̅)
complementary & hence only 1(1’s) will ̅ ̅
be generated & C=1 is required
i.e, When A = 0, B = 0 and C = 1, 10. [Ans. A]
then F = 1 C 0 1
A ̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅
B
5. [Ans. D] 0
P = ̅̅̅̅̅̅̅ = ̅ ̅ = 4 A ̅̅̅̅̅̅̅̅
B AB
Q = ̅̅̅̅ = ̅ + ̅ = 2
y ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅ ( ) ̅̅̅̅
R = A ⊕ B = A̅ + ̅ B = 3
( ) (̅ ̅)
S = A B = AB + ̅ ̅ = 1
̅ ̅

6. [Ans. B]
The output Y expression in the ckt 11. [Ans. *] Range: 40 to 40
(Majority circuit) All the logic gates have same propagation
o ha wo or more inpu s are ‘1’ is delay = 20 ns
A
always ‘1’.
B Z
1 0 0 1
C
0 1
Hence the correct answer is 40

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 GATE QUESTION BANK Digital Circuits

12. [Ans. C] EE
Case I: If any input is logic 0 (i.e., 0 V) then 17. [Ans. B]
correspon ing io e is “ ” an ue o ⊕ ⊕ ⊕ from the given
ideal diode output voltage 0 as well diagram. We know that sum of any
as if there is any input logic 1 (i.e., 10 V) number of bits is XOR of all bits.
corresponding diode will be OFF. o ⊕ ⊕ ⊕ ⊕
Case II: If all the inputs are high (i.e., 10 V) S=Y⊕Y
then all the diodes are R.B (OFF) and S = either zero or even because LSB is
output voltage 10 zero (always).
So, it is a positive logic 3-inputs AND gate.
18. [Ans. C]
13. [Ans. D] NOR and NAND are designated as
Only NAND and NOR are universal gate, universal logic gates, because using any
but in the question other gates are
one of them we can implement all the
mentioned.
logic gates.
14. [Ans. D]
19. [Ans. A]
.̅ ̅. ̅ ̅ 1
̅ X Y
1 0 1
0 1 1
When 1 is ON and is OFF
ou pu IN
When 0 is OFF and is ON 20. [Ans. C]
ou pu 0 When τ = 0 X and Y will be same and
∴ So the given circuit implement Y = AB out-put will be equal to dc of 5V.
ga e When τ = , X and Y will be complement
15. [Ans. A] of each other and output will be equal to
NAND Gate for EX-OR Gate dc 0.
When τ increases from 0 o , O/P will
⊕ decrease from 5V to 0V linearly.

̅ ̅ 21. [Ans. B]
When any of X or Y is zero, Z = 0. For
Number of NAND Gate = 4 X = Y = 1, Z = 1
16. [Ans. *] Range: 6.0 to 6.0
Case (i) When T = 0 22. [Ans. A]
elay of elay of 1 X y
elay of
1. 1. ns x Z
Case (ii) When T = 1 Y y
y
elay of 1s ga e
elay of 1 elay of Z= y. y = y y =x⊕y
ga e elay of
1 1. 1. ns
So, the maximum delay = 6 ns.
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 GATE QUESTION BANK Digital Circuits

23. [Ans. C] 25. [Ans. A]

When both switches in on position, bulb u pu of upper ga e is ̅
is off u pu of lower ga e is ̅
When both switches in off position, bulb u pu of ga e is ̅ ̅ .
is off
Bulb 26. [Ans. D]
0 0 0 The above circuit is a stable multi
0 1 1 vibrator circuit, where odd numbers of
1 0 1 inverter are there in the loop. In such a
1 1 0 circuit, irrespective of the position of
It is a XOR gate output, it always toggles.
Latching means X and Y will be fixed to
24. [Ans. D] same value; in this case it is not possible.
For analysis point of view, assume delay
of each age is 10 msec. However we can 27. [Ans. B]
take any value. ̅̅̅̅
.y

̅. )
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
 By referring the circuit the upper input y

̅̅̅̅
y̅

. y (y
to the NAND gate is direct test signal.

(̅̅̅̅).
The lower input to NAND gate is TEST ̅̅̅̅
y̅.
but with a delay of 30 nsec.
 Assuming the delay of NAND gate is 0. f (̅̅̅̅̅
. y. ). (y̅. ) (̿̿̿̿)
.y ̿̿̿
(y
̅ )
First draw output waveform (ideal y emorgan’s law
case) then shift that by 10 msec. i.e. f y y̅
introduce the delay.

es
0
es
wi h elay
( )
0 n sec 0

Output with
delay = 0
0 0 n sec
Output with
NAND gate
delay = 10 n sec
0 10 n sec 40 n sec
So we can clearly say that initial output
change from high to low, then it changes
from low to high and then finally at
steady state output is 1.
Note: Saying output is high (option A)
will be wrong here. We are not
interested to find steady state
output.

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 GATE QUESTION BANK Digital Circuits

Logic Gate Families

ECE - 2007
1. The circuit diagram of a standard TTL
NOT gate is shown in the figure. When
Vi = 2.5V, the modes of operation of the
transistors will be
(A) 4 V, 3 V, 2 V (C) 4 V, 4 V, 4 V
(B) 5 V, 5 V, 5 V (D) 5 V, 4 V, 3 V
1 4kΩ 100kΩ
R
2
4kΩ
Q4
4. The output (Y) of the circuit shown in the
D figure is
Q2
Q1
Q3
1kΩ
- ̅

(A) Q1: reverse active; Q2: normal active;

Q3: saturation; Q4: cut-off
(B) Q1: reverse active; Q2: saturation;
Q3: saturation; Q4: cut-off
(C) Q1: normal active; Q2: cut-off;
Q3: cut-off; Q4: saturation ̅
(D) Q1: saturation; Q2: saturation;
Q3: saturation; Q4: normal active
(A) ̅ ̅ (C) ̅ ̅
ECE - 2009 (B) ̅ ̅ ̅ (D) ̅
2. The full forms of the abbreviations TTL
and CMOS in reference of logic families EE - 2010
are 5. The TTL circuit shown in the figure is fed
(A) Triple Transistor Logic and Chip with the waveform X (also shown). All
Metal Oxide Semiconductor gates have equal propagation delay of
(B) Tristate Transistor Logic and Chip 10ns. The output Y of the circuit is
Metal Oxide Semiconductor x

(C) Transistor Transistor Logic and 100 ns

Complementary Metal Oxide
Semiconductor
(D) Tristate Transistor Logic and 1
Complementary Metal Oxide Silicon
0 t
ECE - 2014
X
3. In the following circuit employing pass Y
transistor logic, all NMOS transistors are
identical with a threshold voltage of 1V.
Ignoring the body-effect, the output
voltages at P, Q and R are,
499+

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 GATE QUESTION BANK Digital Circuits

(A) Y IN - 2014
7. The figure is a logic circuit with inputs A
and B and output Y. = + 5 V. The
circuit is of type
1

0
t
(B) Y

0
t
(C) Y

1 (A) NOR (C) OR

(B) AND (D) NAND
0
t
(D) Y 8. The com ara ors o ‘1’, when
in ≥ 0 and o ‘0’, when in
0), exclusive-OR gate and the unity gain
low-pass filter given in the circuit are
1
ideal. The logic output voltages of the
0 t
exclusive-OR gate are 0 V and 5 V. The
cutoff frequency of the low-pass filter is
IN - 2007 0.1 Hz. For 1 sin 000 and
6. A CMOS implementation of a logic gate is 1 sin 000 , the value of in volt
shown in the following figure: is ________
5v

Low-pass
X
filter
Y PMOS

NMOS

The Boolean logic function realized by the

circuit is.
(A) AND (C) NOR
(B) NAND (D) OR

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 GATE QUESTION BANK Digital Circuits

Answer Keys and Explanations

ECE EE
1. [Ans. B] 5. [Ans. A]
Reverse active, X
Y
Saturation
Saturation,
Cut off A B

2. [Ans. C] 1
TTL - Transistor Transistor Logic X
CMOS - Complementary Metal Oxide 0

Semiconductor A

3. [Ans. C] B
Suppose all NMOS at saturation
≥
For m Y=X B

≥ 1 &
IN
4 i 6. [Ans. C]
For m NOR Gate
( 1)
7. [Ans. D]
(4 )
Given circuit is of the standard 2 input
ow since
NAND gate.
4 (4 )
4 8. [Ans. *] Range: 1 to 1
or m
1

Low-pass
(4 ) 4 filter
4

4. [Ans. A]
The given circuit is CMOS implementation
If the NMOS is connected in series, then
the output expression is product of each
input with complement to the final
product.
o, ̅̅̅̅̅̅̅̅̅
̅ ̅

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 GATE QUESTION BANK Digital Circuits

a e orm

1
11

1
4
1
11

Output of low pass filter is the average

value of output of XOR GATE
1
[∫ d ∫ d]

1
[ ( ) ( )]
1
[ ] 1 o

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 GATE QUESTION BANK Digital Circuits

Combinational and Sequential Digital Circuits

ECE - 2007 (A)

1. For the circuit shown, the counter state (B)
(Q1 Q0) follows the sequence (C)
(D)

ECE - 2008
4. For the circuit shown in the following
figure, are inputs to the 4:1
multiplexer. R(MSB) and S are control
bits.

(A)
(B)
(C)
(D)
̅
2. The following binary values were applied
to the X and Y inputs of the NAND latch
shown in the figure in the sequence The output Z can be represented by
indicated below: (A) PQ + P ̅ S + ̅ ̅ ̅
(B) P ̅ +PQ̅ +̅ ̅ ̅
X=0, Y=1; X=0, Y=0; X=1, Y=1
(C) P ̅ ̅ + ̅QR +PQRS + ̅ ̅ ̅
The corresponding stable P, Q outputs (D) PQ̅ +PQR̅ +P ̅ ̅S + ̅ ̅ ̅
will be
X P 5. For each of the positive edge – triggered
J-K flip flop used in the following figure,
the propagation delay is T.
1 1
Q CLK
Y 1 1

(A) P=1, Q=0; P=1, Q=0; P=1, Q=0 or 1

P=0, Q=1 CLK
(B) P=1, Q=0; P=0, Q=1 or P=0, Q=1; 0
P=0, Q=1 T

(C) P=1, Q=0; P=1, Q=1; P=1, Q=0 or t

P=0, Q=1 Which of the following waveforms

(D) P=1, Q=0; P=1, Q=1; P=1, Q=1 correctly represents the output at ?
(A) 1
3. In the following circuit, X is given by
0
0 I0 0 I0 4-to-1
1 I1 4-to-1
1 I1 2T
MUX MUX
1 I2 1 I2 Y X
0 I3 Y 0 I3 (B) 1
S1 S0 S1 S0 0
A B C 4T

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 GATE QUESTION BANK Digital Circuits

(C) 1 then, after a few seconds, made (1, 1). The

0 corresponding stable outputs ( ) are
2T P1 Q1 P1 Q1

(D) 1
0
P2 Q2 P2 Q2
4T

(A) NAND : first (0, 1) then (0, 1)

NOR: first (1, 0) then (0, 0)
6. For the circuit shown in the figure, D has a
(B) NAND : first (1, 0) then (1, 0)
transition from 0 to 1 after CLK changes
NOR: first (1, 0) then (1, 0)
from 1 to 0. Assume gate delays to be
(C) NAND : first (1, 0) then (1, 0)
negligible
NOR: first (1, 0) then (0, 0)
(D) NAND : first (1, 0) then (1, 1)
̅ NOR: first (0, 1) then (0, 1)

9. What are the minimum number of 2 to 1

multiplexers required to generate a 2-
Which of the following statements is true? input AND gate and a 2-input Ex-OR gate?
(A) Q goes to 1 at the CLK transition and (A) 1 and 2 (C) 1 and 1
stays at 1 (B) 1 and 3 (D) 2 and 2
(B) Q goes to 0 at the CLK transition and
stays at 0 Statement for Linked Answer Question 10
(C) Q goes to 1 at the CLK transition and and 11
goes to 0 when D goes to 1 Two products are sold from a vending
(D) Q goes to 0 at the CLK transition and machine, which has two push buttons
goes to 1 when D goes to 1 and . When a button is pressed, the
price of the corresponding product is
ECE - 2009 displayed in a 7-segment display.
7. What are the counting states (Q1, Q2) for If no buttons are pressed ‘ ’ is displayed,
the counter shown in the figure below? signifying ‘ s. ’
If only is pressed, ‘ ’ is disp ayed
signifying ‘ s. ’
If only p are pressed, ‘5’ is disp ayed
ip
ip
signifying ‘ s.5’
If both a d are pressed, ‘E’ is
displayed, Signifying ‘Err r’.
The names of the segments in 7-segment
(A) 11, 10, 00, 11, 10 . . . . . display, and the glow of the display for ‘ ’
(B) 01, 10, 11, 00, 01 . . . . . ‘ ’ ‘5’ a d ‘E’ are sh w be w.
(C) 00, 11, 01, 10, 00, . . . . . a 0 2 5 E
(D) 01, 10, 00, 01, 10 . . . . . . f b
g
e c
8. Refer to the NAND and NOR latches d
shown in the figure. The inputs for
both the latches are first made (0, 1) and

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 GATE QUESTION BANK Digital Circuits

Consider p
(i) Push Button pressed/not Pressed in
a equivalent to logic 1/0
respectively.
(ii) A segment glowing / not glowing in
̅ ̅ ̅
the display is equivalent to logic 1/0
respectively.
(A) (C)
10. If segment a to g are considered as (B) (D)
functions of and , then which are of
the following is correct? ECE - 2011
(A) ̅ d e 14. Two D flip – flops are connected as a
(B) d e synchronous counter that goes through
(C) ̅ e b the following sequence
(D) e b
The connections to the inputs and
11. What are the minimum numbers of NOT are
gates and 2-input OR gates required to (A)
design the logic of the driver for this (B)
7-segment display? (C)
(A) a d
(D)
(B) a d
(C) a d
15. When the output Y in the circuit below is
(D) a d
“ ” i i p ies ha da a has
ECE - 2010 Data D Q Y
D Q
12. The Boolean function realized by the logic
circuit shown is Clock

(A) ha ed fr “ ” “ ”
MUX (B) ha ed fr “ ” “ ”
(C) Changed in either direction
(D) Not changed

16. The logic function implemented by the

circuit below is (ground implies a logic
(A) ∑ 5
“ ”
(B) ∑ 5
MUX
(C) ∑ 5 5
(D) ∑ 5

13. Assuming that all flips flops are in reset

condition initially, the count sequence
observed at in the circuit shown is

(A) F = AND(P, Q) (C) F = XNOR(P, Q)

(B) F = OR(P, Q) (D) F = XOR(P, Q)

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 GATE QUESTION BANK Digital Circuits

ECE - 2014 20. In the circuit shown, choose the correct

17. Five JK flip-flops are cascaded to form the timing diagram of the output (y) from the
circuit shown in Figure. Clock pulses at a given waveforms a d .
frequency of 1 MHz are applied as shown.
The frequency (in kHz) of the waveform
at Q3 is _____. ̅
p y

18. The digital logic shown in the figure

satisfies the given state diagram when Q1
is connected to input A of the XOR gate.

̅̅̅̅ ̅̅̅̅

(A) (C)
(B) (D)

Suppose the XOR gate is replaced by an

21. The outputs of the two flip-flops Q1, Q2 in
XNOR gate. Which one of the following
the figure shown are initialized to 0, 0.
options preserves the state diagram?
The sequence generated at Q1 upon
(A) Input A is connected to ̅̅̅̅ application of clock signal is
(B) Input A is connected to
(C) Input A is connected to ̅̅̅̅ and S is
complemented
(D) Input A is connected to ̅̅̅̅ ̅̅̅̅
̅̅̅̅

19. In a half-subtractor circuit with X and Y as

inputs, the Borrow (M) and Difference
(N = X Y) are given by (A) (C)
(A) (B) (D)
(B)
(C) ̅
(D) ̅ ̅̅̅̅̅̅̅̅

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 GATE QUESTION BANK Digital Circuits

22. The circuit shown in the figure is a

a h a h
E ̅ E ̅

(A) Toggle Flip Flop

(B) JK Flip Flop
(C) SR Latch
(D) Master-Slave D Flip Flop

23. Consider the multiplexer based logic

circuit shown in the figure.

26. An 8-to-1 multiplexer is used to

Which one of the following Boolean
implement a logical function as shown
functions is realized by the circuit?
̅ ̅̅̅ in the figure. The output Y is given by
(A)
(B)
(C) ̅
(D)

24. In the circuit shown, W and Y are MSBs of

the control inputs. The output F is given
by

(A) ̅ ̅ (C) ̅ ̅
(B) ̅ ̅ (D) ̅̅ ̅

27. A 16-bit ripple carry adder is realized

using 16 identical full adders (FA) as
shown in the figure. The carry-
(A) ̅ ̅ ̅̅ propagation delay of each FA is 12 ns and
(B) ̅ ̅ ̅ the sum-propagation delay of each FA is
(C) ̅̅ ̅ ̅ 15 ns. The worst case delay (in ns) of this
(D) ̅ ̅ ̅̅ 16-bit adder will be __________

25. If X and Y are inputs and the Difference

and the Borrow (B) are the
outputs, which one of the following
diagrams implements a half-subractor?
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 GATE QUESTION BANK Digital Circuits

ECE - 2015 ̅̅̅E̅ 2-to-4 ̅ ̅

28. A mod-n counter using a synchronous Decoder ̅ ̅
binary up-counter with synchronous clear ̅ ̅
̅ ̅
input is shown in the figure. The value of
n is_________
i i ary ̅̅̅E̅ 2-to-4 ̅ ̅
er Decoder ̅ ̅
̅ ̅
̅̅̅̅̅̅̅̅̅
E ̅ ̅
(A) (C)
(B) (D)

31. The circuit shown consists of J-K flip-

29. The figure shows a binary counter with
flops, each with an active low
synchronous clear input. With the
asynchronous reset (̅ input). The
decoding logic shown. the counter works
counter corresponding to this circuit is
as a
i ary
er ̅ ̅ ̅

̅̅̅̅̅
(A) A modulo-5 binary up counter
(B) A modulo-6 binary down counter
(C) A modulo-5 binary down counter
(A) mod-2 counter (D) A modulo-6 binary up counter
(B) mod-4 counter
(C) mod-5 counter 32. An SR latch is implemented using TTL
(D) mod-6 counter gates as shown in the figure. The set and
reset pulse inputs are provided using the
30. A 1-to-8 demultiplexer with data input push-button switches. It is observed that
, address inputs (with as the circuit fails to work as desired. The SR
the LSB) and ̅ ̅ as the eight latch can be made functional by changing
demultiplexed outputs, is to be designed
using two 2-to-4 decoders (with enable
e
̅ and address inputs
input E and as
shown in the figure. a d are 5
to be connected to P. Q, R and S, but not
necessarily in this order. The respective ̅
input connections to P, Q, R, and S ese
terminals should be (A) NOR gates to NAND gates
(B) Inverters to buffers
(C) NOR gates to NAND gates and
inverters to buffers
(D) 5 V to ground

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 GATE QUESTION BANK Digital Circuits

33. A three bit pseudo random number 36. The functionality implemented by the
generator is shown. Initially the value of circuit below is
output
is set to 111. The value of
output Y after three clock cycles is

e der
(A) 000 (C) 010
(B) 001 (D) 100
E ab e
ECE - 2016
34. The output of the combinational circuit is a ris a e b ffer
given below is (A) 2-to-1 multiplexer
(B) 4-to-1 multiplexer
(C) 7-to-1 multiplexer
(D) 6-to-1 multiplexer

37. Transistor geometries in a CMOS inverter

have been adjusted to meet the
(A) A+B+C (C) B(C+A)
requirement for worst case charge and
(B) A(B+C) (D) C(A+B)
discharge times for driving a load
capacitor C. This design is to be converted
35. Identify the circuit below.
to that of a NOR circuit in the same
technology, so that its worst case charge
and discharge times while driving the
same capacitor are similar. The channel
lengths of all transistors are to be kept
e der
E der unchanged. Which one of the following
statements is correct?

(A) Binary to Gray code converter

(B) Binary to XS3 converter
(C) Gray to Binary converter
(D) XS3 to Binary converter

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 GATE QUESTION BANK Digital Circuits

Which one of the following statements

correctly describes the choice of signals to
be connected to the inputs , , and
(A) Widths of PMOS transistors should so that the output is ?
be doubled, while widths of NMOS (A) a d
transistors should be halved. (B) a d
(B) Widths of PMOS transistors should (C) a d
be doubled, while widths of NMOS (D) a d
transistors should not be changed.
(C) Widths of PMOS transistors should 40. The state transition diagram for a finite
be halved, while widths of NMOS state machine with states A, B and C, and
transistors should not be changed. binary inputs X, Y and Z, is shown in the
(D) Widths of PMOS transistors should figure
be unchanged, while widths of NMOS
transistors should be halved.

38. Assume that all the digital gates in the

circuit shown in the figure are ideal, the
resistor and the supply voltage
is 5 . The D flip-flops , , , and
are initialized with logic values 0, 1, 0,
1 and 0, respectively. The clock has a 30%
duty cycle.

Which one of the following statements is

correct?
(A) Transitions from State A are
ambiguously defined.
The average power dissipated (in mW) in
(B) Transitions from State B are
the resistor R is __________ ambiguously defined.
(C) Transitions from State C are
39. A 4:1 multiplexer is to be used for ambiguously defined.
generating the output carry of a full (D) All of the state transitions are
adder. A and B are the bits to be added defined unambiguously
while is the input carry and is the
output carry. A and B are to be used as the 41. For the circuit shown in the figure, the
select bits with A being the more delay of the bubbled NAND gate is 2 ns
significant select bit. and that of the counter is assumed to be
zero.

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 GATE QUESTION BANK Digital Circuits

If the state of the counter at the

3-bit clock time is “ ” he he s a e
Synchronous of the counter at (after three clock
Courier cycles) will be
(A) 00 (C) 10
(B) 01 (D) 11
̅̅̅̅̅̅̅̅̅
E E
EE - 2013
44. The clock frequency applied to the digital
circuit show in the figure blow is 1 kHz. If
If the clock (Clk) frequency is 1 GHz, then the initial state of the output Q of the flip
the counter behaves as a – f p is ‘ ’ he he freq e y f he
(A) Mod-5 counter (C) Mod-7 counter output wavefrom Q in kHz is
(B) Mod-6 counter (D) Mod-8 counter

X Q
EE - 2008 T Q
42. A 3 line to 8 line decoder, with active low
outputs, is used to implement a CLK >

3 – variable Boolean function as shown in

the figure.
3L x 8L Decoder
(A) 0.25 (C) 1
0 (B) 0.5 (D) 2
1
z 2
3 F
y EE - 2014
4
x 45. A state diagram of a logic gate which
5
6 exhibits a delay in the output is shown in
7
the figure, where X is the d ’ care
The simplified form of Boolean function condition, and Q is the output
p e e ed i ‘ r d f representing the state.
’ f r wi be ⁄

(A) (X + Z). (̅ ̅ ̅ ). (Y + Z)
⁄
(B) (̅ ̅ ). (X + Y + Z). (̅ ̅ ).
(C) (̅ ̅+ Z). (̅ + Y + Z). (X + ̅ + Z).
(X +Y + ̅ ) The logic gate represented by the state
(D) (̅ ̅ . (̅ ̅ ). (X +̅ + ). diagram is
( ̅ ̅ ) (A) XOR (C) AND
(B) OR (D) NAND
EE - 2011
43. A two-bit counter circuit is shown below. 46. A 3-bit gray counter is used to control the
output of the multiplexer as shown in the
figure. The initial state of the counter is
J Q J Q
. The output is pulled high. The
K ̅ ̅
output of the circuit follows the sequence
K

CLK

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 GATE QUESTION BANK Digital Circuits

48. Two monoshot multivibrators, one

-bi ray 5 positive edge triggered ( ) and another
er negative edge triggered ( ), are
̅
E
connected as shown in figure
5

p
̅ ̅

(A)
(B)
(C) The monoshots a d when triggered
(D) produce pulses of width a d
respectively, where . The steady
47. A JK flip flop can be implemented by T state output voltage of the circuit is
flip-flops. Identify the correct
implementation.

f ip f p

f ip f p

f ip f p EE - 2015
49. In the 4 × 1 multiplexer, the output F is
ive by . i d he req ired
̅
input

f ip f p

(A) 1010 (C) 1000

(B) 0110 (D) 1110

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 GATE QUESTION BANK Digital Circuits

50. The figure shows a digital circuit EE - 2016

constructed using negative edge triggered 53. Consider the following circuit which uses
J-K flip flops. Assume a starting state of 2-to-1 multiplexer as shown in the figure
. This state below. The Boolean expression for output
will repeat after ______ number of F in terms of A and B is
cycles of the clock CLK
0

Y
F
S
1

51. ea f i f Π 5 A B
12, 15) is to be implemented using an 8 × (A) A ⨁ B (C) A + B
1 multiplexer (A is MSB). The inputs ABC
(B) ̅̅̅̅̅̅̅ (D) ̅̅̅̅̅̅̅̅
⨁
are connected to the select inputs
of the multiplexer respectively. 54. The current state of a two JK flip-
0
flop system is 00. Assume that the clock
1 rise-time is much smaller than the delay
2
3 f of the JK flip-flop. The next state of the
4 system is
5
6 5
7

Which one of the following options gives

the correct inputs to pins 0, 1, 2, 3, 4, 5, 6,
7 in order? (A) 00 (C) 11
(A) ̅ (B) 01 (D) 10
(B) ̅ ̅ ̅
(C) ̅ IN - 2007
(D) ̅ ̅ ̅ Statement for Linked Answer Questions
55 and 56
52. In the following sequential circuit, the Consider the circuit shown in the
initial state (before the first clock pulse) following figure.
of the circuit is = 00. The state
, immediately after the clock
pulse is

(A) 00 (C) 10
(B) 01 (D) 11

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 GATE QUESTION BANK Digital Circuits

55. The correct input-output relationship IN - 2008

between Y and ( , ) is Statement for Linked Answer Questions 59
(A) Y= + (C) Y= ⨁ and 60
(B) Y= (D) Y= ⨁ Consider the counter circuit shown
below.
56. The D flip-flops are initialized to l

=000. After 1 clock cycle,

is equal to Q0 Q1 Q2
J Q J Q J Q J Q Q3

Clock
(A) 011 (C) 100
KCLR KCLR KCLR K CLR
(B) 010 (D) 101

57. A sequential circuit is shown in the figure

below. Let the state of the circuit be
encoded as . he ai ̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅
implies that state Y is reachable from
state X in a finite number of clock
transitions. Y

̅A QB 59. In the above figure, Y can be expressed as

QA
̅ Q ̅ Q (A) (C)
CLK TA CLK TB (B) (D)

60. The above circuit is a

(A) Mod – 8 Counter
(B) Mod – 9 Counter
CLK (C) Mod – 10 Counter
Identify the INCORRECT statement. (D) Mod – 11 Counter
(A) (C)
(B) (D) 61. The output F of the multiplexer circuit
shown below expressed in terms of the
58. A MUX circuit shown in the figure below inputs P, Q and R is
implements a logic function . The
R I0
correct expression for is
̅ I1
Z 1 4 1 MUX Y
F1 I2 F
MUX out ̅
̅ 0 R I3 S1 S0
S
X P Q
1
(A) F=P⨁Q⨁R
MUX out
F0 (B) F = PQ + QR + RP
̅ 0 (C) F = (P ⨁ Q) R
S (D) F = (P ⨁ Q)̅
Y
(A) (̅̅̅̅̅̅̅̅)⨁ (C) ⨁ ⨁̅
(B) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(̅̅̅̅̅̅̅̅) ⨁ (D) ⨁ +Z

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 GATE QUESTION BANK Digital Circuits

62. The inverters in the ring oscillator circuit

shown below are identical. If the output
waveform has a frequency of 10 MHz, the
propagation delay of each inverter is
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
Output
3 to 8 Decoder
C B A(L.SB)

̅̅̅̅̅̅̅̅
rese Count
D Q
(A) 5 ns (C) 20 ns Flip-Flop Down
Up/down Counter
Clock
(B) 10 ns (D) 50 ns ear ̅
̅̅̅̅̅̅̅ Count Up

Clock
IN - 2009
63. The figure below shows a 3-bit ripple Assuming that the initial value of counter
counter, with as the MSB. The flip- output ( as zero, the counter
flops are rising-edge triggered. The output in decimal for 12 clock cycles are
counting direction is (A) 0,1,2,3,4,4,3,2,1,1,2,3,4,
J 1
Q1
1
(B) 0,1,2,3,4,5,0,1,2,3,4,5,0,
1 Q J Q J Q Q2
Clock
(C) 0,1,2,3,4,5,5,4,3,2,1,0,1
CLK CLK CLK (D) 0,1,2,3,4,5,4,3,2,1,0,1,2
1 K ̅ 1 K ̅ 1 K ̅
ECE/EE/IN - 2012
(A) Always down
66. The output Y of a 2-bit comparator is logic
(B) Always up
1 whenever the 2-bit input A is greater
(C) Up or down depending on the initial
than the 2-bit input B.
state of q only
The number of combinations for which
(D) Up or down depending on the initial the output is logic 1, is
states of q q and q (A) 4 (C) 8
(B) 6 (D) 10
64. In the figure shown, the initial state of Q is
0. The output is observed after the 67. Consider the given circuit
application of each clock pulse. The
output sequence at Q is

1 J Q

CLOCK CLK
K ̅ In this circuit, the race around
(A) Does not occur
(B) Occurs when CLK = 0
(C) Occurs when CLK = 1 and A =B =1
(A) 0 0 0 0 . . . (C) 1 1 1 1 . . . (D) Occurs when clk = 1 and A = B = 0
(B) 1 0 1 0 . . . (D) 1 0 0 0 . . .
68. The state transition diagram for the logic
circuit shown is
IN - 2011
65. The circuit below shows as up/down
counter working with a decoder and a
flip-flop. Preset and clear of the flip-flop ̅
ee
are asynchronous active-low inputs

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 GATE QUESTION BANK Digital Circuits

(A) 1 MHz, 10-bits (C) 1 MHz, 8-bits

(B) 10 MHz, 10-bits (D) 10MHz, 8-bits

IN - 2015
71. For the circuit shown in the figure, the
rising edge triggered D-flip flop with
asynchronous reset has a clock frequency
of 1 Hz, The NMOS transistor has an ON
resis a e f a d a
resistance of infinity. The nature of the
output waveform is

p ̅

IN - 2013
69. The digital circuit shown below uses two
negative edge- triggered D flip- flops.
Assuming initial condition of and
as zero, the ouput of this circuit is

D1 D0

D-Flip-flop D-Flip-flop 72. The number of clock cycles for the

̅̅̅̅ ̅̅̅̅ duration of an input pulse is counted
using a cascade of N decade counters (DC
1 to DC N) as shown in the figure. If the
clock frequency in mega-hertz is f, the
Clock
(A) 00, 01, 10, 11, resolution and Range: of measurement of
(B) 00, 01, 11,clock
10, input pulse width, b h i s. are
(C) 00, 11, 10, 01, respectively
(D) 00, 01, 11, 11, di i disp ay

IN - 2014 ̅̅̅̅̅̅̅̅̅
di i re is er
70. Frequency of an analog periodic signal in
the Range: of 5 kHz - 10 kHz is to be Clock
Generator E⁄̅ E⁄̅ E⁄̅
measured with a resolution of 100Hz by
measuring its period with a counter.
E/̅: Enable/̅̅̅̅̅̅̅
ese Pulse
Assuming negligible signal and transition shaping
delays the minimum clock frequency and
Input pulse
minimum number of bits in the counter
needed, respectively, are:

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 GATE QUESTION BANK Digital Circuits

a d
f f
a d
f f
a d
f f
a d
f f

IN - 2016
73. A 4 to 1 multiplexer to realize a Boolean
function is shown in the figure
below. The inputs Y and Z are connected
to the selectors of the MUX (Y is more
significant). The canonical sum-of-
product expression for is

(A) Σ (C) Σ
(B) Σ 5 (D) Σ 5

74. A synchronous counter using two J-K flip

flops that goes through the sequence of
states:
is required. To achieve this, the
inputs to the flip flops are

Clock
(A)
(B)
(C)
(D)

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 GATE QUESTION BANK Digital Circuits

Answer Keys and Explanations

ECE PQ
RS 00 01 11 10
1. [Ans. B] ̅̅̅
00 1 1
The i/p to first F/F = ̅̅̅̅̅̅̅̅̅̅̅ 1
01 1 1
The i/p to second F/F = P̅ S
11 1 1
10 1 PQ
0 0 0 0 (initially at rest)
1 clk 0 0 1 1
st So option A is correct choice
2nd 1 1 0 0
3rd 0 0 0 0 5. [Ans. B]
So sequence generated At clock will be divide by 4 and will
00, 01, 10, 00 have 2 T delay w.r.t clock.

2. [Ans. C] 6. [Ans. C]
When X = 0, Y = 1 then P = 1 and Q = 0 Initially, when clk is high and D is low,
X = 0, Y = 0 then P = 1 and Q = 1 Q = 0 or 1,
X = 1, Y = 1 then P = 0 and Q = 1 or When clk goes low and D is also low ,
P = 1 and Q = 0 Q = 1,
When clk is low and D goes high, Q = 0.
3. [Ans. A]
Let the output of first MUX is Y 7. [Ans. A]
Y = ̅ B + A̅ = A ⨁ B
X=̅ ̅ ⨁
So X = A ⨁ B ⨁ C 0 0 0 0 0 0
i.e, ̅ ̅ ̅ ̅ ̅̅
1 1 1 1 1 1
0 0 0 1 1 0
4. [Ans. A]
1 1 0 1 0 0
( ) 5 1 1 1 1 1 1
̅̅ ̅ ̅ ̅
So sequence is (00, 11, 10, 00, 11) or
̅̅ ̅̅̅ ̅ ̅
..
s ap
PQ
RS
8. [Ans. C]
00 01 11 10
̅ ̅̅ For NAND latch, when ( ) are (0, 1),
00 1 1 1
( ) will be (1, 0) and when ( )
01 1 1 SP
are (1, 1), ( ) will be (1, 0).
11 1 1
For NOR latch, when ( ) are (0, 1),
10 1 PQ
( ) will be (1, 0) and when ( )
So ̅̅̅ are (1, 1), ( ) will be (0, 0).
Now only option (A) has two similar
terms, we can say that option A is not 9. [Ans. A]
most simplified version of Z it can be
O
obtained as
Y = AB
B

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 GATE QUESTION BANK Digital Circuits

B 14. [Ans. D]
Q(present) Q (next)
Y=A ⨁B
1
0 0 1 1 1 1
0
A
1 1 0 1 0 1
0 1 1 0 1 0
B 1 0 0 0 0 0
10. [Ans. B] ⨀
a b c d e f g ̅̅̅̅ ̅̅̅̅
̅
0 0 1 1 1 1 1 1 0
0 1 1 0 1 1 0 1 1
15. [Ans. A]
1 0 1 1 0 1 1 0 1
Given Y=1, this implies
1 1 1 0 0 1 1 1 1 Both the output of D- flip flop
a should be 1 i.e, input at first flip flop is 1
b ̅̅̅̅ . and for output of 2nd flip flop to be 1,
̅̅̅̅ . inverted output of first flip should be 1 in
d e previous clock, for which input must be 0
e ̅̅̅̅ so data is changing from 0 to 1.
f ̅̅̅̅
16. [Ans. D]
From the CKT
d e 0 is connected to &
d ‘ ’ is e ed and
11. [Ans. D]
a es
a es 17. [Ans. *] Range: 62.4 to 62.6
.5
12. [Ans. D]
̅̅ ̅ ̅̅ ̅̅
̅̅ ̅ ̅ ̅ 18. [Ans. D]
̅ If one input of the gate is kept constant,
̅̅ ̅ ̅̅ [ ] and A is interchanged with ̅, an XNOR
. gate acts as XOR gate.
̅̅ ̅̅ ̅ ̅ ̅ ̅
̅̅ ̅̅̅ ̅̅
19. [Ans. C]
Σ 5
In half subtractor
Difference y y
13. [Ans. D]
y
⨀ = b rr w y
x y Borrow Difference
Initially 0 0 0 0 0 0 0
After first clk 1 0 0 0 1 1 1
After 2 clk
nd 1 1 0 1 0 0 1
After 3rdclk 0 1 1 1 1 0 0
So . . . . . ..

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 GATE QUESTION BANK Digital Circuits

20. [Ans. C] 24. [Ans. C]

̅ ̅̅ ̅̅̅ ̅ ̅ ̅̅
̅ ̅ ̅̅
̅
y 25. [Ans. A]
̅

26. [Ans. C]
̅
̅̅ ̅̅ ̅
̅ ̅

27. [Ans. *] Range: 194.9 to 195.1

Worst case propagation delay
= carry propagation delay of 15FA stages
+ max(carry Pd & sum Pd of last FA
stage)
So wave form is correct 5 5
5 s
21. [Ans. D]
This is a figure of Johnson counter 28. [Ans. *] Range: 7 to 7
So i i ary
i p
er
0 0
̅̅̅̅̅̅̅̅̅
E
1 0
1 1
0 1
0 0 The NAND gate shown is connected to
1 0 synchronous clear that is, clear will be
So = applied after clock pulse
Clock ̅̅̅̅̅̅̅̅
22. [Ans. D] 0 0 0 0 0 1
1 0 0 0 1 1
23. [Ans. D] 2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 0
7 0 0 0 0
As clear is synchronous input, clear will
be zero in 6th clock pulse, but output is
cleared in next clock pulse so total
p f firs ̅ ̅
number of states = Modulus = 7
e
p f se d ̅ ̅

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 GATE QUESTION BANK Digital Circuits

29. [Ans. B] 32. [Ans. D]

̅̅̅E̅ ̅ ̅
̅ ̅
̅ ̅
̅ ̅

Once the output of Ex-NOR gate is 0 then ̅̅̅E̅ ̅ ̅

counter will be RESET. So, Ex-NOR- ̅ ̅
̅ ̅
gate will produce logic 0 for ̅ ̅
. So, the counter will show the sequence
like: The OR gate output is zero, when inputs
are zero. Then, decodes will be enabled
P=Q=0, 1st decoder will work with inputs
So, it is MOD-4 counter. S, R
P = 0, Q = 1, second decoder will work
30. [Ans. D] with input S, R
We need to implement 1: 8 DEMUX select So, Q, S, R are inputs of
lines of DEMUX should be mapped to demultiplexer
address lines of decoder. So, LSB of is
DEMUX should be connected to LSB of
address lines of decoder.
33. [Ans. D]

Input to both the decoder should be same

so
- - - 1 1 1
NOT gate along with OR gate in case to 1stclk 0 1 1 0 1 1
select one decoder at a time so . 2 clk 0
nd 0 1 0 0 1
3rd clk 1 0 0 1 0 0
f er hree p ses p y y y

34. [Ans. C]
A
C
31. [Ans. A]
Clock is taken from normal output and it
B C
is ve edge triggering. So, it is UP-
counter.
Input of the NAND-gate is taken from AB
a d . So, a d . C
To find the modulus For sake of calculation putting the value
of C = 0
So, it is MOD-5 binary UP-counter. And thus we get x = 0; z = AB; y = AB
So, only possible answer is B(C + A)

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 GATE QUESTION BANK Digital Circuits

35. [Ans. C] 39. [Ans. A]

Assume In case of a full adder,
Then output of first decoder = which ∑ 5
is connected to of encoder
5 Applied at select Applied at data
p fe der input of MUX input of MUX
p he ir i a d p
101 0 2 4 ⑥
Consider Gray to Binary converter if input 1 ③ ⑤ ⑦
= 111 then output is 101. 0 1
the given circuit acts like Gray to
Binary converter

36. [Ans. B]
From the given figure
40. [Ans. C]
Y
For State A
0 0 P
X Y Z Present State Next State
0 1 Q
0 0 0 A B
1 0 R
0 0 1 A A
1 1 S
0 1 0 A A
Truth table describes the function ability
0 1 1 A A
of a 4 to 1multiplexer
1 0 0 A C
1 0 1 A C
37. [Ans. B]
1 1 0 A A
1 1 1 A A
38. [Ans. *] Range: 1.45 to 1.55
For State B
CLK
X Y Z Present State Next State
0 0 1 0 1 0 0
0 0 0 B A
1 0 0 1 0 1 1
0 0 1 B C
2 1 0 0 1 0 0
0 1 0 B B
3 0 1 0 0 1 1
0 1 1 B B
4 1 0 1 0 0 1
1 0 0 B A
5 0 1 0 1 0 0
The waveform of the gate output 1 0 1 B B
1 1 0 B B
1 1 1 B B
For State C
5 X Y Z Present State Next State
0 0 0 C C
5
0 0 1 C C
Average power dissipated
0 1 0 C C
5
0 1 1 C B
5 1 0 0 C C
.5
1 0 1 C A
1 1 0 C C
1 1 1 C AB

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 GATE QUESTION BANK Digital Circuits

In state ‘ ’ whe he From above Figure

a bi i y rs. e a se fr s a e‘ ’ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
[ ̅ . ̅̅̅̅̅̅̅̅̅̅̅
̅ ]
he e sae e a se ̅ a ways
he e sae ̅̅̅̅̅̅̅̅̅
̅ a ways
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ . ̅̅̅̅̅̅̅̅̅̅̅
̅
41. [Ans. D]
̅̅̅̅
. ̅
o/p of
Clk i p a ways
NAND
0 0 0 1 0 0 1 r ‘ ’ f ip flop if input is =1 then output
1 0 0 1 1 0 1 0 will be complemented at the time of
2 0 1 0 1 0 1 1 triggering.
CLK
3 0 1 1 1 1 0 0
4 1 0 0 1 1 0 1
5 1 0 1 1 1 1 0 T

6 1 1 0 0 0 0 0
If delay of NAND gate is 0 then the given 2T
circuit acts like Mod-6 counter. But here f .5 f
delay of NAND is 2ns so it will count two .5
more clocks before it resets the counter .5
[ peri d s a e de ay s]
the given counter acts like Mod-8 45. [Ans. D]
counter

EE
42. [Ans. A]
∑ 5 ae
[ ( ) ]
46. [Ans. A]
Gray code output
43. [Ans. C]
Clock Input Output
0 0 0
̅

o/p 0 0 1
0 0 0 1 1
0 1 0 1 0
Initial state 1 0
1 1 0 1 1 1 1 0 1 1 0
2 0 1 1 0 0 1 1 1 1 1
3 1 0 0 1 0 1 0 1
1 0 1
44. [Ans. B] When ̅
E p
ee i p s
p
X Q
T Q
47. [Ans. A]
CLK > T-FF to JKFF is given by eq
̅
This is implemented on options [A]

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 GATE QUESTION BANK Digital Circuits

48. [Ans. C] 52. [Ans. B]

Let is initially high. Since is from ̅ ̅
will be high for time. The - - - - 0 0
waveform is shown below: 0 1 1 0 0 1
1 0 1 0 1 1
̅ 1 0 0 1 1 0
0 1 0 1 0 0
If is a Johnson (MOD-4) counter. Divide
333 by 4, so it will complete 83 cycle and
ri er
remainder clock is 1, at the completion of
y es p ’s i a so, next at
333rd clock pulse output is at .

53. [Ans. D]

49. [Ans. B]

AB ̅
̅̅ ̅̅̅̅̅̅̅̅
00 0
01 54. [Ans. C]
10 5V
11 AB
J J
A B
50. [Ans. *] Range: 6 to 6
First flip flop acts as mod-2 counter K K
Second 2 flip flops from mod
Johnson counter = mod counter Next when clock applied toggles as J, K
Overall modulus = mod counter input of A connects to 5 V.
Also, toggles as previous state
51. [Ans. B]
values is J which is the input of J, K of B.
Given maxterm f 5 5
Thus, output of next state is 11
so minterm
f
IN
∑
55. [Ans. B]

̅ Y=
0 2 4 6 8 10 12 14
D(1) 1 3 5 7 9 11 13 15
56. [Ans. B]
̅ 1 ̅ 1 1 1 D ̅
a d
So initially it means
so after one clock cycle
will be 010.

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 GATE QUESTION BANK Digital Circuits

57. [Ans. D] J K ̅ ̅
01 10, both = 1 so and 1 1 0
both will toggle. 1 0 1

1 0 1
58. [Ans. B]
1

65. [Ans. D]
59. [Ans. A]
Initially Q=0 and count up ( ̅ =1) is active
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Y = ̅̅̅̅̅̅̅ . ̅̅̅̅̅̅̅ so it started counting up and when it
= + reaches to 5 then decoder output at pin 5
= becomes 0 and preset will be active and it
will set Q and it will make the counter
60. [Ans. C] mode down and count becomes 4, then 3
Whenever Y=1, then clear input of all the then 2 then 1 then 0, as soon as it reaches
s re eives ‘ ’ a d p s f he 0, decoder output at pin 0 is low and clear
counter will be reset. When count = 1010, is active and Q goes to 0 and ̅ so up
Y=1 and counter will be reset. is active and it counts 1,2,
Q3 Q2 Q1 Q0 So sequence is 0,1,2,3,4,5,4,3,2,1,0,1,2.
1 0 1 0
1 1 0 0 66. [Ans. B]
1 1 1 0 Let A1 A0 be the bits of number A and
B1B0 be the bits of number B and let Y be
61. [Ans. A] the output
A1 A0 B1 B0 Y
( ) ( ) 0 0 0 0 0
( ) 0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
62. [Ans. B] 0 1 0 0 1
0 1 0 1 0
f
0 1 1 0 0
Where N - no. of inverters 0 1 1 1 0
And - Propagation delay of each, so 1 0 0 0 1
se A1 A0 B1 B0 Y
1 0 0 1 1
63. [Ans. A] 1 0 1 0 0
Since triggering in positive edge 1 0 1 1 0
triggering & Q of pervious flip flop is 1 1 0 0 1
input to next hence always down
1 1 0 1 1
1 1 1 0 1
64. [Ans. C]
̅ Also the truth table 1 1 1 1 0
From the truth table we see that the
ber f i es ‘ ’ be es is

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 GATE QUESTION BANK Digital Circuits

67. [Ans. A] 70. [Ans. C]

Min clock frequency

5
i
̅

71. [Ans. A]
= . . Before solving the problem, consider the
next
= A.CLK + Q following fact.
 Clock is +ve edge triggered and input
next = A.CLK +
to D flip-flop is constant i.e logic 1.
If CLK = 1 and A and B = 1
 Reset pin of Flip flip is active high and
then } No race around it can function at any moment of time
If CLK = 1 and A = B = 0 independent to clock. Also note that
reset will be triggered when
} No race around terminal voltage just crosses 0.1 V.
Thus race around does not occur in the  N-MOS behave as open switch (off
circuit state, ) when ̅ and it will
behave as a resistance of 1000 when
68. [Ans. D] ̅ (as ON resistance is specified).
State table  Now for analysis, assume capacitor is
A D initially uncharged and a +ve edge is
triggered to D-flipflop, as its input is
0 0 1 1
high. Then Q=1 and ̅ .
0 1 0 0
 When ̅ , N-MOS is off, assuming
1 0 0 0 the input resistance of comparator
1 1 1 1 infinite. Then the source current can
From State table flow only through the capacitor. Now
A=O we have to see how much time the
capacitor will take to reach 0.1 V. So
Q=O Q=1 that and R will change from 0
A=O to 1 and as the reset terminal will be
A=1 A=1 triggered the state of flip-flop changes
i.e. ̅ . and N-MOS gets ON.
69. [Ans. B] As the integration of step is ramp if we
State table integrate the constant current voltage
Present Next will be ramp.
state state  For this use the capacitor voltage
equation.
0 0 0 1 0 1
0 1 1 1 1 1
1 1 1 0 1 0
1 0 0 0 0 0
00, 01, 11, 10, 00
∫i d

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 GATE QUESTION BANK Digital Circuits

5 s
. ∫ d

. . se i i se
p . har i is har i
a p E p e ay

s s

ese
 So at t = 0.2sec, N-MOS is ON. Now the
circuit is equivalent to a current source
connected to a parallel combination of RC 72. [Ans. B]
with non-zero initial voltage of capacitor T
(0.1V).
Input
 Now the capacitor will discharge from its
pulse
initial voltage with time constant Clock
= RC = 2ms and at 10 it will react pulse
steady state i.e., at 20 m.sec.
The nature of discharge is exponential
decay.
The Resolution (R) is the smallest change
that is detectable.

f
Range: of measurement of input width =T

73. [Ans. A]
 So we can conclude from the above y y y y y
analysis that capacitor takes 200 msec to y y y
charge upto 0.1V and 20 msec to Σ
discharge to the steady state value.
 So if the +ve edge of clock appeared at 74. [Ans. B]
t = 0 then at 200 msec it completed its Note: OBSERVE is toggling on every
charging and at 220 msec it completed its clock
discharging. This continues in each clock
cycles. can be both connected
This matches with the option given
 The following waveform gives further
clarity as f s

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 GATE QUESTION BANK Digital Circuits

AD/DA Convertor

ECE-2007 ECE-2011
Statement for Linked Answer Q.No 1 and 2 5. The output of a 3 – stage Johnson (twisted
In the Digital-to-Analog converter circuit – ring) counter is fed to a digital – to –
shown in the figure below, = 10 V and analog (D/A) converter as shown in the
R = 10kΩ. figure below. Assume all states of the
R R R I 2R counter to be unset initially. The
V
waveform which represents the D/A
R
2R 2R R
2R 2R converter output is
+ V0 D/A
Converter

1. The current I is D D D
(A) 31.25 μA (C) 125 μA
(B) 62.5 μA (D) 250 μA

2. The voltage Vo is Johnson

(A) 0. 1 (C) 3.125 Clock
Counter
(B) 1.562 (D) 6.250
(A)
ECE-2008
)
Statement for linked Answer Questions 3
and 4
In the following circuit, the comparator
output is logic “1” if and is logic
“0”otherwise. The D/A conversion is
done as per the relation (B)
= ∑ 2 Volts, where )
(MSB), and (LSB) are the
counter outputs.
The counter starts from the clear state.
4 bit D/A
converter
2 Digit (C)
+5V LED
Binary
to Display
̅̅̅̅
BCD )
̅̅̅̅̅ 4bit
Upcounter

= 6.2
Clock

3. The stable reading of the LED displays is (D)

(A) 06 (C) 12
(B) 07 (D) 13 )

4. The magnitude of the error between

and at steady state in volts is
(A) 0.2 (C) 0.5
(B) 0.3 (D) 1.0

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 GATE QUESTION BANK Digital Circuits

ECE-2014 If the flash ADC has 8 bit resolution,

6. For a given sample-and-hold circuit, if the which one of the following alternatives is
value of the hold capacitor is increased, closest to the maximum sampling rate?
then (A) 1 mega samples per second
(A) Droop rate decreases and acquisition (B) 6 mega samples per second
time decreases (C) 64 mega samples per second
(B) Droop rate decreases and acquisition (D) 256 mega samples per second
time increases
(C) Droop rate increases and acquisition
time decreases EE - 2015
(D) Droop rate increases and acquisition 9. An 8-bit, unipolar Successive
time increases Approximation Register type ADC is used
to convert 3.5 V to digital equivalent
ECE - 2015 output. The reference voltage is +5 V. The
7. Consider a four bit D to A converter. The output of the ADC, at the end of 3rd clock
analog value corresponding to a digital pulse after the start of conversion, is
signals of values 0000 and 0001 are 0 V (A) 1010 0000 (C) 0000 0001
and 0.0625 V respectively. The analog (B) 1000 0000 (D) 0000 0011
value (in Volts) corresponding to the
digital signal 1111 is ____________ EE - 2016
10. A 2-bit flash Analog to Digital Converter
ECE - 2016 (ADC) is given below. The input is
8. In an N bit flash ADC, the analog voltage is 0 3 Volts. The expression for the
fed simultaneously to 2 1 LSB of the output as a Boolean
comparators. The output of the function of an is
comparators is then encoded to a binary 3
format using digital circuits. Assume that
100 Ω
the analog voltage source (whose
output is being converted to digital
format) has a source resistance of 5 Ω as 200 Ω
shown in the circuit diagram below and
Digital Circuit

the input capacitance of each comparator

200 Ω
is 8 pF. The input must settle to an
accuracy of 1/2 LSB even for a full scale
input change for proper conversion. 100 Ω
Assume that the time taken by the
thermometer to binary encoder is
negligible. (A) [̅̅̅̅̅̅̅̅̅] (C) [ ]
(B) ̅ [̅̅̅̅̅̅̅̅̅] (D) ̅ [ ]
ref
IN-2007
11. The circuit shown in the figure below
Thermometer works as a 2-bit analog to digital
ref2 code to binary Digital converter for 0 3 .
conversion output

ref1

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 GATE QUESTION BANK Digital Circuits

3V ( ) tart (D) tart

conversion conversion

0.5kΩ 1 0 0 0 1 0 0 0

0 1 0 0 1 1 0 0
1.0kΩ
Digital 0 1 1 0 1 1 1 0

1.0kΩ Circuit 0 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1
0.5kΩ
n n
conversion conversion

The MSB of the output , expressed as a IN-2014

Boolean function of the inputs , , , is 14. A thermopile is constructed using 10
given by junctions of Chromel-Constantan
(A) (C) (sensitivity 60 μ /°C for each junction)
(B) (D) + connected in series. The output is fed to
an amplifier having an infinite input
IN-2009 impedance and a gain of 10. The output
12. An 8- it ADC with 2’s complement from the amplifier is acquired using a
output, has a nominal input Range: of 10 it ADC, with reference voltage of 5 V.
2V to +2V. It generates a digital code of The resolution of this system in units of
00H for an analog input in the Range: °C is _________
– 7.8125mV to +7.8125mV. An input of
1.5 will produce a digital output of 15. An N-bit ADC has an analog reference
(A) 90H (C) 9BH voltage V. Assuming zero mean and
(B) 96H (D) A0H uniform distribution of the quantization
error, the quantization noise power will
IN - 2010 be:
13. A 4-bit successive approximation type (A) (C)
ADC has a full scale value of 15V. The 12(2 1) 12(2 1)
sequence of the states, the SAR will ( ) (D)
traverse, for the conversion of an input of 12(2 1) √12
8.15V is
16. The circuit in the figure represents a
(A) tart (C) tart
conversion conversion counter-based unipolar ADC. When SOC is
asserted the counter is reset and clock is
1 0 0 0 1 0 0 0 enabled so that the counter counts up and
1 1 0 0 0 1 0 0 the DAC output grows. When the DAC
output exceeds the input sample value,
1 0 1 0 0 0 1 0 the comparator switches from logic 0 to
1 0 0 1 0 0 0 1 logic 1, disabling the clock and enabling
the output buffer by asserting EOC.
1 0 0 0 0 0 0 0 Assuming all components to be ideal,
n n DAC output and input to be positive, the
conversion conversion

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 GATE QUESTION BANK Digital Circuits

maximum error in conversion of the IN - 2016

analog sample value is: 17. A 200 mV full scale dual-slope 3 ½ digit
nput
Comparator
tart of conversion DMM has a reference voltage of 100 mV
ample ( C)
l
Control and a first integration time of 100 ms. For
l logic an input of [100 10 cos(100 t)] m ,
Reset l Clock the conversion time (without taking the
auto-zero phase time into consideration)
l
R 2R p
l
in millisecond is _________
La er counter
DAC
l
l utpt uffer
na le
n of
l
l l Conversion
( C)
(A) Directly proportional to
(B) Inversely proportional to
l
(C) Independent of
(D) Directly proportional to clock
frequency

Answer Keys & Explanations

ECE 4. [Ans. B]
1. [Ans. B] In steady state = 0.5 0 2 = 6.5V
So error = 6.5 6.2 = 0.3V
R R R 16 2R
2
V
R 2R 2R 2R 2R R 5. [Ans. A]
For the Johnson counter sequence
16
A V0 D D D
0 0 0 0
Due to virtual ground, node A can be 1 0 0 4
considered as ground so = 10 1 1 0 6
10 1 1 1 7
o = = 1mA
10 0 1 1 3
o = = 62.5 μA 0 0 1 1
16
0 0 0 0
2. [Ans. C]
6. [Ans. B]
= R[ ]= 3.125 v
16 n a capacitor rop rate in given an
t
v
3. [Ans. D] we know i = C
t
= 2 volts v 1
2 ⇒
t C
Counter will stop when VDAC> 6.2 volt From the above relation it is clear that if
So counter will stop when capacitor value increases then the drop
= 1101 rate decreases because of inversion
o L D will isplay 1101 i.e CD ⇒ 13 relation.

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 GATE QUESTION BANK Digital Circuits

C So, at the end of 1st clock pulse the output

Also = C = it ⇒ t = ⇒t c
i is 10000000.
From the above relation, it is clear that if On second clock pulse the value loaded to
capacitor value increases acquisition time output register is (10100000) = (1 2)
also increases as of proportionality Then = 160 20 m = 3.
relation So, 3.5 3. ⇒ Clear the loaded bit
So, at the end of 2nd clock pulse output is
7. [Ans. *] Range: 0.93 to 0.94 (10000000)
Analog output = On third clock pulse the value loaded to
[Resolution] × [Decimal equivalent of output register is (10100000) = (160)
Binary] Then = 160 20 m = 3.2
= (0.0625)(15) = 0. 3 5 So 3.5 3.2 ⇒ Maintain the loaded bit
So at the end of 3rd clock pulse output is
8. [Ans. A] (10100000)

EE 10. [Ans. A]
9. [Ans. A]
The block diagram of SAR type ADC is as 0 0 0 0 0
follows 1 0 0 0 1
tart of
1 1 0 1 0
conversion
Control logic
CL C 1 1 1 1 1
1 C = 2.56
00 01 11 10
2 C = 3. utput Register
0 0
3 C = 3.2
1 1 0 1
it DAC [ ]
Unipolar means all the voltages will be = [ ]
+ve i.e. nothing is ve.
The functionality of SAR type DAC is, it IN
will load a value to output register with 11. [Ans. B]
MSB = 1 and remaining bit = 0, and it will Truth table of ADC is
cross check a logic as follows.
f ⇒ Maintain the loaded bit 0 0 0 0 0
f ⇒ Clear the loaded bit. 0 0 1 0 1
This process continues up to 8 number of 0 1 1 1 0
clock pulses 1 1 1 1 1
The output of DAC = (Resolution) × ⇒ =
(Decimal equivalent of applied binary)
From the given information 12. [Ans. D]
5 8 – it ADC o/p is in 2’s complement form
Resolution = = 20 m
2 1 i.e it represents 12 to 12
When SOC is applied on 1st clock the
i/p voltage Range: = 2 to 2
value located to output register is
i.e 2V 12
(10000000) = (12 ) 1.5
Then = 12 20 m = 2.56 1.5 12 = 6
2
So, 3.5 2.56 ⇒ Maintain the bit

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 GATE QUESTION BANK Digital Circuits

It is 96 for 1.5 analog input, while is

given an 6 = 2 complement of +96
= 2’s complement of 01100000
=10100000
= A0H

13. [Ans. A]
By characteristics of SAR ADC.

14. [Ans. *] Range: 0.800 to 0.833

For 10 junctions the thermopile voltage
will be 600 μ = 0.6 m
When it measured through amplifier of
gain 10, its voltage will be 6 mV. So, the
thermopile sensitivity after amplification
is 0.006 V/° C
Which will be input to ADC of resolution
= /2 1
ADC resolution = 5/1023=0.00488
In terms of temperature, the resolution is
0.00488/0.006=0.814

15. [Ans. A]

16. [Ans. A]
Maximum error is equal to step size
which is directly proportional to .
a imum rror =
2 1

17. [Ans. *] Range: 199 to 201

In dual slope converter total conversion
time
T= 1st integration period + 2nd integration
period
=T T = 100 msec T
To obtain T we can use in T =T T
⇒ 100 m 100 msec = 100 m T
⇒ T = 100 m sec
T = 100 100 = 200 m sec.

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 GATE QUESTION BANK Digital Circuits

Semiconductor Memory

ECE-2014 EE-2009
1. If WL is the Word Line and BL is the Bit 3. The increasing order of speed of data
Line, an SRAM cell is shown in access for the following devices is
i. Cache Memory
̅̅̅̅ ii. CDROM
iii. Dynamic RAM
iv. Processor Registers
v. Magnetic Tape
(A) (v), (ii), (iii), (iv), (i )
(B) (v), (ii), (iii), (i), (iv)
(C) (ii), (i), (iii), (iv), (v)
̅̅̅̅ (D) (v), ( ii), (i) , (iii), (iv)

IN-2011
4. An bit RAM is interfaced to an
8085 microprocessor. In a fully decoded
Scheme if the address of the last memory
location of this RAM is 4FFFH, the address
̅̅̅̅
of the first memory location of the RAM
will be,
(A) 1000 H (C) 3000 H
(B) 2000 H (D) 4000 H

̅̅̅̅

ECE - 2015
2. A 16 Kb (=16,384 bit) memory array is
designed as a square with an aspect ratio
of one (number of rows is equal to the
number of columns). The minimum
number of address lines needed for the
row decoder is ____________

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 GATE QUESTION BANK Digital Circuits

Answer Keys & Explanations

ECE
1. [Ans. B]
For an SRAM construction four MOSFETs
are required (2-PMOS and 2-NMOS) with
interchanged outputs connected to each
CMOS inverter. So option (B) is correct.

2. [Ans. *] Range: 7 to 7
Generally the structure of a memory chip
= Number of Row × Number of column

The number of address line required for

row decoder is n where

As per information given in

question:

EE
3. [Ans. B]
Processor registers has highest speed.
Followed by cache memory then dynamic
ram (slower than static ram because of
refreshing required)

IN
4. [Ans. C]
Capacity of chip
= last memory address – First memory
address+1

= last memory address – Capacity of

chip+1
= 4FFFH – 2000H+1
=3000H

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 GATE QUESTION BANK Digital Circuits

Introduction to Microprocessors

ECE-2010 (A) 8CH (C) 23H

1. For the 8085 assembly language program (B) 64H (D) 15H
given below, the content of the
accumulator after the execution of the ECE-2014
program is 4. For the 8085 microprocessor, the
3000 MVI A, 45H interfacing circuit to input 8-bit digital
3002 MOV B, A data ( ) from an external device
3003 STC is shown in the figure. The instruction for
3004 CMC correct data transfer is
3 to 8 ⁄ e ice
3005 RAR ecoder
5
3006 XRA B A
4
A 3 igital ata us
(A) 00H (C) 67H 2 inputs
A A 1
(B) 45H (D) E7H 0
̅̅̅̅̅ ̅̅̅̅̅̅ ̅̅̅̅̅
S S

2. In the circuit shown, the device connected ̅̅̅̅̅

to Y5 can have address in the range A
A A
A
A
A8 A A A
A
A 5 A A
A10 To de ice A
A
hip select A
4 S138
3 to 8 (A) MVI A, F8H (C) OUT F8H
decoder (B) IN F8H (D) LDA F8F8H

A11 ̅̅̅̅̅̅
2A
A12
5. An 8085 microprocessor executes “STA
A13 ̅̅̅̅̅̅
2 1234H” with starting address location
A14
A15 1 1FFEH (STA copies the contents of the
̅
accumulator to the 16-bit address
location). While the instruction is fetched
(A) 2000 20FF (C) 2E00 2EFF and executed, the sequence of values
(B) 2D00 2DFF (D) FD00 FDFF written at the address pins A A is
(A) 1FH, 1FH, 20H, 12H
ECE-2011 (B) 1FH, FEH, 1FH, FFH, 12H
3. An 8085 assembly language program is (C) 1FH, 1FH, 12H, 12H
given below. Assume that the carry flag is (D) 1FH, 1FH, 12H, 20H, 12H
initially unset. The content of the
accumulator after the execution of the ECE - 2015
program is 6. In an 8085 microprocessor, the shift
MVI A, 07H registers which store the result of an
RLC addition and the overflow bit are,
MOV B, A respectively
RLC (A) B and F (C) H and F
RLC (B) A and F (D) A and C
ADD B
RRC

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 GATE QUESTION BANK Digital Circuits

7. In an 8085 microprocessor, which one of Address Contents

the following instructions changes the .. ..
content of the accumulator? 26FE 00
(A) MOV B, M (C) RNZ 26FF 01
(B) PCHL (D) SBI BEH 2700 02
2701 03
8. Which one of the following 8085 2702 04
microprocessor programs correctly .. ..
calculates the product of two 8-bit The contents of stack pointer (SP),
numbers stored in registers B and C? Program counter (PC) and (H, L) are
(A) MVI A, 00 H 2700H, 2100H and 0000H respectively,
JNZ LOOP when the following sequence of
LOOP DCR B instruction are executed,
HLT 2100 H: DAD SP
(B) MVI, A, 00H 2101 H: PCHL
CMP C The contents of (SP) and (PC) at the end
LOOP DCR B of execution will be
JNZ LOOP (A) PC = 2102 H, SP = 2700 H
HLT (B) PC = 2700 H, SP = 2700 H
(C) MVI A, 00H (C) PC = 2800 H, SP = 26 FE H
LOOP ADD C (D) PC = 2A02 H, SP= 2702 H
DCR B
JNZ LOOP EE-2009
HLT 11. In an 8085 microprocessor, the contents
(D) MVI A, 00H of the Accumulator, after the following
ADD C instructions are executed will become
JNZ LOOP XRA A
LOOP INR B MVI B, F0H
HLT SUB B
(A) 01 H (C) F0 H
ECE - 2016 (B) 0F H (D) 10 H
9. In an 8085 microprocessor, the contents
of the accumulator and the carry flag are EE-2010
A7 (in hex) and 0, respectively. If the 12. When a “ A Addr” instruction is
instruction RLC is executed, then the executed, the CPU carries out the
contents of the accumulator (in hex) following sequential operations
and the carry flag, respectively, will be internally:
(A) 4E and 0 (C) 4F and 0 Note:
(B) 4E and 1 (D) 4F and 1 (R) means content of register R
((R)) means content of memory location
EE-2008 pointed to by R
10. The contents (in Hexadecimal) of some of PC means Program Counter
the memory location in an 8085A based SP means Stack Pointer
system are given below

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 GATE QUESTION BANK Digital Circuits

(A) (SP) incremented The interfacing circuit makes use of 3 Line

(PC) Addr to 8 Line decoder having 3 enable lines
((SP)) (PC) ̅ ̅ . The address of the device is
(B) (PC) Addr (A) 50 (C) A0
((SP)) (PC) (B) 5000 (D) A000
(SP) incremented
(C) (PC) Addr 15. In an 8085 microprocessor, the following
(SP) incremented program is executed
((SP)) (PC) Address location - Instruction
(D) ((SP)) (PC) 2000H XRA A
(SP) incremented 2001H MVI B, 04H
(PC) Addr 2003H MVI A, 03H
2005H RAR
EE-2011 2006H DCR B
13. A portion of the main program to call a 2007H JNZ 2005
subroutine SUB in an 8085 environment
200AH HLT
is given below.
: At the end of program, register A contains
: (A) 60H (C) 06H
LXI D, DISP (B) 30H (D) 03H
LP: CALL SUB
:
: 16. In 8085 microprocessor, the operation
It is desired that control be returned to performed by the instruction LHLD
S 3 when the RET instruction 2100 is
is executed in the subroutine. The set of
(A) H 21 00
instructions that precede the RET
instruction in the subroutine are (B) H 2100 3101
(A) POP D (C) POP H (C) H 2101 2100
DAD H DAD D (D) H 00 21
PUSH D PUSH H
(B) POP H (D) XTHL IN-2006
DAD D INXD 17. An 8085 assembly language program is
INX H INX D given as follows. The execution time of
INX H INX D each instruction is given against the
INX H XTHL instruction in terms of T-state.
PUSH H Instruction T-states
MVI B, 0AH 7T
EE-2014 LOOP: MVIC, 05H 7T
14. An output device is interfaced with 8-bit DCR C 4T
microprocessor 8085A. The interfacing
DCR B 4T
circuit is shown in figure
A JNZ LOOP 10T/7T
8
The execution time of the program in
8
3 8 ecoder terms of T-states is
A
A 0
1 utput ort (A) 247 T (C) 254 T
A
2 (B) 250 T (D) 257 T
A 3 8
4
5
A
̅ utput e ice
̅
̅̅̅̅̅
W
̅

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 GATE QUESTION BANK Digital Circuits

18. A memory mapped I/O device has an SUB A

address of 00F0H. Which of the following MOV C, A
8085 instructions outputs the content of LOOP1: INR A
the accumulator to the I/O device? DAA
(A) LXI H, 00F0H (C) LXI H, 00F0H JC LOOP2
MOV M, A OUT F0H JNC LOOP1
(B) LXI H, 00F0H (D) LXI H, 00F0H LOOP2: NOP
OUT M MOV A, M (A) 63H (C) 99H
(B) 64H (D) 100H
IN-2007
19. 8-bit signed integers in 2’s complement 22. A 2k×8 bit RAM is interfaced to an 8-bit
form are read into the accumulator of an microprocessor. If the address of the first
8085 microprocessor from an I/O port memory location in the RAM is 0800H,
using the following assembly language the address of the last memory location
program segment with symbolic will be
addresses. (A) 1000H (C) 4800H
BEGIN: INPORT (B) 0FFFH (D) 47FFH
RAL
JNC BEGIN IN-2009
RAR
23. The following is an assembly language
END: HLT
This program program for 8085 microprocessors
(A) Halts upon reading a negative Address Instruction Code Mnemonic
number 1000H 3E06 MVI A, 06H
(B) Halts upon reading a positive 1002H C6 70 ADI 70H
number 1004H 32 07 10 STA 1007H
(C) Halts upon reading a zero 1007H AF XRA A
(D) Never halts 1008H 76 HLT
When this program halts, the accumulator
20. A snapshot of the address, data and contains
control buses of an 8085 microprocessor (A) 00H (C) 70H
executing program is given below: (B) 06H (D) 76H
Address 2020H
Data 24H 24. Consider a system consisting of a
IO/ ̅ Logic high microprocessor, memory, and peripheral
̅̅̅̅ Logic high devices connected by a common bus.
̅̅̅̅̅
W Logic Low During DMA data transfer, the
The assembly language instruction being microprocessor
executed is (A) Only reads from the bus
(A) IN 24H (C) OUT 24H (B) Only writes to the bus
(B) IN 20H (D) OUT 20H (C) Both reads from and writes to the
bus
IN-2008 (D) Neither reads from nor writes to the
21. A part of a program written for an 8085 bus
microprocessor is shown below. When
the program execution reaches LOOP2,
the value of register C will be

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 GATE QUESTION BANK Digital Circuits

IN-2010
25. In an 8085 processor, the main program Address us xt T0
calls the subroutine SUB1 given below. xt T1
rogrammable
When the program returns to the main ata us nterrupt
program after executing SUB1, the value controller
xt T
in the accumulator is T
Address Opcode Mnemonic TA
2000 3E 00 SUB1: MVIA,00h Assuming vectored interrupt, a correct
2002 CD 05 20 CALL SUB2 sequence of operations when a single
2005 3C SUB2: INR A external interrupt (Ext INT1) is received
2006 C9 RET will be :
(A) 00 (C) 02 (A) xt T1→ TA → Data Read → INT
(B) 01 (D) 03 (B) xt T1→ T → INTA → Data Read
(C) Ext INT1 → INT → INTA → Address
26. A 8-bit DAC is interfaced with a Write
microprocessor having 16 address lines (D) Ext INT1 → INT → ata ead →
(A0...A15) as shown in the adjoining Address Write
figure. A possible valid address for this
DAC is IN - 2015
2 line to d d 29. An ADC is interfaced with a
4 line ecoder microprocessor as shown in the figure. All
b
A a A signals have been indicated with typical
b
A a b Analog notations. Acquisition of one new sample
output
A ̅̅̅S b ̅̅̅S of the analog input signal by the
microprocessor Involves.
(A) 3000H (C) AFFFH
(B) 4FFFH (D) C000H Data Bus ata lines 0 to Data

Analog input
0 0Buffers

27. The subroutine SBX given below is ̅̅̅̅ nable

executed by an 8085 processor. The value A Address bu ers
Address
Decode
in the accumulator immediately after the Bus A Logic
Start
con ersion
execution of the subroutine will be: ̅̅̅̅̅
W ̅̅̅̅̅̅̅̅
nd o
SBX: MVI A, 99H ̅̅̅̅̅
T con ers on
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
ADI 11H icroprocessor A
MOV C, A (A) One READ cycle only
RET (B) One WRITE cycle only
(A) 00H (C) 99H (C) One WRITE cycle followed by one
(B) 11H (D) AAH READ cycle
(D) One READ cycle followed by one
IN-2014 WRITE cycle
28. A microprocessor accepts external
interrupts (Ext INT) through a
Programmable Interrupt Controller as
shown in the figure.

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 GATE QUESTION BANK Digital Circuits

Answer Keys & Explanations

ECE That is F8 F8 memory address is selected

1. [Ans. C] So LDA F8F8 [Load accumulator from the
Content of register content of memory location F8F8H]
MVI A, 45 A = 45 should be the instruction for data transfer
MOV B, A B = 45
STC CY =1 5. [Ans. A]
CMC CY =0 STA 1234H is stored as follows
RAR A = 22 1FFE Opcode of STA
XRA B A =22 ⊕ 45 = 1FFF 34 H
2000 12H
2. [Ans. B] After this 1234H will be loaded in the
Address bits should be as follows: address bus.
A A A A A A A A So the correct sequence of values at
0 0 1 0 1 1 0 1 A A are 1F, 1F, 20, 12
(and for A A the can be the 0 or 1)
2D00 2DFF (Range) 6. [Ans. B]
In an 8085 microprocessor, after
3. [Ans. C] performing the addition, result is stored
MVI A, The content in accumulator and if any carry (overflow
0000 0111
07 H o ‘A’ bit) is generated it updates flags.
The content
RLC 0000 1110
o ‘A’ 7. [Ans. D]
MOV B, The content Generally arithmetic or logical
0000 1110
A o ‘ ’ instructions update the data of
The content accumulator and flags. So, in the given
RLC 0001 1100
o ‘ ’ option only SBT BE H is arithmetic
The content instruction.
RLC 0011 1000
o ‘ ’ S H → Add the content o
ADD B accumulator with immediate data BE H
A 0000 1110 and store the result in accumulator.
+
B 0011 1000 8. [Ans. C]
0100 0110 A 00H oad accumulator b 00H
0010 0011 oop: A Add the content o
→ 23H
2 3 accumulator with content of C register
and store result in accumulator. This will
4. [Ans. D] continue till B register reaches to 004.
In this figure the chip select S and S DCRB
will be selected if the memory address JNZ LOOP
will be HLT
A A A A A A A A
So, repetitive addition of a number as
⏟1 1 1 1 ⏟1 0 0 0
8 many times will give the product of these
A A A A A A A A two numbers.
⏟1 1 1 1 ⏟1 0 0 0
8
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 GATE QUESTION BANK Digital Circuits

9. [Ans. D] POP H
A H DAD D
PUSH H
1 0 1 0 0 1 1 1 Normal call operation shown
cx
1 arr lag = 1
CALL SUB

0 1 0 0 1 1 1 1

4
RET

EE
10. [Ans. B] 14. [Ans. B]
Given, (SP) = 2700H To enable decoder
(PC) = 2100 H =1
(HL) = 0000H Output line 2 is selected
2100 H : DAD SP So = 010
(SP) + (HL) → (HL) A A A = 010
2700 H + 0000 H = 2700 H stored in HL =1 A A ̅ =1 A =1 A =0
pair A A A A A A A A
2101 H : PCHL : The content of HL are ⏟0 1 0 1 ⏟0 0 0 0
transferred to (PC) 5 0
A A A A A A A A
So now (PC) = 2700H and (SP) also
⏟0 0 0 0 ⏟ 0 0 0 0
unchanged 0 0
(PC) = 2700 H = 5000
(SP) = 2700 H
15. [Ans. A]
11. [Ans. D] 2000H XRA A → clear accumulator
XRA A A = 00 MVI B,
2001H → B = 04H
MVI B, F0H = 0 04H
SUB B A – B will go MVI A,
2003H → A= 03H
to accumulator 03H
00 – F0 = 10 → Rotate accumulation
2005H RAR to right A =
12. [Ans. D] 10000001
First of all content of PC is loaded into → Decrement B, B=
stack. i.e. address of next instruction to be 200 H DCR B
03
executed is loaded onto stack. i.e. SP is INZ → ump to 2005 when
decremented then PC is loaded by 200 H
2005 =0
address given in call instruction. 200 AH HLT
After 3 rotation
13. [Ans. C] A= 0 1 1 0 0 0 0 0
Call take 3 address locations. RET always = 0H
returns to LP + 3 location, this stored in
SP. So to return to LP + DISP + 3 we have
to add DISP to SP.

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 GATE QUESTION BANK Digital Circuits

16. [Ans. C] ̅ (Logic High): ̅ high indicates

LHLD instruction loads the value at that this is input/output operation.
memory location specified by the ̅̅̅̅ (Logic High): ̅̅̅̅ logic high indicates
immediate that read operation is inactive.
Value 2100 in H and L pair register ̅̅̅̅̅ (Logic Low): W
W ̅̅̅̅̅ logic low indicates
Value at 2100 will be stored in L register that write operation is active.
Value of 2100 will be stored in H register So, by observing all the operations the
appropriate instruction is OUT20H.
IN
17. [Ans. C] 21. [Ans. A]
4 4 10 4 4 Execution will go to Loop 2 when A
= 254 T contain 4H = 100 , at that time C
contains 63 H.
18. [Ans. A]
Since I/O device is memory mapped I/O 22. [Ans. B]
Memory related instructions will be Starting address 0800H, so last
used for data transfer address = 0800 + 7FF = 0FFFH.
1H 00 0H → load the address of
memory in HL pair 23. [Ans. A]
A → load the memory by content Last instruction is XRA A, so accumulator
of A contents will be 00

19. [Ans. A] 24. [Ans. C]

E.g. 01H positive number In DMA transfer of data between source
→ 0000 0001 After RAL and destination takes place without any
CY Accumulator involvement of microprocessor. During
0 0000 0010 or 00000011 both in read/write mode.
JNC is TRUE and again IN instruction will
load accumulator with same port address, 25. [Ans. B]
and microprocessor will go into infinite SUB 1: MVI A, 00H → A = 00H
loop. CALL SUB 2 → program will shift to SUB 2
Negative number → 1000 0000 after RAL address location
CY Accumulator SUB 2: INR A →A = 00H + 01H = 001H
1 0000 0001 or 00000000 RET → returned to main program
JNC is false and microprocessor will come The contents of Accumulation after
out from the loop. execution of the above SUB 2 is 01H
So, this program halts upon reading a
negative number. 26. [Ans. A]
To select 2-4 line decoder, A15 = 0
20. [Ans. D] To select the DAC, b2 should be active, i.e.
Address 2020H: The contents of lower A14 = 0 and A13 = 1.
and higher address lines are same i.e. Reset all address lines can be either 0 or 1.
20H. So, this indicates that the technique So, address can be
is I/O mapped I/O. 001x xxxx xxxx xxxx
Data 24H: This indicates that the content Out of four choices this is satisfied by
of accumulator is 24 H, which have to sent 3000 H only.
to I/O port.
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 GATE QUESTION BANK Digital Circuits

27. [Ans. D]
Instructions Content of register
MVI A, 99H A = 99
ADI 11H A = 99 + 11 = AAH
MOV C,A C = AAH

28. [Ans. B]
The correct sequence is external
interrupts occurs at PIC, then it is
transferred to microprocessor, then
interrupt is acknowledge and finally data
is read.

29. [Ans. C]

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