Aiwa - 6ZG 1 - 09 001 338 7n4
Aiwa - 6ZG 1 - 09 001 338 7n4
SERVICE MANUAL
VIDEO CD MECHANISM BASIC CD MECHANISM :3ZG-2 E2
TYPE
VZRNDM
VZRDM
YVZRNDM
TA
DA
2
DISASSEMBLY INSTRUCTIONS
1. How to replace PICK UP.
1) Open the TRAY. PICKUP
Push the stopper to arrow direction and release half of
the SHAFT SLED.
2) Turn GEAR MAIN CAM to the counterclockwise
(arrow “a”) direction, and lift up CD mechanism. (Fig-1)
3) Remove SHAFT SLED.
4) CD mechanism in down position, replace PICK UP.
5) Lift up CD mechanism (Fig-1), and Reassemble the
SHAFT SLED.
SHAFT SLED
STOPPER
a
FFC
Fig-2
3
3. The disassemble and reassemble the TRAY
3-1. Disassembling procedure.
1) Push the PLATE GEAR’S Boss at the bottom part of
CHAS MECHA strongly to the outside (arrow “b”
direction). (Fig-3)
b
(Confirm that TRAY appears a little in the front.)
2) Draw TRAY to the open position. BOSS
3) Remove FFC, and push the two LEVERS at both side of
the CHAS MECH to remove TRAY. (Fig-4)
TRAY
FFC
LEVER
Fig-3
LEVER
Fig-4
FFC
TRAY
LEVER TRY
Fig-5 Fig-6
4
4. How to reassemble the TURN TABLE. (Fig-7)
1) Push LEVER TT in the direction of “C”, and put in the
TURN TABLE 5CD. (Fig-7)
After reassembly, one of the TURN TABLE DISC
TRAY (can be either one of the five disc trays) must be
aligned with TURN TABLE 5CD. (Fig-8)
That is, having no gap difference between the TURN
TABLE 5CD and the TRAY 5CD.
ALIGN
5
ELECTRICAL MAIN PARTS LIST
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
IC C114 87-010-260-040 CAP,E 47-25 SME
C115 87-010-197-080 CAP, CHIP 0.01 DM
87-A21-381-040 C-IC,LA9235M C116 87-010-260-040 CAP,E 47-25 SME
87-A21-557-010 C-IC,LC78635E C117 87-010-197-080 CAP, CHIP 0.01 DM
8Z-ZJP-602-010 C-IC,UPD78016FGC-574 C118 87-010-263-040 CAP,E 100-10
87-017-760-080 IC,M51943BML
87-A20-602-040 C-IC,M5291FP C119 87-A11-567-080 C-CAP,S 0.01-50 K B
C123 87-010-197-080 CAP, CHIP 0.01 DM
87-A20-925-040 C-IC,BA05FP C124 87-010-401-040 CAP,E 1-50 SME
87-A20-905-040 C-IC,BA033FP C126 87-010-196-080 CHIP CAPACITOR,0.1-25
87-A21-513-040 C-IC,BA6998FP C130 87-010-196-080 CHIP CAPACITOR,0.1-25
87-A20-920-010 C-IC,CL680-D1
87-A20-975-040 C-IC,SN74LV74APW C132 87-010-405-040 CAP,E 10-50
C133 87-010-314-080 C-CAP,S 22P-50V
87-A20-921-040 C-IC,SN74LVU04APW C135 87-010-197-080 CAP, CHIP 0.01 DM
87-A20-962-040 C-IC,MSM54V16258B/BSL C140 87-010-322-080 C-CAP,S 100P-50 CH
84-ZG1-695-040 C-IC,LH5V2RN1 C194 87-010-197-080 CAP, CHIP 0.01 DM
87-A20-918-040 C-IC,SM5878AM
87-001-982-010 IC,TA7291S C195 87-010-260-040 CAP,E 47-25 SME
C201 87-016-669-080 C-CAP,S 0.1-25 K B
87-A20-974-040 C-IC,LC74781M-9017 C213 87-010-190-080 S CHIP F 0.01
C214 87-010-196-080 CHIP CAPACITOR,0.1-25
C216 87-010-322-080 C-CAP,S 100P-50 CH
TRANSISTOR
C217 87-010-322-080 C-CAP,S 100P-50 CH
87-026-609-080 TR,KTA1266GR C218 87-010-322-080 C-CAP,S 100P-50 CH
87-A30-076-080 C-TR,2SC3052F C219 87-010-322-080 C-CAP,S 100P-50 CH
89-327-125-080 CHIP TR,2SC2712GR C220 87-010-263-040 CAP,E 100-10
87-026-237-080 CHIP-TR,DTC124XK C221 87-010-190-080 S CHIP F 0.01
87-026-231-080 CHIP-TRANSISTER,DTA124XK
C242 87-010-318-080 C-CAP,S 47P-50 CH
87-A30-117-010 TR,2SA1357 C301 87-016-251-040 CAP,E 220-16 SMG
89-421-722-380 TR,2SD2172V/W C302 87-012-140-080 CAP 470P
89-320-011-080 TR,2SC2001 (15W) C303 87-010-178-080 CHIP CAP 1000P
87-026-223-080 TR,DTC143TK C304 87-010-384-040 CAP,E 100-25 SME
87-A30-031-010 P-TR,PT380F
C305 87-010-982-040 CAP,E 33-25 GAS
87-026-580-080 C-TR,DTA123JK C306 87-010-112-040 CAP,E 100-16
87-026-470-080 TR,HN1C03F (0.3W) C307 87-010-196-080 CHIP CAPACITOR,0.1-25
89-111-625-080 TR,2SA1162 (0.15W) C308 87-010-263-040 CAP,E 100-10
87-026-608-080 C-TR,DTC 123 JK<VZRDM> C309 87-010-196-080 CHIP CAPACITOR,0.1-25
C13 87-010-321-080 C-CAP,S 82P (J) C503 87-010-197-080 CAP, CHIP 0.01 DM
C15 87-010-197-080 CAP, CHIP 0.01 DM C509 87-016-669-080 C-CAP,S 0.1-25 K B
C16 87-010-260-040 CAP,E 47-25 SME C511 87-010-196-080 CHIP CAPACITOR,0.1-25
C65 87-010-196-080 CHIP CAPACITOR,0.1-25 C512 87-010-197-080 CAP, CHIP 0.01 DM
C101 87-010-992-080 C-CAP,S 0.047-25 B C513 87-010-197-080 CAP, CHIP 0.01 DM
C102 87-010-401-040 CAP,E 1-50 SME C514 87-010-197-080 CAP, CHIP 0.01 DM
C103 87-010-196-080 CHIP CAPACITOR,0.1-25 C518 87-010-322-080 C-CAP,S 100P-50 CH
C104 87-010-196-080 CHIP CAPACITOR,0.1-25 C519 87-012-145-080 CAP, CHIP S 270P CH
C105 87-010-260-040 CAP,E 47-25 SME C520 87-012-157-080 C-CAP,S 330P-50 CH
C106 87-010-322-080 C-CAP,S 100P-50 CH C521 87-012-154-080 C-CAP,S 150P-50 CH
6
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
C528 87-010-197-080 CAP, CHIP 0.01 DM !PR350 87-A90-246-080 PROTECTOR,0.25A 60 4
C529 87-010-197-080 CAP, CHIP 0.01 DM R350 88-130-220-080 RES,22-1/4 W J
C530 87-010-197-080 CAP, CHIP 0.01 DM R507 87-A00-408-080 C-RES,S 2K-1/10W D
C531 87-010-197-080 CAP, CHIP 0.01 DM S353 87-036-109-010 PUSH SWITCH
C532 87-010-374-040 CAP,E 47-10 SW351 87-036-109-010 PUSH SWITCH
7
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
TRANSISTOR ILLUSTRATION
C1
C B1
E1
E1
B B2
ECB E ECB C2
2SC2001 2SA1162 2SA1357 HN1C03F
2SD2172 2SC2712
KTA1266 DTA123JK
DTA124XK
DTC124XK
DTC143TK
2SC3052F
DTC123JK
8
BLOCK DIAGRAM
VZRDM MODEL
9 10
WIRING-1 (VCD: COMPONENT SIDE)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
11 12
WIRING-2 (VCD: CONDUCTOR SIDE)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
KSS-213F
D
VZRDM MODEL
13 14
SCHEMATIC DIAGRAM-1 (VCD: 1/2)
15 16
SCHEMATIC DIAGRAM-2 (VCD: 2/2)
17 18
WIRING-3 (T-T/VIDEO SW/CD MOTOR) WAVE FORM
1 2 3 4 5 6 7 1 CN231 @ (O-DISH-REV) VOLT/DIV: 500mV 6 IC501 Pin 86 DA XCK VOLT/DIV: 1V
TIME/DIV: 200mS 16.93MHz TIME/DIV: 20nS
2 CN231 ! (O-DISH-FWD)
1.6Vp-p
1
2
B
1.6Vp-p
0
D
F 1.75Vp-p
H
1.0Vp-p
K
19 20
0 IC504 Pin
___________
º UCAS
___________
VOLT/DIV: 1V @ ____________
IC501 Pin 101 HSync VOLT/DIV: 1V
(Pin ⁄ LCAS) TIME/DIV: 2µS PAL TIME/DIV: 20µS
! IC501 Pin 93
____________
VSync VOLT/DIV: 1V
____________
IC501 Pin 101 HSync VOLT/DIV: 1V
NTSC TIME/DIV: 5mS NTSC TIME/DIV: 20µS
____________
IC501 Pin 93 VSync VOLT/DIV: 1V
PAL TIME/DIV: 5mS
21
IC DESCRIPTION
IC, CL680
Pin No. Pin Name I/O Description
1 NC — No connection.
2 VSS — GND.
3 CD BCK I Bit clock input from CD DSP.
4 CD DATA I Data input from CD DSP.
5 CD LRCK I LRCK input from CD DSP.
6 CD C2PO I C2 pointer input from CD DSP.
7-9 NC — No connection.
10-15 MD0-MD5 I/O DRAM/ROM interface. (DATA)
16 VSS — Ground.
17 MD6 I/O DRAM/ROM interface. (DATA)
18 VDD3 — Power supply 3.3V.
19 MD7 I/O DRAM/ROM interface. (DATA)
20 VSS — Ground.
21 MD8 I/O DRAM/ROM interface. (DATA)
22 VDD3 — Power supply 3.3V.
23-29 MD9-MD15 I/O DRAM/ROM interface. (DATA)
30-36 NC — No connection.
________
37 MCE — ROM chip enable.
__________
38 MWE O DRAM write enable.
39 VSS — Ground.
________
40 CAS O DRAM/ROM interface.
41 VDD3 — Power supply 3.3V.
___________
42 RASO O
___________ DRAM/ROM interface.
43 RASI O
44-46 MA10-MA8 O DRAM/ROM interface. (Address)
47 VSS — Ground.
48 MA7 O DRAM/ROM interface. (Address)
49 VDD3 — Power supply 3.3V.
50-52 MA6-MA4 O DRAM/ROM interface. (Address)
53 VSS — Ground.
54 MA3 O DRAM/ROM interface. (Address)
55 VDD3 — Power supply 3.3V.
56-58 MA2-MA0 O DRAM/ROM interface. (Address)
59 PGIO7 I/O Programmable I/O.
______________
60 RESET I Reset input.
61 VDD MAX IN — Power supply - VDDMAX. (5.0V)
62-64 NC — No connection.
65 AGND DAC — Analog ground.
66 A DAC — Analog power supply (DAC) : 3.3V.
67 COMP OUT O Composite out.
68 AGND DAC — Analog ground.
22
Pin No. Pin Name I/O Description
69 Y OUT O Video signal “Y” OUT.
70 AVDD DAC — Analog power supply (DAC) 3.3V.
71 AGND DAC — Analog ground.
72 R REF I Reference resistor input.
73 V REF I Voltage reference input.
74 AVDD DAC — Analog power supply (DAC) : 3.3V.
75 C OUT O Video signal “C” out.
76 AGND DAC — Analog ground.
77-79 CLK SEL0-2 I Clock selection input.
80 VSS — Ground.
81 CLK SEL3 I Clock selection input.
82 VDD3 — Power supply 3.3V.
83, 84 CLK SEL4, 5 I Clock selection input.
85 AGND PLL — Analog ground.
86 DA XCK I DA XCK (16.933MHz) input.
87 AVDD PLL — Analog power supply 3.3V.
88 DA EMP O DAC-emphasis output.
89, 90 PGIO5, O6 I/O
91 PGIO0 I/O Programmable I/O.
92 PGIO8 I/O
______________ ______________ ______________ ______________
93 VSYNC/CSYNC O VSYNC/CSYNC output.
94 AVDD PLL — Analog power supply (PLL) 3.3V.
95 VID_DAC_CK O Video DAC clock.
96 PROC_CK O Processor clock.
97 AUD_XCK O Audio XCK.
98 AGND PLL — Analog ground.
99 VSS — Ground.
100 NC — No connection.
______________ ______________
101 HSYNC O HSYNC output.
102 VDD3 — Power supply 3.3V.
103 VCK OUT O VCK out.
104 VSS — Ground.
105 GCK I Global clock signal input. (42.3MHz)
106 VCK I Video clock signal input. (27.0MHz)
107 GCK OUT O Global clock signal output. (27.0MHz)
108 DA LRCK O DAC-LRCK output.
109 VDD MAX OUT — Power supply (VDD MAX) : 5.0V.
110 DA DATA O DAC-PCM data output.
111 DA BCK O DAC-BIT clock output.
112 HD OUT O Micon interface. (Data out)
113 HRDY O Micon interface. (Host ready)
23
Pin No. Pin Name I/O Description
__________
114 HINT O Micon interface. (Host interrupt)
115 CDG SCK I CD-G serial clock input.
116 VSS — Ground.
117 HCK I Micon interface. (Host clock)
118 VDD3 — Power supply 3.3V.
119 HD IN I Micon interface. (Host data in)
120 VDD3 — Power supply 3.3V.
121 HSEL I Micon interface. (Host select in)
122 CDG DATA I CD-G data input.
123 CDG VFSY I CD-G VFSY input.
124 CDG SOSI I CD-G SOSI input.
125 DSP-XCK O DSP-XCK output.
126-128 NC — No connection.
24
IC, LC78635E
Pin No. Pin Name I/O Description
1 PDO1 O Internal VCO control phase comparator output pin. (Pull down)
Internal VCO control phase comparator output pin.
2 PDO2 O
OFF for rough servo, ON for phase servo. (Pull down)
3 VVSS — Internal VCO ground pin.
4 PCKIST I PDO output current adjustment resistor connection pin.
5 VVDD — Internal VCO power supply pin.
6 FR I VCO frequency range adjustment resistor connection pin. (Pull up)
7 HFL I Mirror detection signal input pin.
8 SLCIST I SLCO output current adjustment resistor connection pin.
9 SLCO O Control output.
10 EFMIN I EFM signal input pin.
11 JITTV O Jitter detection monitor pin.
12 JITTC O Jitter detection adjustment pin. (Pull down)
13 BH I BH signal input pin. (Connected to GND)
14 PH (RFENV) I PH signal or RFENV signal input pin.
15 FE I FE signal input pin.
16 TE I TE signal input pin.
17 VREF I VREF input pin.
18 ADAVDD — Servo A/D, D/A power supply pin.
19 ADAVSS — Servo A/D, D/A ground pin.
20 PHREF O PH reference output pin.
21 BHREF O BH reference output pin.
22 TBLO O Tracking balance output pin.
23 TDO O Tracking control output pin.
24 FDO O Focus control output pin.
25 SPDO O Spindle control output pin.
26 SLDO O Thread control output pin.
27 FG I/O FG signal input pin. (Connected to GND)
28 LASER O Laser ON/OFF control pin.
29 CONT1 I/O General-purpose input/output pin 1. (Connected to GND)
30 CONT2 I/O General-purpose input/output pin 2. (Connected to GND)
31 CONT3 I/O General-purpose input/output pin 3.
32 CONT4 I/O General-purpose input/output pin 4.
33 CONT5 I/O General-purpose input/output pin 5. (Not connected)
EFM data playback clock monitor pin. Average 4.3218MHz when the phase is locked.
34 PCK O
(Not connected)
35 C2F O C2 flag output pin.
36 VDD — Digital power supply pin.
37 DOUT O Digital out output pin. (EIAJ format)
Output pin for the 7.35kHz synchronization signal divided from the crystal oscillator.
38 FSX O
(Not connected)
25
Pin No. Pin Name I/O Description
39 EFLG O C1, C2 error correction monitor pin. (Not connected)
40 TEST I Test input pin. (Connected to GND)
Emphasis pin. Which becomes an input pin after reset and can be controlled externally.
41 EMPH I/O
This becomes an emphasis monitor pin under control by command.
42 MUTEL O L channel mute output pin. (Not connected)
43 MUTER O R channel mute output pin. (Not connected)
44 LVDD — L channel power supply pin.
45 LCHO O L channel output pin. (Not connected)
46 LVSS — L channel ground pin.
47 RVSS — R channel ground pin.
48 RCHO O R channel output pin. (Not connected)
49 RVDD — R channel power supply pin.
50 XVDD — Crystal oscillator power supply pin.
51 XIN I
Connections for a 16.9344MHz crystal oscillator pin.
52 XOUT O
53 XVSS — Crystal oscillator ground pin.
54 ASLRCK I L/R clock input pin. (Connected to GND)
55 ASDACK I Bit clock input pin. (Connected to GND)
56 ASDFIN I L/R channel data input pin. (Connected to GND)
57 LRSY O L/R clock output pin.
58 DATACK O Bit clock output pin.
59 DATA O L/R channel data output pin.
60 16M O 16.9344MHz output pin.
Subcode frame synchronization signal output pin. This signal falls when the subcode is
61 SFSY O
in the standby state.
62 SBSY O Subcode clock synchronization signal output pin.
63 PW O Subcode P, Q, R, S, T, U and W output pin.
64 SBCK I Subcode readout clock input pin.
65 CE I Chip enable signal input pin.
66 CL I Data transfer clock input pin.
67 DI I Data input pin.
68 DO O Data output pin.
69 INT O Interruption signal output pin. (Not connected)
70 WRQ O Interruption signal output pin.
71 RES I Reset input pin. This pin must be set low briefly after power is first applied.
72 DRF O Focus ON detect pin.
73 VDD5V — Microprocessor interface power supply.
74 VSS — Digital ground pin.
75 CONT6 I/O General-purpose input/output pin 6.
76 CONT7 I/O General-purpose input/output pin 7.
Rough servo/phase control automatic switching monitor output pin.
77 V/P O
“H” for rough servo and “L” for phase servo. (Not connected)
26
Pin No. Pin Name I/O Description
Synchronization signal detection output pin.
78 FSEQ O Outputs a high level when the synchronization signal detected from the EFM signal
and the internally generated synchronization signal agree.
Defect pin. Which becomes an input pin after reset and can be controlled externally.
79 DEFECT I/O
This becomes the defect monitor pin under control by command. (Not connected)
80 EFMO O EFM signal output pin. (Not connected)
27
IC, LC74781M
Pin No. Pin Name I/O Description
1 VSS1 — GND connection terminal. (Digital ground terminal).
2 Xtal IN I External X’tal and capacitor for internal sync generator, or the external clock are
3 Xtal OUT O connected to this terminal. (2fsc or 4fsc).
Either the external clock input mode or the X’tal generator mode is selected by this
4 CTRL1 I
selector terminal. L: X’tal generator mode, H: External clock input.
Blank signal (character and the green ORed signal) is output from this terminal.
________
5 BLANK O (MODE 0: composite sync signal is output at H.) When reset (RST terminal = L), the
X’tal clock signal is output. (It is not output when reset by the reset command).
6 OSC IN I External coil and capacitor for the character output dot clock generator are connected
7 OSC OUT O to this terminal.
The character signal is output from this terminal. (MOD 0: when H, the external sync
signal identification signal is output from this terminal. This output signal tells whether
8 CHARA O the external sync signal is present or not. When external sync signal is present, H is
________
output.) When reset (RST terminal = L), the dot clock signal (LC oscillator) is output.
(It is not output when reset by the reset command).
______ Enable signal for the serial data input is input to this terminal. The serial data input is
9 CS I
enabled at L. Pull-up resistor is built-in. (Hysteresis input).
Clock of the serial data input is input to this terminal. Pull-up resistor is built-in.
10 SCLK I
(Hysteresis input).
11 SIN I Serial data input terminal. Pull-up resistor is built-in. (Hysteresis input).
12 VDD2 — Power supply for the composite video signal level adjustment. (Analog power supply).
13 CV OUT O Composite video signal output terminal.
14 NC — Connected to GND or not connected.
15 CV IN I Composite video signal input terminal.
16 VDD1 — Power supply (+5V digital power supply).
Video signal for the internal sync separator circuit is input to this terminal. (When the
17 SYN IN I internal sync separator circuit is not used, the horizontal sync signal or composite sync
signal is input to this terminal).
18 SEP C — Internal sync separator circuit bias voltage monitoring terminal.
The composite sync output signal of the internal sync separator circuit is output from
O this terminal. (H: MOD 1. H: during internal sync mode. L: during external sync
19 SEP OUT
mode.) (When internal sync separator circuit is not used, the SYN IN input signal is
output from this terminal).
The output signal of the SEP OUT terminal is integrated so that the vertical sync signal
is input to this terminal. An integrator circuit must be connected between the SEP
20 SEP IN I
OUT terminal and this terminal. When this terminal is not used, it must be connected
to VDD1.
When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting
has priority. When L, the NTSC system is selected after resetting. Selection of either
21 CTRL2 I
NTSC or PAL or PAL-M or PAL-N system by the command becomes effective. H:
PAL-M system.
28
Pin No. Pin Name I/O Description
______________
Controls whether or not to input the VSYNC signal to the SEPIN input. L: to input the
22 CTRL3 I ______________ ______________
VSYNC signal. H: not to input the VSYNC signal.
________
23 RST I System reset input terminal. Pull-up resistor is built-in. (Hysteresis input).
24 VDD1 — Power supply. (+5V digital power supply).
29
IC, µPD78016FGC
Pin No. Pin Name I/O Description
1 RBPLS O RADIAL BALANCE PLUS.
2 AMUTE O AUDIO ANALOG MUTE (H=MUTE ON).
3 GFS I GFS.
4 XVCDMD I AUDIO/VIDEO CD MODE (L=VCD=SPINDLE GAIN UP).
5 MD2 O DOUT MUTE CONT.
6 EMPH I EMPHASIS.
7 SQSO I SQDATA FROM CD.
8 SQCK O SQCLK TO CD.
9 VSS — GND.
10 SWNT I SW TV OUT MODE (L=NTSC).
11 SWAUTO I SW TV OUT MODE (L=NTSC/PAL AUTO).
12 SWPAL I SW TV OUT MODE (L=PAL).
13 EMERG I POWER EMERGENCY STOP (L*3sec=STOP).
14 NC — Nou used.
15 LPCSEL I “LPC ON/OFF (H=ON, NORMAL)”.
16 NC — Nou used.
17 LOCK O GFS (FRAME SYNC) LOCK (NO USE=H).
18 DMUTE O DIGITAL DATA OUT MUTE.
19 SENS I DSP SENS1 FROM CD.
20 XCDRST O CD RESET.
21 DATA O DATA TO CD.
22 XLAT O XLT TO CD.
23 CLOK O CLK TO CD.
24 VSS — GND.
25 FOK I FOCUS OK.
26 SENS2 I SSP SENS2 FROM CD.
27 XBUSY I/O READY/BUSY I/O TO HOST OD.
28 NC —
29 NC — Nou used.
30 NC —
31 TST0 I/O
32 TST1 I/O
CHECK LAND.
33 TST2 I/O
34 TST3 I/O
35 RESET I RESET.
36 HRDY I HRDY FROM CL680.
37 XHINT I HINT FROM CL680.
38 NC — Nou used.
39 SCOR I SCOR FROM CD.
40 VDD — 5.0VDD.
41 XO O 8.0MHz CERALOCK.
30
Pin No. Pin Name I/O Description
42 XI I 8.0MHz CERALOCK.
43 VSS — GND.
44 XT2 — Nou used.
45 XT1 I 5.0VDD.
46 AVSS — GND.
47 XMPGRST O MPEG BLOCK IC RESET.
48 HSEL O ADDRESS/DATA SEL TO CL680.
49 INLSW I INSIDE LIMIT SW .
50 NC — Nou used.
51 OSDXCS O OSD CHIP SELECT.
52 ABSEL I CXA1992A/B SELECT (L=CXA1992A).
53 CLVSEL I CLV MODE SELECT (H=CLV-N).
54 AADSEL I AUTO ADJUST SELECT (H=AUTO ON).
55 AVDD —
5.0VDD.
56 AVREF —
57 HDOUT I HD-OUT FROM CL680.
58 HDIN O HD-IN TO CL680.
59 HCK O HCK TO CL680.
60 OSDDATA O OSD DATA.
61 OSDCLK O OSD CLOCK.
62 COMMAND I COMMAND FROM HOST.
63 STATUS O STATUS TO HOST.
64 SCK I SCK FROM HOST.
31
IC, SM5878M
Pin No. Pin Name I/O Description
MODE = H: Soft mute ON/OFF terminal. (Mute at H).
1 MUTE I
MODE = L: Attenuator level DOWN/UP terminal. (DOWN at H).
2 DEEM I De-emphasis ON/OFF terminal. (De-emphasis ON at H).
3 CKO O Oscillator clock output. (16.9344 MHz).
4 DVSS — Digital VSS terminal.
5 BCKI I Bit clock input terminal.
6 DI I Serial data input terminal.
7 DVDD — Digital VDD terminal.
8 LRCI I Sample rate clock (fs) input terminal. (H = L ch/L = R ch).
9 TSTN I Test input. (“H” or open during normal operation)
10 TO1 O Test output 1. (Normally low level output).
11 AVDDL — Analog VDD terminal. (For L ch).
12 LO O Left channel analog output terminal.
13 AVSS — Analog VSS terminal.
14 RO O Right channel analog output terminal.
15 AVDDR — Analog VDD terminal. (For R ch).
16 MUTEO O Infinity zero detection output.
17 XVDD — X’tal system VDD terminal.
18 XTI I X’tal oscillator terminal. (Or external clock input terminal of 16.9344 MHz).
19 XTO O X’tal oscillator terminal.
20 XVSS — X’tal system VSS terminal.
21 DS I Double-speed/normal playback selection. (Double-speed at H).
22 RSTN I Reset terminal. (Reset at L).
23 MODE I Soft mute/Attenuator mode selection. (Soft mute at H).
24 ATCK I Attenuator level setup clock (Ignored when MODE = H).
32
IC BLOCK DIAGRAM
IC, SN74LV74APW IC, BA6998FP
IC, TA7291S
IC, M5291FP
PROTECTOR
CIRCUIT
Switch emitter Peak currect (TSD)
OSC detection
BRAKE
IC, LA9235M : HI IMPEDANCE
NOTE : INPUT “H” ACTIVE
33
MECHANICAL EXPLODED VIEW 1/1
A 10
A
9 11
13
12
14
45
E
16
42 17
19 18
15
20
P.C.B (AZA-4)
P.C.B
22
8 21
23
7 24
6
D
5
4 3
2
B
26
40 25
28
33
1 34 41
35 29
36 30
P.C.B (AZA-1) 31
27
37 32 43
D C
38
P.C.B 39
3ZG-2 E2
CUSH CD A
44
34
MECHANICAL PARTS LIST 1/1
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
1 86-ZG1-001-410 TRAY,5CD 26 86-ZG1-210-110 SLIDER,CAM R(*)
2 84-ZG1-267-010 PULLEY,LOAD MO 8 27 87-045-305-010 MOTOR, RF-500TB DC-5V (2MA)
3 87-A90-036-010 MOT ASSY,RF-300CA-11 28 84-ZG2-228-010 PULLEY,MOT
4 86-ZG1-228-110 GEAR,TT-B 29 83-ZG3-211-010 PLATE,DISC
5 86-ZG1-227-110 GEAR,TT-A 30 83-ZG3-604-010 RING,MAG 2
35
CD MECHANISM EXPLODED VIEW 1/1 (3ZG-2E2)
3
1
A
6 M21
SW1
5
P.C.B
6 83-ZG2-253-010 SHAFT,SLIDE 5
A 87-261-032-210 V+2-3
36
REFERENCE NAME LIST
ELECTRICAL SECTION MECHANICAL SECTION
DESCRIPTION REFERENCE NAME DESCRIPTION REFERENCE NAME
WHL WHEEL
WORM-WHL WORM-WHEEL
37
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