INTEL 8255 PPI MPMC

5th Sem Sec A E&IE

 FEATURES
PPI (Programmable Peripheral Interface)
It is an I/O port chip used for interfacing I/O devices with microprocessor
It is used to interface to the keyboard and a parallel printer port in PCs (usually
as part of an integrated chipset).
Requires insertion of wait states if used with a microprocessor using higher that
an 8 MHz clock.
PIN DIAGRAM 0F 8255
• PPI has is a 40 pin
DIP IC that has 24
pins for I/O that
are
programmable in
groups of 12 pins
and has three
distinct modes of
operation.
FUNCTION OF PINS
Data bus(D0‐D7):These are 8‐bit bi‐directional
buses, connected to 8086 data bus for
transferring data.
𝑪𝑺: This is Active Low signal. When it is low, then
data is transfer from 8085.
𝑹𝑫: This is Active Low signal, when it is Low read
operation will be start.
𝑾𝑹Write: This is Active Low signal, when it is Low
Write operation will be start.
 CONT..
Address (A0‐A1):This is used to select the ports as follows:

 (A2 to A15 can be Don’t care; or as per interfacing scheme employed by the designer)

RESET: This is used to reset the device. That means clear control
registers.
PA0‐PA7:It is the 8‐bit bi‐directional I/O pins used to send the
data to peripheral or to receive the data from peripheral.
CONT..
PB0‐PB7:Similar to PA
PC0‐PC7:This is also 8‐bit bidirectional I/O
pins. These lines are divided into two
groups.
 1. PC0 to PC3(Lower Groups)
 2. PC4 to PC7 (Higher groups)

Vcc and GND- Power supply

ARCHITECTURE
CONT..
Data Bus buffer:
 It is a 8‐bit bidirectional Data bus. It is used to interface between
8255 data bus with system bus. The internal data bus and Outer
pins D0‐D7 pins are connected in internally. The direction of data
buffer is decided by Read/Control Logic.

Read/Write Control Logic (RWCL):

 This is getting the input signals from control bus and Address bus.
Control signal are RD and WR.
 Address signals are A0,A1,and CS.
 8255 operation is enabled or disabled by CS.
CONT..
Group A and Group B control:
 Group A and B get the Control Signal from RWCL and send the command to the individual
control blocks.
 Group A send the control signal to port A and Port C (Upper) PC7‐PC4.
 Group B send the control signal to port B and Port C (Lower) PC3‐PC0.

PORT A:
 This is a 8‐bit buffered I/O latch.
 It can be programmed by mode 0 , mode 1, mode 2 .

PORT B:
 This is a 8‐bit buffer I/O latch.
 It can be programmed by mode 0 and mode 1.

PORT C:
 This is a 8‐bit Unlatched buffer Input and an Output latch.
 It is split into two parts, Port C Upper and Port C Lower.
 It can be programmed by bit set/reset operation.
 MODES OF OPERATION
D7 D6 D5 D4 D3 D2 D1 D0

Control Word Register (CWR)

0= BSR
1=I/O MODE

• Two modes- Bit Set Reset (BSR) mode and Input/ Output
(I/O) mode.
• It depends on the value of the D7 bit of the Control Word
Register.
BIT SET/RESET MODE
• Any one of the 8‐bits of PORT C can be Set or Reset depending upon the select bits on control
word register.

Example:
PORT C BIT
To Set PC3, control register will D3 D2 D1 #

be 0XXX0111. 0 0 0 0
To reset PC4, control register 0 0 1 1

will be 0XXX1000. 0 1 0 2
0 1 1 3
To set the 5th bit of Port C (LED)
(X is a don’t care). 00001001=09h 1 0 0 4

MVI A, 09 1 0 1 5
OUT 43H 1 1 0 6
* Here 43H is the 8-bit port 1 1 1 7
address of 8255 CWR
 I/O MODE
3 types of I/O modes are there, mode0, mode1 and mode2.

A
MODE 0 (SIMPLE INPUT / OUTPUT)
In this mode , two 8 bit ports (port A and port B)
and two 4 bit ports(port C upper and port C
lower) are available for I/O operations.
Features:
 Any port can be used as an input or output port.
 Ports do not have Handshake or interrupt capability.
MODE 1 (STROBED I/O MODE)
▪Two groups‐group A and group B are available for
strobed data transfer.
▪Each group contains one 8‐bit data I/O port and one 4
bit control port.
▪The 8 bit data port can be either used as input or output
port.
▪Out of 8 bit port C, PC3 to PC5 are used to generate
control signals for port A and PC0 to PC2 are used to
generate control signals for port B.
▪The lines PC6 and PC7 may be used as independent I/O
lines.
MODE 2 (STROBED BI‐DIRECTIONAL
I/O MODE)
• This mode allows bidirectional data transfer
over a single 8‐bit data bus (port A) using
handshake signals.
 Port A is working as 8‐bit bidirectional.
 5 bit control port PC3‐PC7 is used for generating/accepting
handshaking signals of port A.
 Here, port B and three lines of port C (PC2‐PC0) may be
used in either simple I/O mode or strobed mode.
 PC0‐PC7 is set or reset as per the status of D0 of CWR.
 HANDSHAKING SIGNALS
Handshaking signals are dedicated signals to coordinate data transfer
between two devices with different speeds. The following are the
commonly used handshaking signals:
STB (Strobe Input): This signal is generated by a peripheral device that
it has transmitted a byte of data.
IBF (Input buffer full): This signal is an acknowledgment by the 8255 to
indicate that the input latch has received the data byte.
OBF(Output Buffer Full): This is an output signal that goes low when the
microprocessor writes data into the output latch of the 8255.
ACK (Acknowledge): This is an input signal from a peripheral that must
output a low when the peripheral receives the data from the 8255
ports.
INTE: An internal flip-flop used to enable or disable the generation of
INTR.
PORT A AS INPUT PORT IN MODE 1
PORT A AS OUTPUT PORT IN MODE 1
PORT A IN MODE 2
PORT C AS CONTROL SIGNALS
CONT..
Port C pins act as handshake signals, when Port
A and Port B are configured for any mode other
than Mode 0.

Port A in Mode 2 and Port B in Mode 1 is

possible, as it needs only 5+3 = 8 handshake
signals

After Reset of 8255, Port A , Port B , and Port C

are configured for Mode 0 operation as input
ports.
CONT..
PC 2-0 are used as handshake signals by Port B when
configured in Mode 1. This is immaterial whether Port B
is configured as i/p or o/p port.

PC 5-3 are used as handshake signals by Port A when

configured as i/p port in Mode 1.

PC 7,6,3 are used as handshake signals by Port A when

configured as o/p port in Mode 1.

PC 7-3 are used as handshake signals by Port A when

configured in Mode 2.
CONT..
Port A can work in Mode 0, Mode 1, or Mode 2
Port B can work in Mode 0, or Mode 1
Port C can work in Mode 0 only, if at all

Port A, Port B and Port C can work in Mode 0

Port A and Port B can work in Mode 1
Only Port A can work in Mode 2
EXAMPLE 1
Configure Port A as input in Mode 0, Port B as output in
mode 0, Port C (Lower) as output and Port C (Upper) as
input ports.

1 0 0 1 1 0 0 0 = 98H MVI A, 98H

OUT 43H
EXAMPLE 2
Configure Port A as input in Mode 1, Port B as
output in mode 1, Port C 7-8 as input ports.
1 0 1 1 1 1 0 X
IO Mode PA is Mode 1 PA as i/p PCU as i/p PB Mode 1 PB as o/p PCL

(PC5-0 are handshake lines, some i/p lines and others o/p.
So they are shown as X)

CW= BC or BD

MVI A, BC
OUT 43H
EXAMPLE 3
Configure Port A in Mode 2, Port B as o/p in
mode 1. (PC5-0 are handshake lines for Port A
and PC2-0 are handshake signals for port B).

1 1 0 X X 1 0 X = C4H / C5H
 EXAMPLE 4
Reset to 0 bit 6 of Port C .
0 X X X 1 1 0 0 = 0CH

• Set to 1 bit 4 of Port C

0 X X X 1 0 0 1 = 09H,…
 Assume Port Address as:
Port A: FC H

LED DISPLAY Port B: FD H

Port C: FE H
Port D: FF H

Let mode of operation be IO Mode and all ports as output mode in

Mode 0
1 0 0 0 0 0 0 0
IO Mode PA is Mode 0 PA as o/p PCU as o/p PB Mode 0 PB as o/p PCL as o/p

=80 H (All ports of 8255 in mode 0 output mo

MVI A, 80 H
OUT FF H MVI A, 00
START: MVI A, FF(=11111111) OUT FC;
OUT FC; addr port A CALL DELAY
CALL DELAY JMP START
ROLLING/ FLASHING DISPLAY
PROGRAM (FLASHING)
MVI A, 80 H
OUT 43 H
START: MVI A, FF
OUT 40; a
OUT 41; B
OUT 42; C
CALL DELAY
MVI A, 00
OUT 40
OUT 41
OUT 42
CALL DELAY
JMP START
PROGRAM (ROLLING)
P7 P6 P5 P4 P3 P2 P1 P0 8-BIT VALUE

1 0 0 0 0 0 0 0 80H

0 1 0 0 0 0 0 0 40H

0 0 1 0 0 0 0 0 20H

0 0 0 1 0 0 0 0 10H

0 0 0 0 1 0 0 0 08H

0 0 0 0 0 1 0 0 04H

0 0 0 0 0 0 1 0 02H

0 0 0 0 0 0 0 1 01H
ROLLING 2
P7 P6 P5 P4 P3 P2 P1 P0 8-BIT VALUE

1 0 0 0 0 0 0 0 80H

1 1 0 0 0 0 0 0 C0H

1 1 1 0 0 0 0 0 E0H

1 1 1 1 0 0 0 0 F0H

1 1 1 1 1 0 0 0 F8H

1 1 1 1 1 1 0 0 FCH

1 1 1 1 1 1 1 0 FEH

1 1 1 1 1 1 1 1 FFH
MVI A, 80 H Program
OUT 43 H
MVI A,08
START: MVI A, 80
OUT 40
OUT 40
CALL DELAY
CALL DELAY MVI A, 04
MVI A, 40; PATTERN DATA OUT 40
OUT 40 ; ADDR CALL DELAY
CALL DELAY MVI A, 02
OUT 40
MVI A, 20
MVI A, 01
OUT 40
OUT 40
CALL DELAY CALL DELAY
MVI A, 10 JMP START
OUT 40
SSD
For SSD use 7447 BCD to SSD converter
For flashing display: 9 (flash)
For rolling 0→1→…..→9
END OF LECTURE