ALC4050

(PN: ALC4050-VA1-CG)

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AUDIO CODEC WITH e nt USB
有
TO 限
I2S AUDIO
f i d HARDWARE
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CONTROLLER n AND
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RT 奈克 NOISE 瑟CANCELLATION

杭州 0730
0 1 9 DATASHEET
2
Rev. 1.2
13 May 2019
Track ID: JATR-8275-15

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
 ALC4050
Datasheet

COPYRIGHT
©2019 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark, of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek

or 司
ALC4050 Audio Codec.

f
Though every effort has been made to ensure that this document is current and accurate, more information

l
t i a 限 公
may have become available subsequent to the production of this guide. In that event, please contact your

n
Realtek representative for additional information that may help in the development process.

i d e 技 有
f
ELECTROSTATIC DISCHARGE (ESD) WARNING

c o n 科
This product can be damaged by Electrostatic Discharge (ESD). When handling, care must be taken.
斯
RTK 奈克瑟
Damage due to inappropriate handling is not covered by warranty.
Do not open the protective conductive packaging until you have read the following, and are at an
approved anti-static workstation.
•
• 杭州 0730
Use an approved anti-static mat to cover your work surface

9
Use a conductive wrist strap attached to a good earth ground
•
2 0 1
Always discharge yourself by touching a grounded bare metal surface or approved anti-static mat
before picking up an ESD-sensitive electronic component
• If working on a prototyping board, use a soldering iron or station that is marked as ESD-safe
• Always disconnect the microcontroller from the prototyping board when it is being worked on

REVISION HISTORY
Revision Release Date Summary
1.0 2018/11/19 First release.
1.1 2019/05/02 Modify hardware EQ function for playback path
1.2 2019/05/13 Typo corrections

Audio Codec with USB To I2S Audio Controller and ii Track ID: JATR-8275-15 Rev. 1.2
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 ALC4050
Datasheet

Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2. FEATURES ......................................................................................................................................................................... 2
2.1. GENERAL HARDWARE FEATURES ................................................................................................................................ 2
2.2. USB CONTROLLER FEATURES ..................................................................................................................................... 3
2.3. MICRO CONTROLLER UNIT .......................................................................................................................................... 4
2.4. CONFIGURABLE GPIO PINS ......................................................................................................................................... 4
2.5. SOFTWARE FEATURES .................................................................................................................................................. 4
3. SYSTEM APPLICATIONS ............................................................................................................................................... 5
4. BLOCK DIAGRAM ........................................................................................................................................................... 6
5. PIN ASSIGNMENTS ......................................................................................................................................................... 7
5.1. PIN ASSIGNMENTS FIGURE ........................................................................................................................................... 7
5.2. PACKAGE AND VERSION IDENTIFICATION .................................................................................................................... 7
6. PIN DESCRIPTIONS......................................................................................................................................................... 8
6.1. I/O TYPE DESCRIPTION ................................................................................................................................................ 8

or 司
6.2. USB TRANSCEIVER INTERFACE ................................................................................................................................... 8

f
6.3. GPIO, UART, DMIC, AND SPI INTERFACE ................................................................................................................. 9

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6.4. I2C INTERFACE ............................................................................................................................................................ 9
6.5.

i a 公
I2S INTERFACE........................................................................................................................................................... 10

t 限
n
6.6. ANALOG I/O............................................................................................................................................................... 10
6.7.

d e 有
FILTER/REFERENCE.................................................................................................................................................... 10

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f
6.8. POWER/GROUND ........................................................................................................................................................ 11
7.

c o n 科
ELECTRICAL CHARACTERISTICS .......................................................................................................................... 12

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7.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 12
7.2. RECOMMENDED OPERATING CONDITION ................................................................................................................... 12
7.3. DC CHARACTERISTICS ............................................................................................................................................... 12
7.4. AC CHARACTERISTICS ............................................................................................................................................... 13

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7.4.1. SPDIF Output Timing........................................................................................................................................... 13
7.4.2. I2C Control Interface ........................................................................................................................................... 14
7.4.3. I2S Master Mode .................................................................................................................................................. 15
7.5.
1 9
ANALOG PERFORMANCE ............................................................................................................................................ 16

0
8.
8.1.
8.2.
2
MECHANICAL DIMENSIONS...................................................................................................................................... 17
MECHANICAL DIMENSIONS – QFN 48 6X6MM OUTLINE ............................................................................................ 17
MECHANICAL DIMENSIONS NOTES ............................................................................................................................ 17
9. APPLICATION CIRCUITS ............................................................................................................................................ 18
10. ORDERING INFORMATION ................................................................................................................................... 18

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Datasheet

List of Tables
TABLE 1. I/O TYPE DESCRIPTION ................................................................................................................................................. 8
TABLE 2. USB TRANSCEIVER INTERFACE .................................................................................................................................... 8
TABLE 3. GPIO, UART, DMIC, AND SPI INTERFACE .................................................................................................................. 9
TABLE 4. I2C INTERFACE ............................................................................................................................................................. 9
TABLE 5. I2S INTERFACE ........................................................................................................................................................... 10
TABLE 6. ANALOG I/O ............................................................................................................................................................... 10
TABLE 7. FILTER/REFERENCE .................................................................................................................................................... 10
TABLE 8. POWER/GROUND......................................................................................................................................................... 11
TABLE 9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................. 12
TABLE 10. RECOMMENDED OPERATING CONDITION ................................................................................................................... 12
TABLE 11. DC CHARACTERISTICS ............................................................................................................................................... 12
TABLE 12. SPDIF OUTPUT TIMING ............................................................................................................................................. 13
TABLE 13. I2C CONTROL INTERFACE .......................................................................................................................................... 14
TABLE 14. I2S MASTER MODE .................................................................................................................................................... 15
TABLE 15. ANALOG PERFORMANCE ............................................................................................................................................ 16
TABLE 16. ORDERING INFORMATION .......................................................................................................................................... 18

f o r
a l
List of Figures
i 公 司
FIGURE 1.

e n t 有 限
BLOCK DIAGRAM ........................................................................................................................................................ 6
FIGURE 2.

i d
PIN ASSIGNMENTS ....................................................................................................................................................... 7

f 技
n
FIGURE 3. SPDIF OUTPUT TIMING ............................................................................................................................................. 13
FIGURE 4.

c o 科
I2C CONTROL INTERFACE ......................................................................................................................................... 14

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FIGURE 5. I2S MASTER MODE TIMING ....................................................................................................................................... 15

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Audio Codec with USB To I2S Audio Controller and iv Track ID: JATR-8275-15 Rev. 1.2
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 ALC4050
Datasheet

1. General Description
The ALC4050 is a single-chip USB 2.0 audio codec with embedded USB 2.0 to I2S and SPDIF interface
for high analog and digital audio performance. The ALC4050 integrates stereo analog input and output,
USB, I2S, I2C, digital microphone, and SPDIF interfaces to support a standard USB audio device class
designed for all major commercial operating systems, e.g., Windows, Linux, and Android.

The ALC4050 features a Class-G type ultra-low-power cap-saving headphone amplifier. It is a high
efficiency audio amplifier with an integrated Class-G voltage converter that enhances efficiency at low
output power. The ALC4050 integrates a USB 2.0 function controller and USB transceiver optimized for
a high data transfer rate, a high speed MCU (Micro Processor Unit), DC-to-DC regulators, digital audio
I2S interface and I2C control interface, and SPI interface into a single chip.

The ALC4050 connects codecs and DACs that typically have digital I2S and are configured by an I2C
interface to a USB host system with programmable capabilities in order to remove the need for complex
audio configuration and operations. The ALC4050 integrates an S/PDIF output interface for external

or 司
compressed audio data decoding.

l f
t i a 公
The ALC4050 Universal Audio Jack, where it not only operates with OMTP and CTIA Headsets, but also

限
e n
as a Line-in/Microphone. The ALC4050 detects OMTP and CTIA headsets with no extra MOSFET or

d 有
i
analog switch required. The ALC4050 provides a ‘Headset Push-Button Control’ function; certain types

n f 科 技
of push button behavior on the headset line can be detected, and control corresponding to individual push

o
c 斯
button behavior can be customized by the Realtek Audio FW according to customer’s requests.

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 ALC4050
Datasheet

2. Features
2.1. General Hardware Features
 Digital-to-Analog Converter with 100dBA SNR

 Analog-to-Digital Converter with 94dBA SNR

 One stereo DAC supports 8K/16K/22.05K/24K/32K/44.1K/48K/96K/176.4K/192K/384KHz Sample

Rate, 16/24/32-bit resolution

 Two stereo ADCs support 8K/16K/22.05K/24K/32K/44.1K/48K/96K/176.4K/192K/384KHz Sample

Rate, 16/24/32-bit resolution

 2nd Gen. Realtek Proprietary Hardware Feed-Forward or Feedback Active Noise Cancellation (ANC)

 Integrates hardware Direct-Stream-Digital (DSD) native decoder (64Fs/128Fs/256Fs) and DSD over
PCM (DoP) decoder and encoder (64Fs/128Fs) for both I2S and headphone outputs


f or 司
Class-G type amplifier for headphone output without DC blocking capacitors


i a l 公
t
9-Band hardware EQ function (HPFx1, BPFx4, LBFx1, Biquadx3) and AGC (Auto Gain Control)

e n
function for playback path

d 有 限

n f i 科 技
6-Band hardware EQ function for recording path (LPFx1, HPFx1, BPFx4)

c o 斯
RTK 奈克瑟
 Microphone input Automatic Gain Control (AGC) function

 0.5mA current consumption for USB suspend and Ultra-Low-Power for headphone playback

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 One S/PDIF Out interface supports 44.1/48/88.2/96/176.4/192KHz sample rate for PCM format
playback and AC-3 format data transfer

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2
 Single-ended analog microphone inputs with volume gain control in 0.375dB per step

 Microphone boost gain settings of 0/10/20/30dB

 Low noise microphone and programmable MICBIAS voltage level

 Analog-to-analog pass-through path with volume gain adjustments

 Audio jack detection feature

 Supports combo jack with stereo headphone output and mono microphone input on a four-conductor
headset jack for CTIA and OMTP type headsets without external components

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 4-Button Headset in-line controls support Android Wired Audio Headset Specification with
customizable multi-function

 External active speaker humming noise cancellation

 One I2S interface supports 8K/16K/22.05K/32K/44.1K/48K/88.2K/96K/176.4K/192K/384kHz

sample rate and , 16/24/32-bit resolution

 I2S digital interface supports TDM format up to 8CH output/input data transfer simultaneously

 I2C control interface supports master mode and slave mode

 Two stereo digital microphone interfaces with shared clock rate support
0.1875M/0.375M/0.75M/1.5M/3M/6MHz

 SPI (Serial Peripheral Interface, Mode 0~Mode 3) connection to serial flash for switching code and
configuration of customized parameters

 UART interface for external devices


f or 司
Embedded 64K Byte flash and 16K Byte OTP for F/W programming


i a l 公
t
Built-in Analog LDO, supports voltage input supply range from 3.0V to 5.0V

d e n 有 限
i
 48-pin QFN ‘Green’ package

o n f 科 技
USBK c Features 斯
RT 奈克瑟
2.2. Controller


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Compliant with USB Specification 2.0 Full-Speed and High-Speed transfer mode

 Compliant with USB Audio Class Specification Rev1.0 and 2.0


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Supports 6 isochronous customizable endpoints for maximum 10 channel streaming, 3 UAC In and 3


2
UAC Out simultaneously

ISO In/Out endpoints support customizable channel configuration for 1/2/3/4/5/6/8 channel mappings

 Supports one endpoint for control transfer and two endpoints for interrupt transfer

 Supports Selective Suspend mode

 Supports USB LPM-L1 protocol

 Supports jack detection, headset’s in-line button, and GPIOs Remote wakeup function in suspend
mode

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 ALC4050
Datasheet
 Internal PLL supports non-crystal design

 Built-in Self-Loop-Back BIST for testing purposes

2.3. Micro Controller Unit

 On-chip high-performance and low-power MCU

 Software controlled connection to USB bus for re-enumeration

 Internal programmable memory support for various Realtek codec and audio configurations

 Watchdog control for MCU reset and interrupt

 Configurable VID (Vendor ID), PID (Product ID), and serial number string

2.4. Configurable GPIO Pins


f or 司
Programmable inputs and outputs for control purposes


i a l 公
t
Toggle PWM LED driver and controller upon firmware or custom driver customizations

d e n 有 限
n f i 科 技
2.5.
o
Software Features
c 斯
RTK 奈克瑟
 Does not require a custom audio driver

 USB Audio Class compliant; operates with native driver in Microsoft Windows XP, VISTA,

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Windows 7, Windows 8, Windows 8.1, and Windows 10

9
 Realtek custom audio driver provides a certified logo driver for Microsoft Windows XP, VISTA,

 2 0 1
Windows 7, Windows 8, Windows 8.1, and Windows 10

Realtek Control Panel (Realtek Audio Manager) for enhanced user experience
 Audio I/O Jack and Device settings and controls
 Application Enhancements for both voice processing and audio post processing and effects
 Reduces audio software development and usage complexity

 Selective suspend function saves power in Standby mode

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 ALC4050
Datasheet

3. System Applications
 USB Docking Station for Notebook, Tablet, PCs

 Mobile Phone audio accessary

 Embedded USB audio applications

 USB Type-C audio headset, microphone, speaker and generic audio accessories

 USB gaming headset and generic audio accessories

f or 司
i a l 公
e nt 有 限
f i d 技
c o n 斯 科
RTK 奈克瑟
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 ALC4050
Datasheet

4. Block Diagram

DMIC_L

RING2 DMIC_R

SLEEVE
BST1
DAC_1 Headphone HPOUT_L
ADC_1 Amplifier HPOUT_R

LINE_L DAC_2
ADC_2
IN2N
USB2.0

Volume

Volume
ADC

DAC
Interface
MIXER

INL1_Vol
REC

Jack
ADC_3 JD0
Dectection
LINE_R
IN3N
ADC_4
INR1_Vol I2C Slave SCL_S
Controller SDA_S
VREF Reference ADC_5
Voltage
DACREF

or 司
I2C Master SCL_M

f
Controller SDA_M
MIC_BIAS1 MICBIAS/ DANC/

l
MIC_BIAS2 Voltage Detection Sidetone Path

t i a 限 公 PLL I2S0_MCLK

n
DMIC

e
DMIC_CLK Interface

有
Digital Audio Interface
DMIC_DAT

f i d
DMIC

技
(I2S/PCM/TDM/SPI/UART/S/PDIF_OUT/GPIO/ DP

n
GPIO_AL/LED_PWM/ANC_SW) USB TRX

科
Interface

o
DMIC_DAT2 DM

c 斯
RTK 奈克瑟
SPI-MISO/GPIO[1]
GPIO_AL[1]
GPIO_AL[0]
SPI-CS#/GPIO[4]
SPI-SCK/GPIO[3]
SPI-MOSI/GPIO[2]

SPI-WP/GPIO[0]

I2S0_SD_OUT
I2S0_SD_IN
CTS/GPIO[8]
RTS/GPIO[7]
TXD/GPIO[6]
RXD/GPIO_AL[2]
LED/GPIO_AL[3]
ANC_SW

I2S_MCLK
I2S0_SCK
I2S0_SCK2

I2S0_WS2
I2S0_WS
S/PDIF_OUT

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Figure 1. Block Diagram

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 ALC4050
Datasheet

5. Pin Assignments
5.1. Pin Assignments Figure

MICBIAS1
MICBIAS2
HPOUT_R

MIC_CAP
MICBIAS1
MICBIAS2
HPOUT_L
HPOUT_R

MIC_CAP
HPOUT_L

MICVDD
MICVDD
CPVREF
CPVREF

RING2
CPVDD

RING2
CPVDD
CPVPP
CPVPP
CBN1
CBP1
CBN1
CBP1
36 35 34 33 32 31 30 29 28 27 26 25
CBP2
CBP2 37 24 SLEEVE
SLEEVE
CBN2
CBN2 38 23 AGND
AGND
CPVEE
CPVEE 39 22 VREF
VREF
RXD/GPIO_AL[2]/JD0
RXD/GPIO_AL[2]/JD0 40 21 AVDD
AVDD
TXD/GPIO[6]/SPDIF_OUT/DMIC_DAT2/SPI-CS#
TXD/GPIO[6]/SPDIF_OUT/DMIC_DAT2/SPI-CS# 41 20 LINE_R
LINE_R
RTS/GPIO[7]/DMIC_CLK
RTS/GPIO[7]/DMIC_CLK 42 19 LINE_L
LINE_L
CTS/GPIO[8]/DMIC_DAT
CTS/GPIO[8]/DMIC_DAT 43 18 DACREF
DACREF
GPIO_AL[3]/LED/ANC
GPIO_AL[3]/LED/ANC SWITCH
SWITCH
I2C_SDA_M/I2C_SDA_S/GPIO[16]
I2C_SDA_M/I2C_SDA_S/GPIO[16]
44
45
ALC4050 17
16
SPI-WP/GPIO[0]
SPI-WP/GPIO[0]
SPI-MOSI/GPIO[2]
SPI-MOSI/GPIO[2]
I2C_SCL_M/I2C_SCL_S/GPIO[17]
I2C_SCL_M/I2C_SCL_S/GPIO[17] 46 LLLLLLL 15 SPI-MISO/GPIO[1]
SPI-MISO/GPIO[1]
VDD_I2S
VDD_I2S 47 TXXXVS 14 SPI-SCK/GPIO[3]
SPI-SCK/GPIO[3]
I2S0_MCLK/GPIO[18]
I2S0_MCLK/GPIO[18] 48 13 SPI-CS#/GPIO[4]
SPI-CS#/GPIO[4]
1 2 3 4 5 6 7 8 9 10 11 12

f or 司
I2S0_SCK/GPIO[19]

I2S0_SD_IN/GPIO[21]
I2S0_SD_OUT/GPIO[22]
I2S0_WS/GPIO[20]

GPIO_AL[1]/CODEC_PWDN
GPIO_AL[0]/IRQ
DV12S
DP
DM
VBUS
RREF
D3V3
I2S0_SCK/GPIO[19]

I2S0_SD_IN/GPIO[21]
I2S0_SD_OUT/GPIO[22]
I2S0_WS/GPIO[20]

GPIO_AL[1]/CODEC_PWDN
GPIO_AL[0]/IRQ
DV12S
DP
DM
VBUS
RREF
D3V3

i a l 公
e nt 有 限
f i d 技
c o n 斯 科
RTK 奈克瑟
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23

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39 22
40 21
41 20
42 Thermal PAD as 19

0 1 9 43 PIN49:DVSS 18
17

2
44
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12

Figure 2. Pin Assignments

5.2. Package and Version Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in ‘TXXXVS’ in Figure 2.

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 ALC4050
Datasheet

6. Pin Descriptions
6.1. I/O Type Description
Table 1. I/O Type Description
I/O Type Description
I Input
O Output
IH Input with internal pull-up 200K
IL Input with internal pull-down 200K
IO Input/Output
IOH Input/Output with internal pull-up 200K
IOL Input/Output with internal pull-down 200K
IOSH Input/Output with Schmitt trigger
IO-U USB related IO
CLK Clock related IO
PWR-O Power output pin
PWR-I Power input pin

or 司
GND Ground related pin

l f
USB Transceiver Interfacetia 公
6.2.
d e n 有 限
n f i 科 技
Table 2. USB Transceiver Interface
Name

c o Type Pin No. Description

斯
RTK 奈克瑟
DP IO-U 8 USB D+ signal
DM IO-U 9 USB D- signal
RREF - 11 External Reference. Requires 1% precision 6.25k or 6.2k resistor to ground

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- Total: 3 Pins

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 ALC4050
Datasheet

6.3. GPIO, UART, DMIC, and SPI Interface

Table 3. GPIO, UART, DMIC, and SPI Interface
Name Type Pin No. Description
GPIO_AL[1]
IOH 5 General purpose input and output; operates even in USB suspend mode
/Codec_PWDN
GPIO_AL[0]
IOH 6 General purpose input and output; operates even in USB suspend mode
/IRQ
SPI-WP# SPI serial flash write protected
IOH 17
/GPIO[0] /General purpose input and output
SPI-MOSI SPI serial data in
IOH 16
/GPIO[2] /General purpose input and output
SPI-MISO SPI serial data out
IOH 15
/GPIO[1] /General purpose input and output
SPI-SCK SPI clock signal
IOH 14
/GPIO[3] /General purpose input and output
SPI-CS# SPI chip select
IOH 13
/GPIO[4] /General purpose input and output
GPIO_AL[3] IOH 44 General purpose input and output; operates even in USB suspend mode

or 司
/LED /LED controller
CTS IOH

l f Clear-to-send handshaking signal

a 公
/GPIO[8] 43 /General purpose input and output
/DMIC_DAT

nt i 限
/Primary DMIC data
RTS

i d
IOH
e 42

技 有
Request-to-send handshaking signal

f
/GPIO[7] /General purpose input and output
/DMIC_CLK
TXD
c o n IOH
斯 科 41
/DMIC clock
Serial data transmit

RTK 奈克瑟
/GPIO[6] /General purpose input and output
/SPDIF_OUT /SPDIF-Out
/DMIC_DAT2 /Secondary DMIC data

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/SPI-CS# /SPI chip select
RXD IOH 40 Serial data receive
/GPIO_AL[2] /General purpose input and output
/JD0

0 1 9 /Jack detection

2
- Total: 12 Pins

6.4. I2C Interface

Table 4. I2C Interface
Name Type Pin No. Description
I2C_SDA_M IO 45 I2C Bus Data – Master
/I2C_SDA_S /I2C Bus Data – Slave
/GPIO[16] /General purpose input and output
I2C_SCL_M IO 46 I2C Bus clock– Master
/I2C_SCL_S /I2C Bus clock – Slave
/GPIO[17] /General purpose input and output
- Total: 2 Pins

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 ALC4050
Datasheet

6.5. I2S Interface

Table 5. I2S Interface
Name Type Pin No. Description
I2S0_SCK IO 1 I2S Clock output
/GPIO[19] /General purpose input and output
I2S0_WS IO 2 I2S channel select
/GPIO[20] /General purpose input and output
I2S0_SD_IN IO 3 I2S data input
/GPIO[21] /General purpose input and output
I2S0_SD_OUT IO 4 I2S data output
/GPIO[22] /General purpose input and output
I2S0_MCLK IO 48 System Master Clock
/GPIO[18] /General purpose input and output
- Total: 5 Pins

6.6. Analog I/O

or 司
Table 6. Analog I/O
Name Type
f
Pin No. Description

l
Characteristic Definition

a 公
RING2 I 25 Combo jack microphone input Analog input
SLEEVE I

nt i24

限
Combo jack microphone input Analog input
LINE_L I

i d e 19

技 有
Line input left channel Analog input

f
LINE_R I 20 Line input right channel Analog input
HPOUT_R

c o n O

斯 科 32 Headphone output Right channel Analog output

RTK 奈克瑟
HPOUT_L O 31 Headphone output Left channel Analog output
- Total: 6 Pins

6.7.
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Filter/Reference

0 1 9 Table 7. Filter/Reference

2
Name Type Pin No. Description Characteristic Definition
VREF R 22 Analog I/O reference voltage Capacitor to analog ground
CPVREF R 30 Analog I/O reference voltage To analog ground
MICBIAS1 O 29 MIC BIAS Voltage output Programmable Analog DC output
MICBIAS2 O 28 MIC BIAS Voltage output Programmable Analog DC output
MIC_CAP I 26 Microphone input reference Capacitor to analog ground
voltage
DACREF O 18 DAC/ADC reference voltage Capacitor to analog ground
CBN1 R 36 Charge pump Bucket Capacitor 2.2µF capacitor to CPN1
CBP1 R 35 Charge pump Bucket Capacitor 2.2µF capacitor to CPP1
CBN2 R 38 Charge pump Bucket Capacitor 2.2µF capacitor to CPN2
CBP2 R 37 Charge pump Bucket Capacitor 2.2µF capacitor to CPP2
- Total: 10 Pins

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6.8. Power/Ground
Table 8. Power/Ground
Name Type Pin No. Description
DV12S PWR-O 7 Regulated 1.2V output for core power
D3V3 PWR-O 12 3.3V power output from integrated VBUS-to-3.3V regulator and I/O interface
VBUS PWR-I 10 USB bus 5.0V power input for integrated multiple regulators. This power pin
can accept 3.3V of USB power input for 3.3V system
VDD_I2S PWR-O 47 VDD_I2S for companion I2S IO power
AVDD PWR-O 21 Analog power
CPVPP PWR-O 33 Charge Pump Positive Voltage Output
CPVDD PWR-O 34 Charge Pump Voltage Output
CPVEE PWR-O 39 Charge Pump Negative Voltage Output
MICVDD PWR-O 27 Microphone bias power
AGND GND 23 Analog ground
Thermal Pad GND 49 DVSS/Power Stage Ground
- Total: 11 Pins

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7. Electrical Characteristics
7.1. Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings
Parameter Symbol Minimum Typical Maximum Units
Power Supplies VBus -0.3 5.0 5.5 V
Digital Power
o
Ambient Operating Ta 0 - +70 C
Temperature
o
Storage Temperature Ts -40 - +125 C
ESD (Electrostatic Discharge)
- Susceptibility Voltage
All Pins Pass 3500V

7.2. Recommended Operating Condition

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Table 10. Recommended Operating Condition
Symbol

l f
Description Min. Typ. Max. Unit

a
VBus Supply Voltage 3.3 5 5.5 V

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DC Characteristics
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c 斯 Table 11. DC Characteristics

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Symbol Description Min. Typ. Max. Unit
VIH Input Voltage High 2 - 3.3 V
VIL Input Voltage Low -0.5 - 0.8 V

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VOH Output Voltage High 2.4 - - V
VOL Output Voltage Low - - 0.4 V
IOH

0 1 9 Output Current High - - 4 mA

2
IOL Output Current Low - - 4 mA

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7.4. AC Characteristics
7.4.1. SPDIF Output Timing
Table 12. SPDIF Output Timing
Parameter Symbol Minimum Typical Maximum Units
SPDIF-OUT Frequency - - 3.072 - MHz
SPDIF-OUT Period Tcycle - 325.6 - ns
SPDIF-OUT Jitter Tjitter - - 4 ns
SPDIF-OUT High Level Width THigh 156.2 (48%) 162.8 (50%) 169.2 (52%) ns (%)
SPDIF-OUT Low Level Width TLow 156.2 (48%) 162.8 (50%) 169.2 (52%) ns (%)
SPDIF-OUT Rising Time Trise - 2.0 - ns
SPDIF-OUT Falling Time Tfall - 2.0 - ns

Tcycle
Thigh Tlow

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VOH
VIH

l f
VIL

t i a 限 公
Vt

n
V OL

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f
Trise Tfall

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7.4.2. I2C Control Interface

Table 13. I2C Control Interface
Parameter Symbol Min Typ Max Units
Clock Low Pulse Duration Tw(9) 1.3 - - µs
Clock High Pulse Duration Tw(10) 0.6 - - µs
Clock Frequency f 0 - 400(*2) KHz
Setup Time for a Repeated START Condition Tsu(6) 600 - - ns
Start Hold Time Th(5) 600 - - ns
Data Setup Time Tsu(7) 100 - - ns
Data Hold Time Th(6) - - 900 ns
Rising Time Tr - - 300 ns
Falling Time Tf - - 300 ns
Setup Time Tsu(8) 600 - - ns
Bus Free Time Between a STOP and START
Tbuf 1.3 - - µs
Condition
Pulse Width of Spikes Suppressed Input Filter Tsp 0 - 50 ns
Note 1: The host must apply the MCLK clock during I2C control interface access.

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Note 2: If MCLK provides 256*8KHz, I2C clock frequency only can support 400 KHz

f
Note 3: There is no need for MCLK in I2C communications.

l
t i a 限 公
n
Tsp Tsu(6)

e
Th(6)

有
Tbuf
SDA Th(5)

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SCL Tsu(7)
Tw(10)
Tw(9) Tsu(8)

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Re-
Start Tr Start Stop Start
Tf

0 1 9 Figure 4. I2C Control Interface

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7.4.3. I2S Master Mode

Table 14. I2S Master Mode
Parameter Symbol Min Typ Max Units
LRCK output to BCLK delay tLRD - - 30 ns
Data output to BCLK delay tADD - - 30 ns
Data input Setup time tDAS 10 - - ns
Data input Hold time tDAH 10 - - ns

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7.5. Analog Performance

Standard Test Conditions • Tambient=25°C, VBUS=5.0V ±5%
• 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
• 10KΩ/50pF load; Test bench Characterization BW: 20Hz~22kHz

Table 15. Analog Performance

Parameter Min Typ Max Units
Full-Scale Input Voltage
All ADC (Gain=0dB) - 0.6 -
Vrms
Line Input - 0.6 -
MIC Input - 0.6 -
Full-Scale Output Voltage
All DAC (Gain=0dB) - 1.0 -
Headphone Out @10KΩ load - 1.0 - Vrms
Headphone Out @32Ω load - 1.0 -
Headphone Out @16Ω Load - 0.9 -

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SNR (A Weighted)
ADC

l f - 94 -

a
DAC - 100 -
Headphone Out @16Ω Load

nt i 限 公 - 98 - dB FSA

e
- 98 -

有
Headphone Out @32Ω Load

i d
MIC_IN to Stereo ADC with 0dB

f 技
- 93 -

n 科
LINE_IN to stereo ADC with 0dB - 93 -

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Total Harmonic Distortion Plus Noise, THD+N

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ADC - -84 -
DAC - -85 - dB FS
Headphone Out @16Ω Load - -81 -

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Headphone Out @32Ω Load - -81 -
Frequency Response
ADC (-3dB lower edge, -1dB higher edge) 10 - 0.454*Fs Hz

0 1 9
DAC (-3dB lower edge, -1dB higher edge) 10 - 0.454*Fs

2
Crosstalk - -80 - dB
Current consumption @ Idle(HID only) - 14 - mA
Current consumption @ Idle(DAC+ADC) - 24.5 - mA
Current consumption @ Active - 27.5 - mA
Current consumption @ Suspend - 495 - µA
Note: FSA=Full-Scale with A-weighting filter. FS=Full-Scale.

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8. Mechanical Dimensions
8.1. Mechanical Dimensions – QFN 48 6x6mm Outline

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8.2. 杭州 Dimensions
Mechanical
0 7 3 0 Notes
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20
Symbol Dimension in mm Dimension in inch
Min Nom Max Min Nom Max
A 0.75 0.85 1.00 0.030 0.034 0.039
A1 0.00 0.02 0.05 0.000 0.001 0.002
A3 0.20 REF 0.008 REF
b 0.15 0.20 0.25 0.006 0.008 0.010
D/E 6.00BSC 0.236BSC
D2/E2 4.15 4.4 4.65 0.163 0.173 0.183
e 0.40BSC 0.016BSC
L 0.30 0.40 0.50 0.012 0.016 0.020
Notes: CONTROLLING DIMENSION: MILLIMETER (mm).
REFERENCE DOCUMENT: JEDEC MO-220

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9. Application Circuits
To guarantee the best compatibility and performance quality in hardware design with specific
requirements, please contact Realtek to receive the latest application circuits. Any modification made to
the reference circuits is recommended to be reviewed by Realtek. Realtek may update the latest
application circuits without modifying this datasheet.

10. Ordering Information

Table 16. Ordering Information
Part Number Package Status
ALC4050-VA1-CG MQFN-48 ‘Green’ Package (6mm x 6mm) MP

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Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
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